aboutsummaryrefslogtreecommitdiffstats
path: root/doc
diff options
context:
space:
mode:
Diffstat (limited to 'doc')
-rw-r--r--doc/README.atmel_mci4
-rw-r--r--doc/README.cfi4
-rw-r--r--doc/README.davinci2
-rw-r--r--doc/README.generic_usb_ohci2
-rw-r--r--doc/README.mpc85xx16
-rw-r--r--doc/README.nand2
-rw-r--r--doc/README.serial_multi2
-rw-r--r--doc/arch/m68k.rst18
-rw-r--r--doc/develop/driver-model/migration.rst2
-rw-r--r--doc/device-tree-bindings/video/exynos-dp.txt4
-rw-r--r--doc/device-tree-bindings/video/exynos-fb.txt10
-rw-r--r--doc/imx/common/imx5.txt2
-rw-r--r--doc/usage/environment.rst6
13 files changed, 37 insertions, 37 deletions
diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci
index 00e64ba0c7d..0b6d2c53db7 100644
--- a/doc/README.atmel_mci
+++ b/doc/README.atmel_mci
@@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd)
/* this is a weak define that we are overriding */
int board_mmc_getcd(struct mmc *mmc)
{
- return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
+ return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN);
}
#endif
@@ -70,5 +70,5 @@ and the board definition files needs:
/* SD/MMC card */
#define CONFIG_GENERIC_ATMEL_MCI 1
#define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */
-#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9
+#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9
#define CONFIG_CMD_MMC 1
diff --git a/doc/README.cfi b/doc/README.cfi
index ad52850818f..38185747028 100644
--- a/doc/README.cfi
+++ b/doc/README.cfi
@@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly:
void flash_cmd_reset(flash_info_t *info)
{
/*
- * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and
* needs the Spansion type reset commands. The other flash chip
* is located behind a FPGA (Xilinx DS617) and needs the Intel type
* reset command.
*/
- if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ if (info->start[0] == CFG_SYS_FLASH_BASE)
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
else
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
diff --git a/doc/README.davinci b/doc/README.davinci
index 607531af2a8..326efa0a2d6 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138
Davinci special defines
=======================
-CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode
+CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode
need a "NOR Boot Configuration Word" stored
in the NOR Flash. This define adds this.
More Info about this, see:
diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
index 82fea6201d6..767614cbc6d 100644
--- a/doc/README.generic_usb_ohci
+++ b/doc/README.generic_usb_ohci
@@ -11,7 +11,7 @@ Configuration options
CONFIG_USB_OHCI_NEW: enable the new OHCI driver
- CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
+ CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
registers
CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name
diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index 3c6ebbdb0e6..bafffe6dc51 100644
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx
@@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) Invalidate unproctected TLB Entries
@@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
8) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
@@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
#if defined(CONFIG_NXP_ESBC)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
Location : Label "create_init_ram_area"
TLB Entry : 15
#if defined(CONFIG_NXP_ESBC)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
12) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
diff --git a/doc/README.nand b/doc/README.nand
index a3c3ab4b950..37657512533 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -134,7 +134,7 @@ Configuration Options:
chip.IO_ADDR_R = ...;
chip.IO_ADDR_W = ...;
- if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
+ if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
error out
/*
diff --git a/doc/README.serial_multi b/doc/README.serial_multi
index c9049fd01d6..0446fe95937 100644
--- a/doc/README.serial_multi
+++ b/doc/README.serial_multi
@@ -35,7 +35,7 @@ just after switching the console:
setenv sout serial_scc; setenv baudrate 38400
After that press 'enter' at the SCC console. Note that baudrates <38400
-are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in
+are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in
include/configs/lwmon.h).
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 584503eb12e..770327fea21 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -112,16 +112,16 @@ CONFIG_M5272:
Other options, generally set inside include/configs/<boardname>.h, they may
apply to one or more cpu for the ColdFire family:
-CONFIG_SYS_MBAR:
+CFG_SYS_MBAR:
defines the base address of the MCF5272 configuration registers
-CONFIG_SYS_SCR:
+CFG_SYS_SCR:
defines the contents of the System Configuration Register
-CONFIG_SYS_SPR:
+CFG_SYS_SPR:
defines the contents of the System Protection Register
-CONFIG_SYS_MFD:
+CFG_SYS_MFD:
defines the PLL Multiplication Factor Divider
(see table 9-4 of MCF user manual)
-CONFIG_SYS_RFD:
+CFG_SYS_RFD:
defines the PLL Reduce Frequency Devider
(see table 9-4 of MCF user manual)
CONFIG_SYS_CSx_BASE:
@@ -136,9 +136,9 @@ CONFIG_SYS_CSx_RO:
if set to 0 chip select x is read/write else chip select is read only
CONFIG_SYS_CSx_WS:
defines the number of wait states of chip select x
-CONFIG_SYS_CACHE_ICACR:
+CFG_SYS_CACHE_ICACR:
cache-related registers config
-CONFIG_SYS_CACHE_DCACR:
+CFG_SYS_CACHE_DCACR:
cache-related registers config
CONFIG_SYS_CACHE_ACRX:
cache-related registers config
@@ -162,7 +162,7 @@ CFG_SYS_SDRAM_EMOD:
these options are used.
CONFIG_MCFUART:
defines enabling of ColdFire UART driver
-CONFIG_SYS_UART_PORT:
+CFG_SYS_UART_PORT:
defines the UART port to be used (only a single UART can be actually enabled)
-CONFIG_SYS_SBFHDR_SIZE:
+CFG_SYS_SBFHDR_SIZE:
size of the prepended SBF header, if any
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 43665de64f5..fe1ae210def 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015.
Maintainers should submit patches switching over to using CONFIG_DM_I2C and
other base driver model options in time for inclusion in the 2021.10 release.
-CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER
+CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
--------------------------------------------------
Deadline: 2023.01
diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt
index 464a85302ec..273d8fc7968 100644
--- a/doc/device-tree-bindings/video/exynos-dp.txt
+++ b/doc/device-tree-bindings/video/exynos-dp.txt
@@ -30,9 +30,9 @@ Optional properties:
8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
10(MOBILE_WHITEBAR_64)
samsung,h-sync-polarity: Horizontal Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,v-sync-polarity: Vertical Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,interlaced: Progressive if 0, else Interlaced
samsung,color-space: input video data format
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt
index b022f6163f1..bff0cecfcfb 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -23,15 +23,15 @@ Board(panel specific):
samsung,vl-height: Height of display area in mm
samsung,vl-clkp: Clock polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-oep: Output Enable polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-hsp: Horizontal Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-vsp: Vertical Sync polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-dp: Data polarity
- CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+ CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-cmd-allow-len: Wait end of frame
samsung,winid: Window number on which data is to be displayed
diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt
index ea0e144cedc..6c8c2e594fb 100644
--- a/doc/imx/common/imx5.txt
+++ b/doc/imx/common/imx5.txt
@@ -16,7 +16,7 @@ i.MX5x SoCs.
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
-1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
This option should be enabled for boards having a SYS_ON_OFF_CTL signal
connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
reference designs.
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 15897f63dd9..83f210d2d05 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -162,7 +162,7 @@ bootm_low
for use by the bootm command. See also "bootm_size"
environment variable. Address defined by "bootm_low" is
also the base of the initial memory mapping for the Linux
- kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+ kernel -- see the description of CFG_SYS_BOOTMAPSZ and
bootm_mapsize.
bootm_mapsize
@@ -170,7 +170,7 @@ bootm_mapsize
This variable is given as a hexadecimal number and it
defines the size of the memory region starting at base
address bootm_low that is accessible by the Linux kernel
- during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used
+ during early boot. If unset, CFG_SYS_BOOTMAPSZ is used
as the default value if it is defined, and bootm_size is
used otherwise.
@@ -228,7 +228,7 @@ initrd_high
is usually what you want since it allows for
maximum initrd size. If for some reason you want to
make sure that the initrd image is loaded below the
- CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+ CFG_SYS_BOOTMAPSZ limit, you can set this environment
variable to a value of "no" or "off" or "0".
Alternatively, you can set it to a maximum upper
address to use (U-Boot will still check that it
generated by cgit (git 2.34.1) at 2025-02-27 02:02:17 +0000