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path: root/drivers/i2c/i2c-cdns.c
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Diffstat (limited to 'drivers/i2c/i2c-cdns.c')
-rw-r--r--drivers/i2c/i2c-cdns.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index a650dd69b89..0da9f6f35a9 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -251,24 +251,32 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
u8 *cur_data = data;
struct cdns_i2c_regs *regs = i2c_bus->regs;
u32 ret;
+ bool start = 1;
/* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO);
clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
- /* Check message size against FIFO depth, and set hold bus bit
- * if it is greater than FIFO depth
+ /*
+ * For sequential data load hold the bus.
*/
- if (len > CDNS_I2C_FIFO_DEPTH)
+ if (len > 1)
setbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
/* Clear the interrupts in status register */
writel(CDNS_I2C_INTERRUPTS_MASK, &regs->interrupt_status);
- writel(addr, &regs->address);
+ /* In case of Probe (i.e no data), start the transfer */
+ if (!len)
+ writel(addr, &regs->address);
while (len-- && !is_arbitration_lost(regs)) {
writel(*(cur_data++), &regs->data);
+ /* Trigger write only after loading data */
+ if (start) {
+ writel(addr, &regs->address);
+ start = 0;
+ }
if (len && readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
CDNS_I2C_INTERRUPT_ARBLOST);
@@ -375,7 +383,6 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
curr_recv_count = recv_count;
}
} else if (recv_count && !hold_quirk && !curr_recv_count) {
- writel(addr, &regs->address);
if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
writel(CDNS_I2C_TRANSFER_SIZE,
&regs->transfer_size);
@@ -384,6 +391,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
writel(recv_count, &regs->transfer_size);
curr_recv_count = recv_count;
}
+ writel(addr, &regs->address);
}
}