diff options
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/spi/cadence_ospi_versal.c | 45 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 13 | ||||
| -rw-r--r-- | drivers/spi/mxc_spi.c | 14 | ||||
| -rw-r--r-- | drivers/spi/renesas_rpc_spi.c | 2 | ||||
| -rw-r--r-- | drivers/spi/spi-uclass.c | 4 |
6 files changed, 20 insertions, 60 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fd5cb3694f6..96ea033082b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -420,7 +420,7 @@ config RENESAS_RPC_SPI imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash - on Renesas RCar Gen3 SoCs. This uses driver model and requires a + on Renesas R-Car Gen3 SoCs. This uses driver model and requires a device tree binding to operate. config ROCKCHIP_SFC diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 222f828f54e..dcf28c75596 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -125,49 +125,8 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) return 0; } -#if defined(CONFIG_DM_GPIO) -int cadence_qspi_versal_flash_reset(struct udevice *dev) -{ - struct gpio_desc gpio; - u32 reset_gpio; - int ret; - - /* request gpio and set direction as output set to 1 */ - ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret) { - printf("%s: unable to reset ospi flash device", __func__); - return ret; - } - - reset_gpio = PMIO_NODE_ID_BASE + gpio.offset; - - /* Request for pin */ - xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL); - - /* Enable hysteresis in cmos receiver */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_SCHMITT_CMOS, - PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL); - - /* Disable Tri-state */ - xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio, - PM_PINCTRL_CONFIG_TRI_STATE, - PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL); - udelay(1); - - /* Set value 0 to pin */ - dm_gpio_set_value(&gpio, 0); - udelay(1); - - /* Set value 1 to pin */ - dm_gpio_set_value(&gpio, 1); - udelay(1); - - return 0; -} -#else -int cadence_qspi_versal_flash_reset(struct udevice *dev) +#if !CONFIG_IS_ENABLED(DM_GPIO) +int cadence_qspi_flash_reset(struct udevice *dev) { /* CRP WPROT */ writel(0, WPROT_CRP); diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9c466f8695e..623904ecdad 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -33,7 +33,7 @@ __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, return 0; } -__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) +__weak int cadence_qspi_flash_reset(struct udevice *dev) { return 0; } @@ -251,15 +251,10 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - /* Versal and Versal-NET use spi calibration to set read delay */ - if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || - CONFIG_IS_ENABLED(ARCH_VERSAL2)) - if (priv->read_delay >= 0) - priv->read_delay = -1; - /* Reset ospi flash device */ - return cadence_qspi_versal_flash_reset(bus); + return cadence_qspi_flash_reset(bus); + + return 0; } static int cadence_spi_remove(struct udevice *dev) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 9ab39a188b2..2c9b0ada87b 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -115,6 +115,9 @@ struct mxc_spi_slave { #if defined(MXC_ECSPI) u32 cfg_reg; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif int gpio; int ss_pol; unsigned int max_hz; @@ -214,7 +217,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) #ifdef MXC_ECSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { +#if CONFIG_IS_ENABLED(CLK) + u32 clk_src = clk_get_rate(&mxcs->clk); +#else u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); +#endif s32 reg_ctrl, reg_config; u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; u32 pre_div = 0, post_div = 0; @@ -599,14 +606,13 @@ static int mxc_spi_probe(struct udevice *bus) return -ENODEV; #if CONFIG_IS_ENABLED(CLK) - struct clk clk; - ret = clk_get_by_index(bus, 0, &clk); + ret = clk_get_by_index(bus, 0, &mxcs->clk); if (ret) return ret; - clk_enable(&clk); + clk_enable(&mxcs->clk); - mxcs->max_hz = clk_get_rate(&clk); + mxcs->max_hz = clk_get_rate(&mxcs->clk); #else int node = dev_of_offset(bus); const void *blob = gd->fdt_blob; diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index f1e6f9f4e01..7103d786c7e 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 RPC QSPI driver + * Renesas R-Car Gen3 RPC QSPI driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 36b7d383aa9..d6049753740 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -446,7 +446,7 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave = dev_get_parent_priv(dev); bus_data = dev_get_uclass_priv(bus); -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) { dev_err(dev, "controller doesn't support multi CS\n"); return -EINVAL; @@ -515,7 +515,7 @@ int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) int mode = 0; int value; -#if CONFIG_IS_ENABLED(SPI_ADVANCE) +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) int ret; ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); |