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-rw-r--r--drivers/video/anx9804.c103
-rw-r--r--drivers/video/anx9804.h5
-rw-r--r--drivers/video/sunxi/sunxi_display.c55
3 files changed, 93 insertions, 70 deletions
diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c
index 3037ff39b41..52b5988ba5f 100644
--- a/drivers/video/anx9804.c
+++ b/drivers/video/anx9804.c
@@ -21,18 +21,23 @@
* This function will init an anx9804 parallel lcd to dp bridge chip
* using the passed in parameters.
*
- * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
+ * @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
* @lanes: Number of displayport lanes to use
* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
* @bpp: Bits per pixel, must be 18 or 24
*/
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
{
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- u8 c, colordepth;
- int i;
+ struct udevice *chip0, *chip1;
+ int c, colordepth, i, ret;
- i2c_set_bus_num(i2c_bus);
+ ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
+ if (ret)
+ return;
+
+ ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
+ if (ret)
+ return;
if (bpp == 18)
colordepth = 0x00; /* 6 bit */
@@ -40,24 +45,23 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
colordepth = 0x10; /* 8 bit */
/* Reset */
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
mdelay(100);
- i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
/* Write 0 to the powerdown reg (powerup everything) */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
- c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
+ c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
if (c != 0x98) {
printf("Error anx9804 chipid mismatch\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
- i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
- c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
+ c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
break;
@@ -66,51 +70,51 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
if (i == 100)
printf("Error anx9804 clock is not stable\n");
- i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
/* Set a bunch of analog related register values */
- i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
- i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
- i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
- i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
- i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
+ dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
+ dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
+ dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
/* Force HPD */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
/* Power up and configure lanes */
- i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
- i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
+ dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
/* Reset AUX CH */
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
- i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
- ANX9804_RST_CTRL2_AC_MODE);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
+ dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE);
/* Powerdown audio and some other unused bits */
- i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
- i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
- i2c_reg_write(0x38, 0xa7, 0x00);
+ dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
+ dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
+ dm_i2c_reg_write(chip0, 0xa7, 0x00);
/* Set data-rate / lanes */
- i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
- i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
+ dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
/* Link training */
- i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
- ANX9804_LINK_TRAINING_CTRL_EN);
+ dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
+ ANX9804_LINK_TRAINING_CTRL_EN);
mdelay(5);
for (i = 0; i < 100; i++) {
- c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
+ c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
if ((c & 0x01) == 0)
break;
@@ -118,17 +122,14 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
}
if(i == 100) {
printf("Error anx9804 link training timeout\n");
- i2c_set_bus_num(orig_i2c_bus);
return;
}
/* Enable */
- i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
- ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
+ dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
+ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
/* Force stream valid */
- i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
- ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
- ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
-
- i2c_set_bus_num(orig_i2c_bus);
+ dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
+ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
}
diff --git a/drivers/video/anx9804.h b/drivers/video/anx9804.h
index c0fe3b393b4..ea6c9f2d558 100644
--- a/drivers/video/anx9804.h
+++ b/drivers/video/anx9804.h
@@ -16,9 +16,10 @@
#define ANX9804_DATA_RATE_2700M 0x0a
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
+void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
#else
-static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
+static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate,
int bpp) {}
#endif
+
#endif
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c
index da3e8988296..5a21f7af668 100644
--- a/drivers/video/sunxi/sunxi_display.c
+++ b/drivers/video/sunxi/sunxi_display.c
@@ -901,6 +901,42 @@ static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
}
#endif /* CONFIG_VIDEO_LCD_SSD2828 */
+#ifdef CONFIG_VIDEO_LCD_PANEL_I2C
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display)
+{
+ const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME;
+ struct udevice *i2c_bus;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus);
+ if (ret)
+ return;
+
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
+ /*
+ * The anx9804 needs 1.8V from eldo3, we do this here
+ * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
+ * to avoid turning this on when using hdmi output.
+ */
+ axp_set_eldo(3, 1800);
+ anx9804_init(i2c_bus, 4,
+ ANX9804_DATA_RATE_1620M,
+ sunxi_display->depth);
+ }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ struct udevice *chip;
+
+ ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip);
+ if (ret)
+ return;
+
+ dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */
+ }
+}
+#else
+static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {}
+#endif
+
static void sunxi_engines_init(void)
{
sunxi_composer_init();
@@ -935,27 +971,12 @@ static void sunxi_mode_set(struct sunxi_display_priv *sunxi_display,
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
- if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
- /*
- * The anx9804 needs 1.8V from eldo3, we do this here
- * and not via CONFIG_AXP_ELDO3_VOLT from board_init()
- * to avoid turning this on when using hdmi output.
- */
- axp_set_eldo(3, 1800);
- anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
- ANX9804_DATA_RATE_1620M,
- sunxi_display->depth);
- }
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
- if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
- unsigned int orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
- i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
- i2c_set_bus_num(orig_i2c_bus);
- }
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C))
+ sunxi_panel_i2c_init(sunxi_display);
sunxi_composer_mode_set(mode, address, monitor);
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
sunxi_composer_enable();
generated by cgit (git 2.34.1) at 2025-02-28 10:46:29 +0000