diff options
Diffstat (limited to 'drivers')
154 files changed, 12613 insertions, 1461 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 4fbb63a148a..29ceab849c0 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -1,6 +1,7 @@ config AHCI bool "Support SATA controllers with driver model" depends on DM + select BLK help This enables a uclass for disk controllers in U-Boot. Various driver types can use this, such as AHCI/SATA. It does not provide any standard @@ -9,6 +10,7 @@ config AHCI config SATA bool "Support SATA controllers" + select BLK help This enables support for SATA (Serial Advanced Technology Attachment), a serial bus standard for connecting to hard drives and diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 5283d8981e0..cc75bad02b8 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -1,8 +1,5 @@ config BLK - bool # "Support block devices" - depends on DM - def_bool y if MMC || USB || SCSI || NVME || IDE || AHCI || SATA - def_bool y if EFI_MEDIA || VIRTIO_BLK || PVBLOCK + bool help Enable support for block devices, such as SCSI, MMC and USB flash sticks. These provide a block-level interface which permits @@ -100,6 +97,7 @@ config TPL_BLOCK_CACHE config EFI_MEDIA bool "Support EFI media drivers" default y if EFI || SANDBOX + select BLK help Enable this to support media devices on top of UEFI. This enables just the uclass so you also need a specific driver to make this do @@ -139,6 +137,7 @@ endif # EFI_MEDIA config IDE bool "Support IDE controllers" + select BLK help Enables support for IDE (Integrated Drive Electronics) hard drives. This allows access to raw blocks and filesystems on an IDE drive diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index ad7fed3ddaa..f9f0948ae09 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -15,6 +15,7 @@ #include <power/pmic.h> #include <spmi/spmi.h> #include <linux/bitops.h> +#include <time.h> #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5 @@ -31,6 +32,7 @@ struct qcom_pmic_btn_priv { u32 status_bit; int code; struct udevice *pmic; + ulong last_release_time; }; #define PON_INT_RT_STS 0x10 @@ -42,13 +44,21 @@ struct qcom_pmic_btn_priv { static enum button_state_t qcom_pwrkey_get_state(struct udevice *dev) { struct qcom_pmic_btn_priv *priv = dev_get_priv(dev); + bool pressed; + int reg; - int reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS); + if (get_timer_us(0) - priv->last_release_time < 25000) + return BUTTON_OFF; + reg = pmic_reg_read(priv->pmic, priv->base + PON_INT_RT_STS); if (reg < 0) return 0; - return (reg & BIT(priv->status_bit)) != 0; + pressed = !!(reg & BIT(priv->status_bit)); + if (!pressed) + priv->last_release_time = get_timer_us(0); + + return pressed; } static int qcom_pwrkey_get_code(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0c796a1788a..94fc5e51456 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -186,7 +186,7 @@ static const int pwm_parents[] = { CLK_TOP_UNIVPLL2_D4 }; -static const int f10m_ref_parents[] = { +static const int sgmii_ref_1_parents[] = { CLK_XTAL, CLK_TOP_SGMIIPLL_D2 }; @@ -369,7 +369,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), @@ -412,7 +412,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_8 */ MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; @@ -574,6 +574,18 @@ static const struct mtk_clk_tree mt7629_clk_tree = { .muxes = top_muxes, }; +static const struct mtk_clk_tree mt7629_peri_clk_tree = { + .xtal_rate = 40 * MHZ, + .xtal2_rate = 20 * MHZ, + .gates_offs = CLK_PERI_PWM1_PD, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + static int mt7629_mcucfg_probe(struct udevice *dev) { void __iomem *base; @@ -619,7 +631,7 @@ static int mt7629_infracfg_probe(struct udevice *dev) static int mt7629_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs); + return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs); } static int mt7629_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h index c06a51ecd43..6b74fc5f16b 100644 --- a/drivers/clk/mpc83xx_clk.h +++ b/drivers/clk/mpc83xx_clk.h @@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im) } /** - * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed + * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed * @im: Pointer to the MPC83xx main register map in question * * Return: The CSB clock speed value as a 32-bit number. diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d76fca5dba4..cb867acc48c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -47,6 +47,14 @@ config CLK_QCOM_QCS404 on the Snapdragon QCS404 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SA8775P + bool "Qualcomm SA8775 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SA8775 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SDM845 bool "Qualcomm SDM845 GCC" select CLK_QCOM @@ -103,6 +111,14 @@ config CLK_QCOM_SC7280 on the Snapdragon SC7280 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_X1E80100 + bool "Qualcomm X1E80100 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon X1E80100 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + endmenu endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab33f1c5faf..1bc0f15005b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -9,9 +9,11 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o +obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o +obj-$(CONFIG_CLK_QCOM_X1E80100) += clock-x1e80100.o diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 25ca67e537d..7687bbe6a23 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, clk_bcr_update(base + cmd_rcgr); } +#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + cmd_rcgr); + cfg &= ~(PHY_MUX_MASK); + if (enabled) + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC); + else + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC); + + writel(cfg, base + cmd_rcgr); +} + const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { if (!f) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 78d9b1d81ec..ff336dea39c 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -6,6 +6,7 @@ #define _CLOCK_QCOM_H #include <asm/io.h> +#include <linux/bitfield.h> #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c new file mode 100644 index 00000000000..e31f24ed4f0 --- /dev/null +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock drivers for Qualcomm sa8775p + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include "clock-qcom.h" + +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 + +static ulong sa8775p_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate); + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return rate; + case GCC_USB30_PRIM_MASTER_CLK: + WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8); + clk_rcg_set_rate(priv->base, 0xf064, 0, 0); + return rate; + default: + return 0; + } +} + +static const struct gate_clk sa8775p_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1), + GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1), +}; + +static int sa8775p_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map sa8775p_gcc_resets[] = { + [GCC_CAMERA_BCR] = { 0x32000 }, + [GCC_DISPLAY1_BCR] = { 0xC7000 }, + [GCC_DISPLAY_BCR] = { 0x33000 }, + [GCC_EMAC0_BCR] = { 0xB6000 }, + [GCC_EMAC1_BCR] = { 0xB4000 }, + [GCC_GPU_BCR] = { 0x7D000 }, + [GCC_MMSS_BCR] = { 0x17000 }, + [GCC_PCIE_0_BCR] = { 0xa9000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 }, + [GCC_PCIE_0_PHY_BCR] = { 0xAD144 }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C }, + [GCC_PCIE_1_BCR] = { 0x77000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 }, + [GCC_PCIE_1_PHY_BCR] = { 0xAE08C }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 }, + [GCC_PDM_BCR] = { 0x3F000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 }, + [GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 }, + [GCC_SDCC1_BCR] = { 0x20000 }, + [GCC_TSCSS_BCR] = { 0x21000 }, + [GCC_UFS_CARD_BCR] = { 0x81000 }, + [GCC_UFS_PHY_BCR] = { 0x83000 }, +}; + +static const struct qcom_power_map sa8775p_gdscs[] = { + [UFS_PHY_GDSC] = { 0x83004 }, + [USB30_PRIM_GDSC] = { 0x1B004 }, +}; + +static struct msm_clk_data sa8775_gcc_data = { + .resets = sa8775p_gcc_resets, + .num_resets = ARRAY_SIZE(sa8775p_gcc_resets), + .clks = sa8775p_clks, + .num_clks = ARRAY_SIZE(sa8775p_clks), + + .power_domains = sa8775p_gdscs, + .num_power_domains = ARRAY_SIZE(sa8775p_gdscs), + + .enable = sa8775p_enable, + .set_rate = sa8775p_set_rate, +}; + +static const struct udevice_id gcc_sa8775p_of_match[] = { + { + .compatible = "qcom,sa8775p-gcc", + .data = (ulong)&sa8775_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_sa8775p) = { + .name = "gcc_sa8775p", + .id = UCLASS_NOP, + .of_match = gcc_sa8775p_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7..62b5a409e8e 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8550_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b243..9baaecb571f 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; } qcom_gate_clk_en(priv, clk->id); diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c new file mode 100644 index 00000000000..bd9c6ed1c8a --- /dev/null +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm x1e80100 + * + * (C) Copyright 2024 Linaro Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> + +#include "clock-qcom.h" + +/* On-board TCXO, TOFIX get from DT */ +#define TCXO_RATE 38400000 + +/* bi_tcxo_div2 divided after RPMh output */ +#define TCXO_DIV2_RATE (TCXO_RATE / 2) + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ + { } +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + +static ulong x1e80100_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + switch (clk->id) { + case GCC_QUPV3_WRAP2_S5_CLK: /* UART21 */ + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s4_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x1e500, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_SDCC2_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x14018, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MASTER_CLK: + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3902c, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_USB30_PRIM_MOCK_UTMI_CLK: + clk_rcg_set_rate(priv->base, 0x39044, 0, 0); + return TCXO_DIV2_RATE; + case GCC_PCIE_4_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b080, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_4_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_6A_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3108c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_6A_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src); + return freq->freq; + default: + return 0; + } +} + +static const struct gate_clk x1e80100_clks[] = { + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)), + GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)), + GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)), + GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)), + GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)), + GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)), + GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)), + GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)), + GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), + GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), + GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)), + GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)), + GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)), + GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)), + GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), +}; + +static int x1e80100_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_AGGRE_USB3_PRIM_AXI_CLK: + qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); + fallthrough; + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + break; + case GCC_PCIE_4_PIPE_CLK: + // GCC_PCIE_4_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b07c, true); + break; + case GCC_PCIE_6A_PIPE_CLK: + // GCC_PCIE_6A_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x31088, true); + break; + } + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map x1e80100_gcc_resets[] = { + [GCC_AV1E_BCR] = { 0x4a000 }, + [GCC_CAMERA_BCR] = { 0x26000 }, + [GCC_DISPLAY_BCR] = { 0x27000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, + [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, + [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, + [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, + [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, + [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, + [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, + [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 }, + [GCC_PCIE_2_PHY_BCR] = { 0xa501c }, + [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 }, + [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 }, + [GCC_PCIE_3_BCR] = { 0x58000 }, + [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 }, + [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 }, + [GCC_PCIE_3_PHY_BCR] = { 0xab01c }, + [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 }, + [GCC_PCIE_4_BCR] = { 0x6b000 }, + [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 }, + [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 }, + [GCC_PCIE_4_PHY_BCR] = { 0xb301c }, + [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 }, + [GCC_PCIE_5_BCR] = { 0x2f000 }, + [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 }, + [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 }, + [GCC_PCIE_5_PHY_BCR] = { 0xaa01c }, + [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 }, + [GCC_PCIE_6A_BCR] = { 0x31000 }, + [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 }, + [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 }, + [GCC_PCIE_6A_PHY_BCR] = { 0xac01c }, + [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 }, + [GCC_PCIE_6B_BCR] = { 0x8d000 }, + [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 }, + [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 }, + [GCC_PCIE_6B_PHY_BCR] = { 0xb501c }, + [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 }, + [GCC_PCIE_PHY_BCR] = { 0x6f000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, + [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, + [GCC_PCIE_RSCC_BCR] = { 0xa4000 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, + [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c }, + [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 }, + [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB20_PRIM_BCR] = { 0x29000 }, + [GCC_USB30_MP_BCR] = { 0x17000 }, + [GCC_USB30_PRIM_BCR] = { 0x39000 }, + [GCC_USB30_SEC_BCR] = { 0xa1000 }, + [GCC_USB30_TERT_BCR] = { 0xa2000 }, + [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 }, + [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 }, + [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 }, + [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 }, + [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 }, + [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 }, + [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 }, + [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 }, + [GCC_USB4_0_BCR] = { 0x9f000 }, + [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 }, + [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 }, + [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 }, + [GCC_USB4_1_BCR] = { 0x2b000 }, + [GCC_USB4_2_BCR] = { 0x11000 }, + [GCC_USB_0_PHY_BCR] = { 0x50020 }, + [GCC_USB_1_PHY_BCR] = { 0x2a020 }, + [GCC_USB_2_PHY_BCR] = { 0xa3020 }, + [GCC_VIDEO_BCR] = { 0x32000 }, +}; + +static const struct qcom_power_map x1e80100_gdscs[] = { + [GCC_PCIE_0_TUNNEL_GDSC] = { 0xa0004 }, + [GCC_PCIE_1_TUNNEL_GDSC] = { 0x2c004 }, + [GCC_PCIE_2_TUNNEL_GDSC] = { 0x13004 }, + [GCC_PCIE_3_GDSC] = { 0x58004 }, + [GCC_PCIE_3_PHY_GDSC] = { 0x3e000 }, + [GCC_PCIE_4_GDSC] = { 0x6b004 }, + [GCC_PCIE_4_PHY_GDSC] = { 0x6c000 }, + [GCC_PCIE_5_GDSC] = { 0x2f004 }, + [GCC_PCIE_5_PHY_GDSC] = { 0x30000 }, + [GCC_PCIE_6_PHY_GDSC] = { 0x8e000 }, + [GCC_PCIE_6A_GDSC] = { 0x31004 }, + [GCC_PCIE_6B_GDSC] = { 0x8d004 }, + [GCC_UFS_MEM_PHY_GDSC] = { 0x9e000 }, + [GCC_UFS_PHY_GDSC] = { 0x77004 }, + [GCC_USB20_PRIM_GDSC] = { 0x29004 }, + [GCC_USB30_MP_GDSC] = { 0x17004 }, + [GCC_USB30_PRIM_GDSC] = { 0x39004 }, + [GCC_USB30_SEC_GDSC] = { 0xa1004 }, + [GCC_USB30_TERT_GDSC] = { 0xa2004 }, + [GCC_USB3_MP_SS0_PHY_GDSC] = { 0x1900c }, + [GCC_USB3_MP_SS1_PHY_GDSC] = { 0x5400c }, + [GCC_USB4_0_GDSC] = { 0x9f004 }, + [GCC_USB4_1_GDSC] = { 0x2b004 }, + [GCC_USB4_2_GDSC] = { 0x11004 }, + [GCC_USB_0_PHY_GDSC] = { 0x50024 }, + [GCC_USB_1_PHY_GDSC] = { 0x2a024 }, + [GCC_USB_2_PHY_GDSC] = { 0xa3024 }, +}; + +static struct msm_clk_data x1e80100_gcc_data = { + .resets = x1e80100_gcc_resets, + .num_resets = ARRAY_SIZE(x1e80100_gcc_resets), + .clks = x1e80100_clks, + .num_clks = ARRAY_SIZE(x1e80100_clks), + .power_domains = x1e80100_gdscs, + .num_power_domains = ARRAY_SIZE(x1e80100_gdscs), + + .enable = x1e80100_enable, + .set_rate = x1e80100_set_rate, +}; + +static const struct udevice_id gcc_x1e80100_of_match[] = { + { + .compatible = "qcom,x1e80100-gcc", + .data = (ulong)&x1e80100_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_x1e80100) = { + .name = "gcc_x1e80100", + .id = UCLASS_NOP, + .of_match = gcc_x1e80100_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +/* TCSRCC */ + +static const struct gate_clk x1e80100_tcsr_clks[] = { + GATE_CLK(TCSR_PCIE_2L_4_CLKREF_EN, 0x15100, BIT(0)), + GATE_CLK(TCSR_PCIE_2L_5_CLKREF_EN, 0x15104, BIT(0)), + GATE_CLK(TCSR_PCIE_8L_CLKREF_EN, 0x15108, BIT(0)), + GATE_CLK(TCSR_USB3_MP0_CLKREF_EN, 0x1510c, BIT(0)), + GATE_CLK(TCSR_USB3_MP1_CLKREF_EN, 0x15110, BIT(0)), + GATE_CLK(TCSR_USB2_1_CLKREF_EN, 0x15114, BIT(0)), + GATE_CLK(TCSR_UFS_PHY_CLKREF_EN, 0x15118, BIT(0)), + GATE_CLK(TCSR_USB4_1_CLKREF_EN, 0x15120, BIT(0)), + GATE_CLK(TCSR_USB4_2_CLKREF_EN, 0x15124, BIT(0)), + GATE_CLK(TCSR_USB2_2_CLKREF_EN, 0x15128, BIT(0)), + GATE_CLK(TCSR_PCIE_4L_CLKREF_EN, 0x1512c, BIT(0)), + GATE_CLK(TCSR_EDP_CLKREF_EN, 0x15130, BIT(0)), +}; + +static struct msm_clk_data x1e80100_tcsrcc_data = { + .clks = x1e80100_tcsr_clks, + .num_clks = ARRAY_SIZE(x1e80100_tcsr_clks), +}; + +static int tcsrcc_x1e80100_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static ulong tcsrcc_x1e80100_clk_get_rate(struct clk *clk) +{ + return TCXO_RATE; +} + +static int tcsrcc_x1e80100_clk_probe(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = data; + + return 0; +} + +static struct clk_ops tcsrcc_x1e80100_clk_ops = { + .enable = tcsrcc_x1e80100_clk_enable, + .get_rate = tcsrcc_x1e80100_clk_get_rate, +}; + +static const struct udevice_id tcsrcc_x1e80100_of_match[] = { + { + .compatible = "qcom,x1e80100-tcsr", + .data = (ulong)&x1e80100_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(tcsrcc_x1e80100) = { + .name = "tcsrcc_x1e80100", + .id = UCLASS_CLK, + .of_match = tcsrcc_x1e80100_of_match, + .ops = &tcsrcc_x1e80100_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = tcsrcc_x1e80100_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index a093027eb0e..12966d02a22 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,20 +5,20 @@ config CLK_RENESAS Enable support for clock present on Renesas SoCs. config CLK_RCAR - bool "Renesas RCar clock driver support" + bool "Renesas R-Car clock driver support" help - Enable common code for clocks on Renesas RCar SoCs. + Enable common code for clocks on Renesas R-Car SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" config CLK_RCAR_GEN2 - bool "Renesas RCar Gen2 clock driver" + bool "Renesas R-Car Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS select CLK_RCAR help - Enable this to support the clocks on Renesas RCar Gen2 SoC. + Enable this to support the clocks on Renesas R-Car Gen2 SoC. config CLK_R8A7790 bool "Renesas R8A7790 clock driver" @@ -51,14 +51,14 @@ config CLK_R8A7794 Enable this to support the clocks on Renesas R8A7794 SoC. config CLK_RCAR_GEN3 - bool "Renesas RCar Gen3 and Gen4 clock driver" + bool "Renesas R-Car Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help - Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs. + Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 bool "Renesas R8A774A1 clock driver" diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 89f2d966746..9b6fce4675c 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen2 CPG MSSR driver + * Renesas R-Car Gen2 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index aa38c0f7dd0..375cc4a4930 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 8862fbc7579..ea33bfd3239 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 35bad7f5f73..39ff4541c1e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 71e409f3eb0..d5db14baf06 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 43c44fadbe7..a4ff1c41abb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa int ret; /* - * If the requested parent is in the same clock-controller and - * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal - * clock. + * If the requested parent is in the same clock-controller the + * likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"), + * switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { + if (parent->dev == clk->dev) { debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); return 0; diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8dc378..880dd4f6ece 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -10,6 +10,9 @@ #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> +#define TEGRA_CAR_CLK_PLL BIT(0) +#define TEGRA_CAR_CLK_PERIPH BIT(1) + static int tegra_car_clk_request(struct clk *clk) { debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, @@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk) * varies per SoC) are the peripheral clocks, which use a numbering * scheme that matches HW registers 1:1. There are other clock IDs * beyond this that are assigned arbitrarily by the Tegra CAR DT - * binding. Due to the implementation of this driver, it currently - * only supports the peripheral IDs. + * binding. */ - if (clk->id >= PERIPH_ID_COUNT) - return -EINVAL; + if (clk->id < PERIPH_ID_COUNT) { + clk->data |= TEGRA_CAR_CLK_PERIPH; + return 0; + } - return 0; + /* If check for periph failed, then check for PLL clock id */ + int id = clk_id_to_pll_id(clk->id); + + if (clock_id_is_pll(id)) { + clk->id = id; + clk->data |= TEGRA_CAR_CLK_PLL; + return 0; + } + + return -EINVAL; } static ulong tegra_car_clk_get_rate(struct clk *clk) { - enum clock_id parent; - debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); - parent = clock_get_periph_parent(clk->id); - return clock_get_periph_rate(clk->id, parent); + if (clk->data & TEGRA_CAR_CLK_PLL) + return clock_get_rate(clk->id); + + if (clk->data & TEGRA_CAR_CLK_PERIPH) { + enum clock_id parent; + + parent = clock_get_periph_parent(clk->id); + return clock_get_periph_rate(clk->id, parent); + } + + return -1U; } static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) @@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + parent = clock_get_periph_parent(clk->id); return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL); } @@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_enable(clk->id); return 0; @@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_disable(clk->id); return 0; @@ -83,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); + clock_init(); + clock_verify(); + return 0; } diff --git a/drivers/core/root.c b/drivers/core/root.c index c7fb58285ca..15b8c83fee9 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -288,26 +288,40 @@ void *dm_priv_to_rw(void *priv) } #endif -static int dm_probe_devices(struct udevice *dev, bool pre_reloc_only) +/** + * dm_probe_devices() - Check whether to probe a device and all children + * + * Probes the device if DM_FLAG_PROBE_AFTER_BIND is enabled for it. Then scans + * all its children recursively to do the same. + * + * @dev: Device to (maybe) probe + * Return 0 if OK, -ve on error + */ +static int dm_probe_devices(struct udevice *dev) { - ofnode node = dev_ofnode(dev); struct udevice *child; - int ret; - - if (pre_reloc_only && - (!ofnode_valid(node) || !ofnode_pre_reloc(node)) && - !(dev->driver->flags & DM_FLAG_PRE_RELOC)) - goto probe_children; if (dev_get_flags(dev) & DM_FLAG_PROBE_AFTER_BIND) { + int ret; + ret = device_probe(dev); if (ret) return ret; } -probe_children: list_for_each_entry(child, &dev->child_head, sibling_node) - dm_probe_devices(child, pre_reloc_only); + dm_probe_devices(child); + + return 0; +} + +int dm_autoprobe(void) +{ + int ret; + + ret = dm_probe_devices(gd->dm_root); + if (ret) + return log_msg_ret("pro", ret); return 0; } @@ -344,7 +358,7 @@ static int dm_scan(bool pre_reloc_only) if (ret) return ret; - return dm_probe_devices(gd->dm_root, pre_reloc_only); + return 0; } int dm_init_and_scan(bool pre_reloc_only) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index c45481bef0b..8f7a821ebf3 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -654,7 +654,7 @@ static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) ret = instantiate_rng(sec_idx, sec, gen_sk); /* * entropy delay is calculated via self-test method. - * self-test are run across different volatge, temp. + * self-test are run across different voltage, temp. * if worst case value for ent_dly is identified, * loop can be skipped for that platform. */ diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile index 592d0c6ebad..95c93ba16d5 100644 --- a/drivers/ddr/imx/phy/Makefile +++ b/drivers/ddr/imx/phy/Makefile @@ -5,5 +5,5 @@ # ifdef CONFIG_XPL_BUILD -obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o endif diff --git a/drivers/ddr/imx/phy/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c deleted file mode 100644 index 67dd4e7059f..00000000000 --- a/drivers/ddr/imx/phy/ddrphy_csr.c +++ /dev/null @@ -1,732 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -/* ddr phy trained csr */ -struct dram_cfg_param ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - 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{ 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c index 2a2161dec33..1a2d071d6f1 100644 --- a/drivers/ddr/imx/phy/ddrphy_train.c +++ b/drivers/ddr/imx/phy/ddrphy_train.c @@ -90,7 +90,8 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing) } /* save the ddr PHY trained CSR in memory for low power use */ - ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); + ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, + dram_timing->ddrphy_trained_csr_num); return 0; } diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index c1fc800f191..b0dfc3a0b4f 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -181,7 +181,7 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; - saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num; saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; /* save the fsp table */ @@ -209,9 +209,9 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved /* save the ddrphy csr */ saved_timing->ddrphy_trained_csr = cfg; - for (i = 0; i < ddrphy_trained_csr_num; i++) { - cfg->reg = ddrphy_trained_csr[i].reg; - cfg->val = ddrphy_trained_csr[i].val; + for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) { + cfg->reg = timing_info->ddrphy_trained_csr[i].reg; + cfg->val = timing_info->ddrphy_trained_csr[i].val; cfg++; } diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index dac4023ccfd..3013c4741d0 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1331,6 +1331,8 @@ static int udma_get_mmrs(struct udevice *dev) continue; if (i == MMR_RCHANRT && ud->rchan_cnt == 0) continue; + if (i == MMR_RFLOW && ud->match_data->type == DMA_TYPE_BCDMA) + continue; ud->mmrs[i] = dev_read_addr_name_ptr(dev, mmr_names[i]); if (!ud->mmrs[i]) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 719cfa771b4..190a1e3f5fc 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -3077,6 +3077,7 @@ U_BOOT_DRIVER(ti_sci) = { .of_match = ti_sci_ids, .probe = ti_sci_probe, .priv_auto = sizeof(struct ti_sci_info), + .flags = DM_FLAG_PRE_RELOC, }; #if IS_ENABLED(CONFIG_K3_DM_FW) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 92a8597420a..f4a453e1cdd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -358,10 +358,10 @@ config PCF8575_GPIO chips are from NXP and TI. config RCAR_GPIO - bool "Renesas RCar GPIO driver" + bool "Renesas R-Car GPIO driver" depends on DM_GPIO && ARCH_RENESAS help - This driver supports the GPIO banks on Renesas RCar SoCs. + This driver supports the GPIO banks on Renesas R-Car SoCs. config RZA1_GPIO bool "Renesas RZ/A1 GPIO driver" diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c index ea0cb75459b..114583b3c3b 100644 --- a/drivers/gpio/adp5585_gpio.c +++ b/drivers/gpio/adp5585_gpio.c @@ -224,7 +224,7 @@ static int adp5585_probe(struct udevice *dev) } static const struct udevice_id adp5585_ids[] = { - { .compatible = "adp5585" }, + { .compatible = "adi,adp5585" }, { } }; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index e9bd38f162c..709d04017d1 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -204,7 +204,17 @@ static int mpc8xxx_gpio_plat_to_priv(struct udevice *dev) return -ENOMEM; priv->gpio_count = plat->ngpios; - priv->dat_shadow = 0; + + /* + * On platforms that do support reading back output values, we want to + * try preserving them, so that we don't accidentally set unrelated + * GPIOs to zero in mpc8xxx_gpio_set_value. + */ + if (priv->little_endian) + priv->dat_shadow = in_le32(&priv->base->gpdat) & in_le32(&priv->base->gpdir); + else + priv->dat_shadow = in_be32(&priv->base->gpdat) & in_be32(&priv->base->gpdir); + priv->type = driver_data; diff --git a/drivers/gpio/npcm_sgpio.c b/drivers/gpio/npcm_sgpio.c index 6d73287c0a2..fcc42087d57 100644 --- a/drivers/gpio/npcm_sgpio.c +++ b/drivers/gpio/npcm_sgpio.c @@ -4,31 +4,47 @@ */ #include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <asm/gpio.h> +#include <linux/err.h> #include <linux/io.h> +#include <asm/arch/rst.h> #define MAX_NR_HW_SGPIO 64 -#define NPCM_CLK_MHZ 8000000 +#define NPCM_SIOX1 24 +#define NPCM_SIOX2 25 -#define NPCM_IOXCFG1 0x2A - -#define NPCM_IOXCTS 0x28 -#define NPCM_IOXCTS_IOXIF_EN BIT(7) -#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) +#define NPCM_IOXCTS 0x28 +#define NPCM_IOXCTS_IOXIF_EN BIT(7) +#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1) #define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2) +#define NPCM_IOXCFG1 0x2A #define NPCM_IOXCFG2 0x2B #define NPCM_IOXCFG2_PORT GENMASK(3, 0) #define GPIO_BANK(x) ((x) / 8) #define GPIO_BIT(x) ((x) % 8) +#define WD0RCR 0x38 +#define WD1RCR 0x3c +#define WD2RCR 0x40 +#define SWRSTC1 0x44 +#define SWRSTC2 0x48 +#define SWRSTC3 0x4c +#define TIPRSTC 0x50 +#define CORSTC 0x5c + struct npcm_sgpio_priv { void __iomem *base; + struct regmap *rst_regmap; u32 nin_sgpio; u32 nout_sgpio; u32 in_port; u32 out_port; + u8 persist[8]; + u8 siox_num; }; struct npcm_sgpio_bank { @@ -185,7 +201,13 @@ static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset) static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset, int value) { - return npcm_sgpio_direction_output(dev, offset, value); + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 check = priv->persist[GPIO_BANK(offset)]; + + if (!!(check & BIT(GPIO_BIT(offset))) == 0) + return npcm_sgpio_direction_output(dev, offset, value); + else + return -EINVAL; } static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset) @@ -213,12 +235,10 @@ static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable) iowrite8(reg, gpio->base + NPCM_IOXCTS); } -static int npcm_sgpio_init_port(struct udevice *dev) +static void npcm_sgpio_set_port(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); - u8 in_port, out_port, set_port, reg, set_clk; - - npcm_sgpio_setup_enable(priv, false); + u8 in_port, out_port; in_port = GPIO_BANK(priv->nin_sgpio); if (GPIO_BIT(priv->nin_sgpio) > 0) @@ -230,8 +250,16 @@ static int npcm_sgpio_init_port(struct udevice *dev) priv->in_port = in_port; priv->out_port = out_port; +} - set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT); +static int npcm_sgpio_init_port(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 set_port, reg, set_clk; + + npcm_sgpio_setup_enable(priv, false); + + set_port = (priv->out_port & NPCM_IOXCFG2_PORT) << 4 | (priv->in_port & NPCM_IOXCFG2_PORT); set_clk = 0x07; iowrite8(set_port, priv->base + NPCM_IOXCFG2); @@ -242,6 +270,61 @@ static int npcm_sgpio_init_port(struct udevice *dev) return reg == set_port ? 0 : -EINVAL; } +static void npcm_sgpio_reset_persist(struct udevice *dev, uint enable) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u8 num; + + if (priv->siox_num == 1) + num = NPCM_SIOX2; + else + num = NPCM_SIOX1; + + if (enable) { + regmap_update_bits(priv->rst_regmap, WD0RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD1RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, WD2RCR, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, CORSTC, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC1, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC2, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, SWRSTC3, BIT(num), 0); + regmap_update_bits(priv->rst_regmap, TIPRSTC, BIT(num), 0); + } +} + +static bool is_gpio_persist(struct udevice *dev) +{ + struct npcm_sgpio_priv *priv = dev_get_priv(dev); + u32 val; + int status; + + status = npcm_get_reset_status(); + + if (status & PORST) + return false; + if (status & CORST) + regmap_read(priv->rst_regmap, CORSTC, &val); + else if (status & WD0RST) + regmap_read(priv->rst_regmap, WD0RCR, &val); + else if (status & WD1RST) + regmap_read(priv->rst_regmap, WD1RCR, &val); + else if (status & WD2RST) + regmap_read(priv->rst_regmap, WD2RCR, &val); + else if (status & SW1RST) + regmap_read(priv->rst_regmap, SWRSTC1, &val); + else if (status & SW2RST) + regmap_read(priv->rst_regmap, SWRSTC2, &val); + else if (status & SW3RST) + regmap_read(priv->rst_regmap, SWRSTC3, &val); + else if (status & TIPRST) + regmap_read(priv->rst_regmap, TIPRSTC, &val); + + if (priv->siox_num == 1) + return (val && BIT(NPCM_SIOX2)); + else + return (val && BIT(NPCM_SIOX1)); +} + static const struct dm_gpio_ops npcm_sgpio_ops = { .direction_input = npcm_sgpio_direction_input, .direction_output = npcm_sgpio_direction_output, @@ -254,23 +337,57 @@ static int npcm_sgpio_probe(struct udevice *dev) { struct npcm_sgpio_priv *priv = dev_get_priv(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - int rc; + int rc, i; + ofnode node; + u32 val[2]; priv->base = dev_read_addr_ptr(dev); + priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst"); + if (IS_ERR(priv->rst_regmap)) + return -EINVAL; + ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio); ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio); if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO) return -EINVAL; - rc = npcm_sgpio_init_port(dev); - if (rc < 0) - return rc; + if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio2@102000")) + priv->siox_num = 1; + else if (!strcmp(ofnode_get_name(dev_ofnode(dev)), "sgpio1@101000")) + priv->siox_num = 0; + else + return -EINVAL; + npcm_sgpio_set_port(dev); uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio; uc_priv->bank_name = dev->name; - npcm_sgpio_setup_enable(priv, true); + if (is_gpio_persist(dev)) { + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) { + rc = ofnode_read_u32_array(node, "gpios", val, 2); + if (rc == 0) + priv->persist[GPIO_BANK(val[0])] = priv->persist[GPIO_BANK(val[0])] | BIT(GPIO_BIT(val[0])); + } + } + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + } else { + rc = npcm_sgpio_init_port(dev); + if (rc < 0) + return rc; + + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (ofnode_read_bool(node, "persist-enable")) + npcm_sgpio_reset_persist(dev, 1); + } + + for (i = 0; i < priv->nout_sgpio; i++) + npcm_sgpio_set_value(dev, i, 0); + + npcm_sgpio_setup_enable(priv, true); + } return 0; } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 52067fa7c1f..cdae6825736 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -504,16 +504,16 @@ config SYS_I2C_OMAP24XX Add support for the OMAP2+ I2C driver. config SYS_I2C_RCAR_I2C - bool "Renesas RCar I2C driver" + bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C help - Support for Renesas RCar I2C controller. + Support for Renesas R-Car I2C controller. config SYS_I2C_RCAR_IIC - bool "Renesas RCar Gen3 IIC driver" + bool "Renesas R-Car Gen3 IIC driver" depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help - Support for Renesas RCar Gen3 IIC controller. + Support for Renesas R-Car Gen3 IIC controller. config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index 2aa0f5fbfae..e019d06be41 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar IIC driver + * Renesas R-Car IIC driver * * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 5eafe46fd4d..6f5ad37919f 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -408,7 +408,7 @@ static int k3_sec_proxy_remove(struct udevice *dev) return 0; } -static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 }; +static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23, 28, 29 }; static const struct k3_sec_proxy_desc am654_desc = { .thread_count = 90, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 6009d55f400..da84b35e804 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -568,7 +568,7 @@ config QFW_MMIO config QFW_SMBIOS bool default y - depends on QFW && SMBIOS && !SANDBOX + depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS help Hidden option to read SMBIOS tables from QEMU. diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index dee0bdd9663..72a13abaaee 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -310,6 +310,7 @@ static int gsc_hwmon(struct udevice *dev) printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10)); break; case 1: /* prescaled voltage */ + case 3: if (val != 0xffff) printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); break; @@ -330,6 +331,9 @@ static int gsc_hwmon(struct udevice *dev) printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); break; + case 4: /* revolutions per minute */ + printf("%-8s: %drpm\n", label, val * 30); + break; } } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f4fdf15242c..4827834b4aa 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -3,7 +3,8 @@ menu "MMC Host controller Support" config MMC bool "MMC/SD/SDIO card support" default ARM || PPC || SANDBOX - select DM_MMC if DM + select BLK + select DM_MMC help This selects MultiMediaCard, Secure Digital and Secure Digital I/O support. @@ -39,14 +40,14 @@ config MMC_BROKEN_CD If card detection feature is broken, just poll to detect. config DM_MMC - bool "Enable MMC controllers using Driver Model" + bool depends on DM help - This enables the MultiMediaCard (MMC) uclass which supports MMC and - Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) - and non-removable (e.g. eMMC chip) devices are supported. These - appear as block devices in U-Boot and can support filesystems such - as EXT4 and FAT. + This enables the MultiMediaCard (MMC) driver model uclass which + supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, + micro-SD, etc.) and non-removable (e.g. eMMC chip) devices are + supported. These appear as block devices in U-Boot and can support + filesystems such as EXT4 and FAT. config SPL_DM_MMC bool "Enable MMC controllers using Driver Model in SPL" @@ -79,7 +80,7 @@ config MMC_SDHCI_ADMA_HELPERS config MMC_SPI bool "Support for SPI-based MMC controller" - depends on DM_MMC && DM_SPI + depends on DM_SPI help This selects SPI-based MMC controllers. If you have an MMC controller on a SPI bus, say Y here. @@ -97,7 +98,6 @@ config MMC_SPI_CRC_ON config ARM_PL180_MMCI bool "ARM AMBA Multimedia Card Interface and compatible support" - depends on DM_MMC help This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card Interface (PL180, PL181 and compatible) support. @@ -258,7 +258,6 @@ config MMC_DW config MMC_DW_CORTINA bool "Cortina specific extensions for Synopsys DW Memory Card Interface" - depends on DM_MMC depends on MMC_DW help This selects support for Cortina SoC specific extensions to the @@ -285,7 +284,7 @@ config MMC_DW_K3 config MMC_DW_ROCKCHIP bool "Rockchip SD/MMC controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL depends on MMC_DW help This enables support for the Rockchip SD/MMM controller, which is @@ -306,7 +305,6 @@ config MMC_DW_SOCFPGA config MMC_DW_SNPS bool "Extensions for DW Memory Card Interface used in Synopsys ARC devboards" depends on MMC_DW - depends on DM_MMC depends on OF_CONTROL depends on CLK help @@ -317,13 +315,12 @@ config NEXELL_DWMMC bool "Nexell SD/MMC controller support" depends on ARCH_NEXELL depends on MMC_DW - depends on DM_MMC depends on PINCTRL_NEXELL default y config MMC_MESON_GX bool "Meson GX EMMC controller support" - depends on DM_MMC && ARCH_MESON + depends on ARCH_MESON help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) @@ -338,7 +335,7 @@ config MMC_MXC config MMC_OWL bool "Actions OWL Multimedia Card Interface support" - depends on ARCH_OWL && DM_MMC && BLK + depends on ARCH_OWL help This selects the OWL SD/MMC host controller found on board based on Actions S700/S900 SoC. @@ -366,7 +363,6 @@ config MMC_PCI config MMC_OCTEONTX bool "Marvell Octeon Multimedia Card Interface support" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) - depends on DM_MMC select MMC_SUPPORTS_TUNING if ARCH_OCTEONTX2 help This selects the Octeon Multimedia card Interface. @@ -377,7 +373,7 @@ config MMC_OCTEONTX config MVEBU_MMC bool "Kirkwood MMC controller support" - depends on DM_MMC && ARCH_KIRKWOOD + depends on ARCH_KIRKWOOD help Support for MMC host controller on Kirkwood SoCs. If you are on a Kirkwood architecture, say Y here. @@ -386,8 +382,7 @@ config MVEBU_MMC config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR - select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR + select DM_REGULATOR_PBIAS if DM_REGULATOR help This selects the TI OMAP High Speed Multimedia card Interface. If you have an omap2plus board with a Multimedia Card slot, @@ -430,7 +425,6 @@ config SH_MMCIF config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER - depends on DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on @@ -439,7 +433,6 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" depends on ARCH_RENESAS - depends on DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER help @@ -449,7 +442,6 @@ config RENESAS_SDHI config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" depends on ARCH_BCM283X - depends on DM_MMC depends on OF_CONTROL default y help @@ -469,7 +461,7 @@ config JZ47XX_MMC config MMC_SANDBOX bool "Sandbox MMC support" depends on SANDBOX - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This select a dummy sandbox MMC driver. At present this does nothing other than allow sandbox to be build with MMC support. This @@ -559,7 +551,6 @@ config FIXED_SDHCI_ALIGNED_BUFFER config MMC_SDHCI_ASPEED bool "Aspeed SDHCI controller" depends on ARCH_ASPEED - depends on DM_MMC depends on MMC_SDHCI select MISC help @@ -571,7 +562,7 @@ config MMC_SDHCI_ASPEED config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 depends on MMC_SDHCI help This enables support for the Atmel SDHCI controller, which supports @@ -606,7 +597,6 @@ config MMC_SDHCI_BCMSTB config MMC_SDHCI_CADENCE bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -618,7 +608,6 @@ config MMC_SDHCI_CADENCE config MMC_SDHCI_CV1800B bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" - depends on DM_MMC depends on MMC_SDHCI depends on OF_CONTROL help @@ -633,7 +622,7 @@ config MMC_SDHCI_AM654 bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 depends on MMC_SDHCI - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on REGMAP select MMC_SDHCI_IO_ACCESSORS help @@ -653,7 +642,6 @@ config MMC_SDHCI_IPROC config MMC_SDHCI_F_SDH30 bool "SDHCI support for Fujitsu Semiconductor/Socionext F_SDH30" - depends on DM_MMC depends on MMC_SDHCI help This selects the Secure Digital Host Controller Interface (SDHCI) @@ -673,7 +661,6 @@ config MMC_SDHCI_KONA config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on DM_MMC depends on MMC_SDHCI help Enables support for SDHCI 2.0 controller present on some Qualcomm @@ -685,7 +672,6 @@ config MMC_SDHCI_MV bool "SDHCI support on Marvell platform" depends on ARCH_MVEBU depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface on Marvell platform. @@ -697,7 +683,6 @@ config MMC_SDHCI_MV config MMC_SDHCI_NPCM bool "SDHCI support on Nuvoton NPCM device" depends on MMC_SDHCI - depends on DM_MMC help This selects the Secure Digital Host Controller Interface (SDHCI) on Nuvoton NPCM device. @@ -708,7 +693,7 @@ config MMC_SDHCI_NPCM config MMC_SDHCI_PIC32 bool "Microchip PIC32 on-chip SDHCI support" - depends on DM_MMC && MACH_PIC32 + depends on MACH_PIC32 depends on MMC_SDHCI help Support for Microchip PIC32 SDHCI controller. @@ -716,7 +701,6 @@ config MMC_SDHCI_PIC32 config MMC_SDHCI_ROCKCHIP bool "Arasan SDHCI controller for Rockchip support" depends on ARCH_ROCKCHIP - depends on DM_MMC && BLK depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform @@ -735,7 +719,6 @@ config MMC_SDHCI_S5P config MMC_SDHCI_SNPS bool "Synopsys DesignWare SDHCI controller" depends on MMC_SDHCI - depends on DM_MMC help Support for DesignWare SDHCI host controller on Alibaba TH1520 SoC. This is a highly configurable and programmable, high performance @@ -753,7 +736,7 @@ config MMC_SDHCI_STI config MMC_SDHCI_XENON bool "SDHCI support for the Xenon SDHCI controller" - depends on MMC_SDHCI && DM_MMC && OF_CONTROL + depends on MMC_SDHCI && OF_CONTROL help Support for Xenon SDHCI host controller on Marvell Armada 3700 7k/8k ARM SoCs platforms @@ -764,7 +747,6 @@ config MMC_SDHCI_XENON config MMC_SDHCI_TANGIER bool "Tangier SDHCI controller support" - depends on DM_MMC && BLK depends on MMC_SDHCI help This selects support for SDHCI controller on Tanginer @@ -800,7 +782,7 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" - depends on DM_MMC && OF_CONTROL && BLK + depends on OF_CONTROL depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform @@ -842,7 +824,6 @@ config MMC_SUNXI_HAS_MODE_SWITCH config MMC_PITON bool "MMC support for OpenPiton SoC" - depends on DM_MMC && BLK help This selects support for the SD host controller on OpenPiton SoC. Note that this SD controller directly exposes the contents of the @@ -851,7 +832,7 @@ config MMC_PITON config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" - depends on DM_MMC && ARCH_AT91 + depends on ARCH_AT91 help This enables support for Atmel High Speed Multimedia Card Interface (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, @@ -860,7 +841,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on DM_MMC && OF_CONTROL + depends on OF_CONTROL help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -880,7 +861,6 @@ config FTSDC010_SDIO config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS - depends on DM_MMC depends on OF_CONTROL help This selects the MediaTek(R) Secure digital and Multimedia card Interface. @@ -911,7 +891,7 @@ config FSL_ESDHC_SUPPORT_ADMA2 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND bool "enable eSDHC workaround for 3.3v IO reliability issue" - depends on FSL_ESDHC && DM_MMC + depends on FSL_ESDHC help When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index efe98354a0f..799586891af 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -750,7 +750,7 @@ static int mmc_send_op_cond(struct mmc *mmc) { int err, i; int timeout = 1000; - uint start; + ulong start; /* Some cards seem to need this */ mmc_go_idle(mmc); @@ -844,7 +844,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, bool send_status) { - unsigned int status, start; + ulong start; + unsigned int status; struct mmc_cmd cmd; int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 92afa6adcda..556f07eaf8f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -571,7 +571,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) int i, ret = 0, sret; u32 caps, reg; - /* Only supported on Renesas RCar */ + /* Only supported on Renesas R-Car */ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) return -EINVAL; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index f489fb70766..657aba75148 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -64,7 +64,7 @@ #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ #define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ -#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ +#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (R-Car ver.) */ #define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ #define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ #define TMIO_SD_SIZE 0x04c /* block size */ @@ -90,7 +90,7 @@ #define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ #define TMIO_SD_DMA_MODE 0x410 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ -#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */ +#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* R-Car, 64bit */ #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ #define TMIO_SD_DMA_CTL 0x414 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ @@ -128,9 +128,9 @@ struct tmio_sd_priv { #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ #define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ #define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ -#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ +#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas R-Car UHS/SDR modes */ #define TMIO_SD_CAP_RCAR \ (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) struct udevice *vqmmc_dev; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 678bbde89e6..185e8346213 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -34,7 +34,7 @@ config MTD_CONCAT config MTD_BLOCK bool "Enable block device access to MTD devices" - depends on BLK + select BLK help Enable support for block device access to MTD devices using blk_ops abstraction. @@ -194,11 +194,11 @@ config ALTERA_QSPI "Embedded Peripherals IP User Guide" of Altera. config RENESAS_RPC_HF - bool "Renesas RCar Gen3 RPC HyperFlash driver" + bool "Renesas R-Car Gen3 RPC HyperFlash driver" depends on RCAR_GEN3 && DM_MTD help This enables access to HyperFlash memory through the Renesas - RCar Gen3 RPC controller. + R-Car Gen3 RPC controller. config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 03545822b07..50a6191d9c2 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 RPC HyperFlash driver + * Renesas R-Car Gen3 RPC HyperFlash driver * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index ec841fb13bd..6f352c5c0e2 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1130,17 +1130,19 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) goto erase_err; } offset = addr; - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; - - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) - nor->spi->flags |= SPI_XFER_U_PAGE; - else - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + + if (nor->flags & SNOR_F_HAS_STACKED) { + if (offset >= (mtd->size / 2)) + nor->spi->flags |= SPI_XFER_U_PAGE; + else + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } } #ifdef CONFIG_SPI_FLASH_BAR - ret = write_bar(nor, addr); + ret = write_bar(nor, offset); if (ret < 0) goto erase_err; #endif @@ -1152,7 +1154,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { ret = spi_nor_erase_chip(nor); } else { - ret = spi_nor_erase_sector(nor, addr); + ret = spi_nor_erase_sector(nor, offset); } if (ret < 0) goto erase_err; @@ -1576,11 +1578,12 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - int ret; loff_t offset = from; - u32 read_len = 0; u32 rem_bank_len = 0; + u32 stack_shift = 0; + size_t read_len; u8 bank; + int ret; bool is_ofst_odd = false; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); @@ -1593,39 +1596,49 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } while (len) { - bank = (u32)from / SZ_16M; - if (nor->flags & SNOR_F_HAS_PARALLEL) - bank /= 2; - - rem_bank_len = SZ_16M * (bank + 1); - if (nor->flags & SNOR_F_HAS_PARALLEL) - rem_bank_len *= 2; - rem_bank_len -= from; - + read_len = len; offset = from; - if (nor->flags & SNOR_F_HAS_STACKED) { - if (offset >= (mtd->size / 2)) { - offset = offset - (mtd->size / 2); - nor->spi->flags |= SPI_XFER_U_PAGE; - } else { - nor->spi->flags &= ~SPI_XFER_U_PAGE; + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) { + bank = (u32)from / SZ_16M; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank /= 2; + } + rem_bank_len = SZ_16M * (bank + 1); + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + rem_bank_len *= 2; } + rem_bank_len -= from; } - if (nor->flags & SNOR_F_HAS_PARALLEL) - offset /= 2; + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_STACKED) { + stack_shift = 1; + if (offset >= (mtd->size / 2)) { + offset = offset - (mtd->size / 2); + nor->spi->flags |= SPI_XFER_U_PAGE; + } else { + nor->spi->flags &= ~SPI_XFER_U_PAGE; + } + } + } + + if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) { + if (nor->flags & SNOR_F_HAS_PARALLEL) + offset /= 2; + } #ifdef CONFIG_SPI_FLASH_BAR ret = write_bar(nor, offset); if (ret < 0) return log_ret(ret); -#endif - if (len < rem_bank_len) read_len = len; else read_len = rem_bank_len; +#endif if (read_len == 0) return -EIO; diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index c027d898a64..ba77c034736 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -116,7 +116,7 @@ config MTD_UBI_FM_DEBUG config UBI_BLOCK bool "Enable UBI block device support" - depends on BLK + select BLK help Enable UBI block device support using blk_ops abstraction. diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad..dcf6b4c81fc 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -975,6 +975,18 @@ config MEDIATEK_ETH This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +endif # MEDIATEK_ETH + config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" select DM_CLK @@ -1007,6 +1019,26 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config FSL_ENETC_NETC_BLK_CTRL + bool "NXP ENETC NETC blocks control driver" + depends on FSL_ENETC && IMX95 + default y if IMX95 + help + This driver configures Integrated Endpoint Register Block (IERB) and + Privileged Register Block (PRB) of NETC. For i.MX platforms, it also + includes the configuration of NETCMIX block. + The IERB contains registers that are used for pre-boot initialization, + debug, and non-customer configuration. The PRB controls global reset + and global error handling for NETC. The NETCMIX block is mainly used + to set MII protocol and PCS protocol of the links, it also contains + settings for some other functions. + +config MDIO_GPIO_BITBANG + bool "GPIO bitbanging MDIO driver" + depends on DM_MDIO && DM_GPIO + help + Driver for bitbanging MDIO + config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" depends on DM_MDIO_MUX && DM_I2C diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f5ab1f5dedf..c6217f08f14 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o +obj-$(CONFIG_FSL_ENETC_NETC_BLK_CTRL) += fsl_enetc_netc_blk_ctrl.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ @@ -61,6 +62,7 @@ obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 7d2170ae72c..54b08482b91 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1503,4 +1503,5 @@ U_BOOT_DRIVER(fecmxc_gem) = { .ops = &fecmxc_ops, .priv_auto = sizeof(struct fec_priv), .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ACTIVE_DMA, }; diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index a6b0bafc8c6..67ef5f34a8a 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -2,6 +2,7 @@ /* * ENETC ethernet controller driver * Copyright 2017-2021 NXP + * Copyright 2023-2025 NXP */ #include <dm.h> @@ -16,52 +17,267 @@ #include <miiphy.h> #include <linux/bug.h> #include <linux/delay.h> +#include <linux/build_bug.h> + +#ifdef CONFIG_ARCH_IMX9 +#include <asm/mach-imx/sys_proto.h> +#include <cpu_func.h> +#endif #include "fsl_enetc.h" #define ENETC_DRIVER_NAME "enetc_eth" +/* + * Calculate number of buffer descriptors per cacheline, and compile-time + * validate that: + * - the RX and TX descriptors are the same size + * - the descriptors fit exactly into cachelines without overlap + * - all descriptors fit exactly into cachelines + */ +#define ENETC_NUM_BD_IN_CL \ + ((ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(sizeof(struct enetc_tx_bd) != \ + sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(struct enetc_tx_bd)) + \ + BUILD_BUG_ON_ZERO(ARCH_DMA_MINALIGN % sizeof(union enetc_rx_bd)) + \ + BUILD_BUG_ON_ZERO(ENETC_BD_CNT % \ + (ARCH_DMA_MINALIGN / sizeof(struct enetc_tx_bd)))) + static int enetc_remove(struct udevice *dev); +static int enetc_is_imx95(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is i.MX95 ENETCv4. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_IMX9) && + pplat->vendor == PCI_VENDOR_ID_PHILIPS; +} + +static int enetc_is_ls1028a(struct udevice *dev) +{ + struct pci_child_plat *pplat = dev_get_parent_plat(dev); + + /* Test whether this is LS1028A ENETC. This may be optimized out. */ + return IS_ENABLED(CONFIG_ARCH_LS1028A) && + pplat->vendor == PCI_VENDOR_ID_FREESCALE; +} + +static int enetc_dev_id(struct udevice *dev) +{ + if (enetc_is_imx95(dev)) + return PCI_DEV(pci_get_devfn(dev)) >> 3; + if (enetc_is_ls1028a(dev)) + return PCI_FUNC(pci_get_devfn(dev)); + + return 0; +} + +static void enetc_inval_rxbd(struct udevice *dev) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *desc = &priv->enetc_rxbd[priv->rx_bdr.next_prod_idx]; + unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)desc + sizeof(*desc), + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_bd(struct udevice *dev, int pi, bool tx) +{ + struct enetc_priv *priv = dev_get_priv(dev); + union enetc_rx_bd *rxdesc = &priv->enetc_rxbd[pi]; + struct enetc_tx_bd *txdesc = &priv->enetc_txbd[pi]; + unsigned long desc = tx ? (unsigned long)txdesc : (unsigned long)rxdesc; + unsigned long size = tx ? sizeof(*txdesc) : sizeof(*rxdesc); + unsigned long start = rounddown(desc, ARCH_DMA_MINALIGN); + unsigned long end = roundup(desc + size, ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +static void enetc_inval_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + invalidate_dcache_range(start, end); +} + +static void enetc_flush_buffer(struct udevice *dev, void *buf, size_t size) +{ + unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); + unsigned long end = roundup((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + if (enetc_is_imx95(dev)) + flush_dcache_range(start, end); +} + +/* register accessors */ +static u32 enetc_read_reg(void __iomem *addr) +{ + return readl(addr); +} + +static void enetc_write_reg(void __iomem *addr, u32 val) +{ + writel(val, addr); +} + +static void enetc_write(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->regs_base + off, val); +} + +/* base port register accessors */ +static void enetc_write_pmr(struct udevice *dev, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PMR + data->reg_offset_pmr; + + enetc_write_reg(priv->port_regs + off, val); +} + +static void enetc_write_psipmar(struct udevice *dev, int n, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = (n ? ENETC_PSIPMAR1 : ENETC_PSIPMAR0) + + data->reg_offset_psipmar; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port station register accessors */ +static void enetc_write_psicfgr(struct udevice *dev, int port, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PSICFGR(port, ENETC_PSICFGR_SHIFT_LS) + + data->reg_offset_psicfgr; + + enetc_write_reg(priv->port_regs + off, val); +} + +/* port register accessors */ +static u32 enetc_read_pcapr_mdio(struct udevice *dev) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u32 off = ENETC_PCAPR0 + data->reg_offset_pcapr; + const u32 reg = enetc_read_reg(priv->port_regs + off); + + if (enetc_is_imx95(dev)) + return reg & ENETC_PCS_PROT; + else if (enetc_is_ls1028a(dev)) + return reg & ENETC_PCAPRO_MDIO; + + return 0; +} + +static void enetc_write_port(struct enetc_priv *priv, u32 off, u32 val) +{ + enetc_write_reg(priv->port_regs + off, val); +} + +/* MAC port register accessors */ +static u32 enetc_read_mac_port(struct udevice *dev, u32 off) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_read_reg(priv->port_regs + data->reg_offset_mac + off); +} + +static void enetc_write_mac_port(struct udevice *dev, u32 off, u32 val) +{ + struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev); + struct enetc_priv *priv = dev_get_priv(dev); + + enetc_write_reg(priv->port_regs + data->reg_offset_mac + off, val); +} + +/* BDR register accessor, see also ENETC_BDR() */ +static void enetc_bdr_write(struct enetc_priv *priv, int type, int n, + u32 off, u32 val) +{ + enetc_write(priv, ENETC_BDR(type, n, off), val); +} + /* * sets the MAC address in IERB registers, this setting is persistent and * carried over to Linux. */ -static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, - const u8 *enetaddr) -{ -#ifdef CONFIG_ARCH_LS1028A -/* - * LS1028A is the only part with IERB at this time and there are plans to change - * its structure, keep this LS1028A specific for now - */ #define IERB_BASE 0x1f0800000ULL #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ + (n) * 4) -static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; - +static void enetc_set_ierb_primary_mac(struct udevice *dev, void *blob) +{ + static int ierb_fn_to_pf[] = { 0, 1, 2, -1, -1, -1, 3 }; + struct pci_child_plat *ppdata = dev_get_parent_plat(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + const u8 *enetaddr = pdata->enetaddr; u16 lower = *(const u16 *)(enetaddr + 4); u32 upper = *(const u32 *)enetaddr; + int devfn, offset; + char path[256]; + + if (enetc_is_imx95(dev)) { + /* + * Configure the ENETC primary MAC addresses - Set register + * PMAR0/1 for SI 0 and PSIaPMAR0/1 for SI 1, 2 .. a + * (optionally pre-configured in IERB). + */ + devfn = enetc_dev_id(dev); + if (devfn > 2) + return; + + enetc_write(priv, IMX95_ENETC_SIPMAR0, upper); + enetc_write(priv, IMX95_ENETC_SIPMAR1, lower); + + snprintf(path, 256, "/soc/pcie@%x/ethernet@%x,%x", + PCI_BUS(dm_pci_get_bdf(dev)), PCI_DEV(ppdata->devfn), + PCI_FUNC(ppdata->devfn)); + } else if (enetc_is_ls1028a(dev)) { + /* + * LS1028A is the only part with IERB at this time and + * there are plans to change its structure, keep this + * LS1028A specific for now. + */ + devfn = PCI_FUNC(ppdata->devfn); + + if (ierb_fn_to_pf[devfn] < 0) + return; - if (ierb_fn_to_pf[devfn] < 0) + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); + + snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", + PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); + } else { return; + } - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); - out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); -#endif + offset = fdt_path_offset(blob, path); + if (offset >= 0) + fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); } /* sets up primary MAC addresses in DT/IERB */ void fdt_fixup_enetc_mac(void *blob) { - struct pci_child_plat *ppdata; - struct eth_pdata *pdata; struct udevice *dev; struct uclass *uc; - char path[256]; - int offset; - int devfn; uclass_get(UCLASS_ETH, &uc); uclass_foreach_dev(dev, uc) { @@ -69,18 +285,7 @@ void fdt_fixup_enetc_mac(void *blob) strcmp(dev->driver->name, ENETC_DRIVER_NAME)) continue; - pdata = dev_get_plat(dev); - ppdata = dev_get_parent_plat(dev); - devfn = PCI_FUNC(ppdata->devfn); - - enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); - - snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", - PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); - offset = fdt_path_offset(blob, path); - if (offset < 0) - continue; - fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); + enetc_set_ierb_primary_mac(dev, blob); } } @@ -101,7 +306,7 @@ static int enetc_bind(struct udevice *dev) * PCI function # and enetc#N based on interface count */ if (ofnode_valid(dev_ofnode(dev))) - sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); + sprintf(name, "enetc-%u", enetc_dev_id(dev)); else sprintf(name, "enetc#%u", eth_num_devices++); device_set_name(dev, name); @@ -181,10 +386,9 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - struct enetc_priv *priv = dev_get_priv(dev); - u32 old_val, val; + u32 old_val, val, dpx = 0; - old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE); + old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); /* disable unreliable RGMII in-band signaling and force the MAC into * the speed negotiated by the PHY. @@ -202,15 +406,20 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } + if (enetc_is_imx95(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_IMX; + else if (enetc_is_ls1028a(dev)) + dpx = ENETC_PM_IFM_FULL_DPX_LS; + if (phydev->duplex == DUPLEX_FULL) - val |= ENETC_PM_IFM_FULL_DPX; + val |= dpx; else - val &= ~ENETC_PM_IFM_FULL_DPX; + val &= ~dpx; if (val == old_val) return; - enetc_write_port(priv, ENETC_PM_IF_MODE, val); + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, val); } /* set up MAC configuration for the given interface type */ @@ -230,9 +439,12 @@ static void enetc_setup_mac_iface(struct udevice *dev, case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ - if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); - if_mode &= ~ENETC_PM_IF_IFMODE_MASK; - enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); + if_mode = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); + if (enetc_is_imx95(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_IMX; + else if (enetc_is_ls1028a(dev)) + if_mode &= ~ENETC_PM_IF_IFMODE_MASK_LS; + enetc_write_mac_port(dev, ENETC_PM_IF_MODE, if_mode); break; }; } @@ -263,7 +475,7 @@ static void enetc_start_pcs(struct udevice *dev) struct enetc_priv *priv = dev_get_priv(dev); /* register internal MDIO for debug purposes */ - if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) { + if (enetc_read_pcapr_mdio(dev)) { priv->imdio.read = enetc_mdio_read; priv->imdio.write = enetc_mdio_write; priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; @@ -375,6 +587,21 @@ static int enetc_remove(struct udevice *dev) return 0; } +static int enetc_imx95_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_plat(dev); + struct enetc_priv *priv = dev_get_priv(dev); + u8 *addr = plat->enetaddr; + + u16 lower = *(const u16 *)(addr + 4); + u32 upper = *(const u32 *)addr; + + enetc_write_port(priv, IMX95_ENETC_PMAR0, upper); + enetc_write_port(priv, IMX95_ENETC_PMAR1, lower); + + return 0; +} + /* * LS1028A is the only part with IERB at this time and there are plans to * change its structure, keep this LS1028A specific for now. @@ -413,39 +640,46 @@ static int enetc_ls1028a_write_hwaddr(struct udevice *dev) static int enetc_write_hwaddr(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); - struct enetc_priv *priv = dev_get_priv(dev); u8 *addr = plat->enetaddr; - if (IS_ENABLED(CONFIG_ARCH_LS1028A)) + if (enetc_is_imx95(dev)) + return enetc_imx95_write_hwaddr(dev); + if (enetc_is_ls1028a(dev)) return enetc_ls1028a_write_hwaddr(dev); u16 lower = *(const u16 *)(addr + 4); u32 upper = *(const u32 *)addr; - enetc_write_port(priv, ENETC_PSIPMAR0, upper); - enetc_write_port(priv, ENETC_PSIPMAR1, lower); + enetc_write_psipmar(dev, 0, upper); + enetc_write_psipmar(dev, 1, lower); return 0; } /* Configure port parameters (# of rings, frame size, enable port) */ -static void enetc_enable_si_port(struct enetc_priv *priv) +static void enetc_enable_si_port(struct udevice *dev) { - u32 val; + struct enetc_priv *priv = dev_get_priv(dev); + u32 val = ENETC_PM_CC_TXP_IMX | ENETC_PM_CC_TX | ENETC_PM_CC_RX; /* set Rx/Tx BDR count */ - val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); - val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); - enetc_write_port(priv, ENETC_PSICFGR(0), val); + enetc_write_psicfgr(dev, 0, ENETC_PSICFGR_SET_BDR(ENETC_RX_BDR_CNT, + ENETC_TX_BDR_CNT)); /* set Rx max frame size */ - enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); + enetc_write_mac_port(dev, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); /* enable MAC port */ - enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); + if (enetc_is_ls1028a(dev)) + val |= ENETC_PM_CC_TXP_LS | ENETC_PM_CC_PROMIS; + enetc_write_mac_port(dev, ENETC_PM_CC, val); /* enable port */ - enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); + if (enetc_is_imx95(dev)) + enetc_write_port(priv, ENETC_POR, 0x0); + enetc_write_pmr(dev, ENETC_PMR_SI0_EN); /* set SI cache policy */ - enetc_write(priv, ENETC_SICAR0, - ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); + enetc_write(priv, ENETC_SICAR0, ENETC_SICAR_WR_CFG | + (enetc_is_imx95(dev) ? + ENETC_SICAR_RD_CFG_IMX : + ENETC_SICAR_RD_CFG_LS)); /* enable SI */ enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); } @@ -536,6 +770,8 @@ static void enetc_setup_rx_bdr(struct udevice *dev) priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); /* each RX buffer must be aligned to 64B */ WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); + + enetc_flush_bd(dev, i, false); } /* reset producer (ENETC owned) and consumer (SW owned) index */ @@ -556,6 +792,7 @@ static void enetc_setup_rx_bdr(struct udevice *dev) */ static int enetc_start(struct udevice *dev) { + int ret; struct enetc_priv *priv = dev_get_priv(dev); /* reset and enable the PCI device */ @@ -563,15 +800,19 @@ static int enetc_start(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - enetc_enable_si_port(priv); + enetc_enable_si_port(dev); /* setup Tx/Rx buffer descriptors */ enetc_setup_tx_bdr(dev); enetc_setup_rx_bdr(dev); + ret = phy_startup(priv->phy); + if (ret) + return ret; + enetc_setup_mac_iface(dev, priv->phy); - return phy_startup(priv->phy); + return 0; } /* @@ -614,6 +855,8 @@ static int enetc_send(struct udevice *dev, void *packet, int length) enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); + enetc_flush_buffer(dev, packet, length); + /* prepare Tx BD */ memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); priv->enetc_txbd[pi].addr = @@ -621,7 +864,10 @@ static int enetc_send(struct udevice *dev, void *packet, int length) priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); + dmb(); + enetc_flush_bd(dev, pi, true); + /* send frame: increment producer index */ pi = (pi + 1) % txr->bd_count; txr->next_prod_idx = pi; @@ -643,15 +889,15 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) { struct enetc_priv *priv = dev_get_priv(dev); struct bd_ring *rxr = &priv->rx_bdr; - int tries = ENETC_POLL_TRIES; int pi = rxr->next_prod_idx; - int ci = rxr->next_cons_idx; + int tries = ENETC_POLL_TRIES; u32 status; int len; u8 rdy; do { dmb(); + enetc_inval_rxbd(dev); status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); /* check if current BD is ready to be consumed */ rdy = ENETC_RXBD_STATUS_R(status); @@ -663,45 +909,142 @@ static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) dmb(); len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); *packetp = (uchar *)enetc_rxb_address(dev, pi); + enetc_inval_buffer(dev, *packetp, len); enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, ENETC_RXBD_STATUS_ERRORS(status), upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); - /* BD clean up and advance to next in ring */ - memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); - priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); + return len; +} + +static int enetc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + const int bd_num_in_cl = enetc_is_imx95(dev) ? ENETC_NUM_BD_IN_CL : 1; + struct enetc_priv *priv = dev_get_priv(dev); + struct bd_ring *rxr = &priv->rx_bdr; + int pi = rxr->next_prod_idx; + int ci = rxr->next_cons_idx; + uchar *packet_expected; + int i; + + packet_expected = (uchar *)enetc_rxb_address(dev, pi); + if (packet != packet_expected) { + printf("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + rxr->next_prod_idx = (pi + 1) % rxr->bd_count; ci = (ci + 1) % rxr->bd_count; rxr->next_cons_idx = ci; dmb(); - /* free up the slot in the ring for HW */ - enetc_write_reg(rxr->cons_idx, ci); - return len; + if ((pi + 1) % bd_num_in_cl == 0) { + /* BD clean up and advance to next in ring */ + for (i = 0; i < bd_num_in_cl; i++) { + memset(&priv->enetc_rxbd[pi - i], 0, sizeof(union enetc_rx_bd)); + priv->enetc_rxbd[pi - i].w.addr = enetc_rxb_address(dev, pi - i); + } + + /* Will flush all bds in one cacheline */ + enetc_flush_bd(dev, pi - bd_num_in_cl + 1, false); + + /* free up the slot in the ring for HW */ + enetc_write_reg(rxr->cons_idx, ci); + } + + return 0; } -static const struct eth_ops enetc_ops = { +#if IS_ENABLED(CONFIG_ARCH_IMX9) +static int enetc_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + unsigned int dev_id = enetc_dev_id(dev); + unsigned char *mac = pdata->enetaddr; + + if (dev_id > 2) + return -EINVAL; + + imx_get_mac_from_fuse(dev_id, mac); + + return !is_valid_ethaddr(mac); +} + +static const struct eth_ops enetc_ops_imx = { + .start = enetc_start, + .send = enetc_send, + .recv = enetc_recv, + .stop = enetc_stop, + .free_pkt = enetc_free_pkt, + .write_hwaddr = enetc_write_hwaddr, + .read_rom_hwaddr = enetc_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(eth_enetc_imx) = { + .name = ENETC_DRIVER_NAME, + .id = UCLASS_ETH, + .bind = enetc_bind, + .probe = enetc_probe, + .remove = enetc_remove, + .ops = &enetc_ops_imx, + .priv_auto = sizeof(struct enetc_priv), + .plat_auto = sizeof(struct eth_pdata), +}; + +static const struct enetc_data enetc_data_imx = { + .reg_offset_pmr = ENETC_PMR_OFFSET_IMX, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_IMX, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_IMX, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_IMX, + .reg_offset_mac = ENETC_PM_OFFSET_IMX, +}; + +static struct pci_device_id enetc_ids_imx[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_ETH), + .driver_data = (ulong)&enetc_data_imx, + }, + {} +}; + +U_BOOT_PCI_DEVICE(eth_enetc_imx, enetc_ids_imx); +#endif + +static const struct eth_ops enetc_ops_ls = { .start = enetc_start, .send = enetc_send, .recv = enetc_recv, .stop = enetc_stop, + .free_pkt = enetc_free_pkt, .write_hwaddr = enetc_write_hwaddr, }; -U_BOOT_DRIVER(eth_enetc) = { +U_BOOT_DRIVER(eth_enetc_ls) = { .name = ENETC_DRIVER_NAME, .id = UCLASS_ETH, .bind = enetc_bind, .probe = enetc_probe, .remove = enetc_remove, - .ops = &enetc_ops, + .ops = &enetc_ops_ls, .priv_auto = sizeof(struct enetc_priv), .plat_auto = sizeof(struct eth_pdata), }; -static struct pci_device_id enetc_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, +static const struct enetc_data enetc_data_ls = { + .reg_offset_pmr = ENETC_PMR_OFFSET_LS, + .reg_offset_psipmar = ENETC_PSIPMARn_OFFSET_LS, + .reg_offset_pcapr = ENETC_PCAPR_OFFSET_LS, + .reg_offset_psicfgr = ENETC_PSICFGR_OFFSET_LS, + .reg_offset_mac = ENETC_PM_OFFSET_LS, +}; + +static struct pci_device_id enetc_ids_ls[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH), + .driver_data = (ulong)&enetc_data_ls, + }, {} }; -U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); +U_BOOT_PCI_DEVICE(eth_enetc_ls, enetc_ids_ls); diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index f2acf367aa3..804df853bf5 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -12,7 +12,9 @@ /* PCI function IDs */ #define PCI_DEVICE_ID_ENETC_ETH 0xE100 +#define PCI_DEVICE_ID_ENETC4_ETH 0xE101 #define PCI_DEVICE_ID_ENETC_MDIO 0xEE01 +#define PCI_DEVICE_ID_ENETC4_EMDIO 0xEE00 /* ENETC Ethernet controller registers */ /* Station interface register offsets */ @@ -22,7 +24,8 @@ /* write cache cfg: snoop, no allocate, data & BD coherent */ #define ENETC_SICAR_WR_CFG 0x6767 /* read cache cfg: coherent copy, look up, don't alloc in cache */ -#define ENETC_SICAR_RD_CFG 0x27270000 +#define ENETC_SICAR_RD_CFG_LS 0x27270000 +#define ENETC_SICAR_RD_CFG_IMX 0x2b2b0000 #define ENETC_SIROCT 0x300 #define ENETC_SIRFRM 0x308 #define ENETC_SITOCT 0x320 @@ -57,32 +60,60 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PORT_REGS_OFF 0x10000 /* Port registers */ +#define ENETC_PMR_OFFSET_IMX 0x0010 +#define ENETC_PMR_OFFSET_LS 0x0000 #define ENETC_PMR 0x0000 #define ENETC_PMR_SI0_EN BIT(16) #define ENETC_PSIPMMR 0x0018 -#define ENETC_PSIPMAR0 0x0100 -#define ENETC_PSIPMAR1 0x0104 -#define ENETC_PCAPR0 0x0900 -#define ENETC_PCAPRO_MDIO BIT(11) -#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10) -#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff) -#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16) +#define ENETC_PSIPMARn_OFFSET_IMX 0x0000 +#define ENETC_PSIPMARn_OFFSET_LS 0x0080 +#define ENETC_PSIPMAR0 0x0080 +#define ENETC_PSIPMAR1 0x0084 +#define ENETC_PCAPR_OFFSET_IMX 0x4008 +#define ENETC_PCAPR_OFFSET_LS 0x0900 +#define ENETC_PCAPR0 0x0000 +#define ENETC_PCAPRO_MDIO BIT(11) /* LS only */ +#define ENETC_PCS_PROT GENMASK(15, 0) /* IMX only */ +/* ENETC base registers */ +#define ENETC_PSICFGR_OFFSET_LS 0x0940 +#define ENETC_PSICFGR_SHIFT_LS 0x10 +#define ENETC_PSICFGR_OFFSET_IMX 0x2010 +#define ENETC_PSICFGR_SHIFT_IMX 0x80 +#define ENETC_PSICFGR(n, s) ((n) * (s)) +#define ENETC_PSICFGR_SET_BDR(rx, tx) (((rx) << 16) | (tx)) /* MAC configuration */ -#define ENETC_PM_CC 0x8008 +#define ENETC_PM_OFFSET_IMX 0x5000 +#define ENETC_PM_OFFSET_LS 0x8000 +#define ENETC_PM_CC 0x0008 #define ENETC_PM_CC_DEFAULT 0x0810 -#define ENETC_PM_CC_RX_TX_EN 0x8813 -#define ENETC_PM_MAXFRM 0x8014 +#define ENETC_PM_CC_TXP_IMX BIT(15) +#define ENETC_PM_CC_TXP_LS BIT(11) +#define ENETC_PM_CC_PROMIS BIT(4) +#define ENETC_PM_CC_TX BIT(1) +#define ENETC_PM_CC_RX BIT(0) +#define ENETC_PM_MAXFRM 0x0014 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN -#define ENETC_PM_IMDIO_BASE 0x8030 -#define ENETC_PM_IF_MODE 0x8300 +#define ENETC_PM_IMDIO_BASE 0x0030 +#define ENETC_PM_IF_MODE 0x0300 #define ENETC_PM_IF_MODE_RG BIT(2) #define ENETC_PM_IF_MODE_AN_ENA BIT(15) #define ENETC_PM_IFM_SSP_MASK GENMASK(14, 13) #define ENETC_PM_IFM_SSP_1000 (2 << 13) #define ENETC_PM_IFM_SSP_100 (0 << 13) #define ENETC_PM_IFM_SSP_10 (1 << 13) -#define ENETC_PM_IFM_FULL_DPX BIT(12) -#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0) +#define ENETC_PM_IFM_FULL_DPX_IMX BIT(6) +#define ENETC_PM_IFM_FULL_DPX_LS BIT(12) +#define ENETC_PM_IF_IFMODE_MASK_IMX GENMASK(2, 0) +#define ENETC_PM_IF_IFMODE_MASK_LS GENMASK(1, 0) + +/* i.MX95 specific registers */ +#define IMX95_ENETC_SIPMAR0 0x80 +#define IMX95_ENETC_SIPMAR1 0x84 + +/* Port registers */ +#define IMX95_ENETC_PMAR0 0x4020 +#define IMX95_ENETC_PMAR1 0x4024 +#define ENETC_POR 0x4100 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER @@ -163,25 +194,14 @@ struct enetc_priv { struct phy_device *phy; }; -/* register accessors */ -#define enetc_read_reg(x) readl((x)) -#define enetc_write_reg(x, val) writel((val), (x)) -#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off)) -#define enetc_write(priv, off, v) \ - enetc_write_reg((priv)->regs_base + (off), v) - -/* port register accessors */ -#define enetc_port_regs(priv, off) ((priv)->port_regs + (off)) -#define enetc_read_port(priv, off) \ - enetc_read_reg(enetc_port_regs((priv), (off))) -#define enetc_write_port(priv, off, v) \ - enetc_write_reg(enetc_port_regs((priv), (off)), v) - -/* BDR register accessors, see ENETC_BDR() */ -#define enetc_bdr_read(priv, t, n, off) \ - enetc_read(priv, ENETC_BDR(t, n, off)) -#define enetc_bdr_write(priv, t, n, off, val) \ - enetc_write(priv, ENETC_BDR(t, n, off), val) +struct enetc_data { + /* Register layout offsets */ + u16 reg_offset_pmr; + u16 reg_offset_psipmar; + u16 reg_offset_pcapr; + u16 reg_offset_psicfgr; + u16 reg_offset_mac; +}; /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ #define ENETC_PCS_PHY_ADDR 0 diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 2d5fcbb6dbd..c1d491f2c5a 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * ENETC ethernet controller driver - * Copyright 2019 NXP + * Copyright 2019-2025 NXP */ #include <dm.h> @@ -14,6 +14,16 @@ #include "fsl_enetc.h" +static u32 enetc_read(struct enetc_mdio_priv *priv, u32 off) +{ + return readl(priv->regs_base + off); +} + +static void enetc_write(struct enetc_mdio_priv *priv, u32 off, u32 val) +{ + writel(val, priv->regs_base + off); +} + static void enetc_mdio_wait_bsy(struct enetc_mdio_priv *priv) { int to = 10000; @@ -122,7 +132,9 @@ static int enetc_mdio_bind(struct udevice *dev) static int enetc_mdio_probe(struct udevice *dev) { + struct pci_child_plat *pplat = dev_get_parent_plat(dev); struct enetc_mdio_priv *priv = dev_get_priv(dev); + u16 cmd = PCI_COMMAND_MEMORY; priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); if (!priv->regs_base) { @@ -132,7 +144,10 @@ static int enetc_mdio_probe(struct udevice *dev) priv->regs_base += ENETC_MDIO_BASE; - dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); + if (pplat->vendor == PCI_VENDOR_ID_PHILIPS) /* i.MX95 */ + cmd |= PCI_COMMAND_MASTER; + + dm_pci_clrset_config16(dev, PCI_COMMAND, 0, cmd); return 0; } @@ -148,6 +163,7 @@ U_BOOT_DRIVER(enetc_mdio) = { static struct pci_device_id enetc_mdio_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) }, + { PCI_DEVICE(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_ENETC4_EMDIO) }, { } }; diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c new file mode 100644 index 00000000000..46b68d3d8a4 --- /dev/null +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP NETC Blocks Control Driver + * + * Copyright 2024 NXP + * + * This driver is used for pre-initialization of NETC, such as PCS and MII + * protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can + * only be probed after the netc-blk-crtl driver has completed initialization. + * In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX + * will be powered off, except for WOL. Therefore, when the system resumes, + * these blocks need to be reinitialized. + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <phy_interface.h> + +/* NETCMIX registers */ +#define IMX95_CFG_LINK_IO_VAR 0x0 +#define IO_VAR_16FF_16G_SERDES 0x1 +#define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_MII_PROT 0x4 +#define CFG_LINK_MII_PORT_0 GENMASK(3, 0) +#define CFG_LINK_MII_PORT_1 GENMASK(7, 4) +#define MII_PROT_MII 0x0 +#define MII_PROT_RMII 0x1 +#define MII_PROT_RGMII 0x2 +#define MII_PROT_SERIAL 0x3 +#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) + +#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) +#define PCS_PROT_1G_SGMII BIT(0) +#define PCS_PROT_2500M_SGMII BIT(1) +#define PCS_PROT_XFI BIT(3) +#define PCS_PROT_SFI BIT(4) +#define PCS_PROT_10G_SXGMII BIT(6) + +/* NETC privileged register block register */ +#define PRB_NETCRR 0x100 +#define NETCRR_SR BIT(0) +#define NETCRR_LOCK BIT(1) + +#define PRB_NETCSR 0x104 +#define NETCSR_ERROR BIT(0) +#define NETCSR_STATE BIT(1) + +/* NETC integrated endpoint register block register */ +#define IERB_EMDIOFAUXR 0x344 +#define IERB_T0FAUXR 0x444 +#define IERB_EFAUXR(a) (0x3044 + 0x100 * (a)) +#define IERB_VFAUXR(a) (0x4004 + 0x40 * (a)) +#define FAUXR_LDID GENMASK(3, 0) + +/* Platform information */ +#define IMX95_ENETC0_BUS_DEVFN 0x0 +#define IMX95_ENETC1_BUS_DEVFN 0x40 +#define IMX95_ENETC2_BUS_DEVFN 0x80 + +/* Flags for different platforms */ +#define NETC_HAS_NETCMIX BIT(0) + +struct netc_blk_ctrl { + void __iomem *prb; + void __iomem *ierb; + void __iomem *netcmix; +}; + +static void netc_reg_write(void __iomem *base, u32 offset, u32 val) +{ + writel(val, base + offset); +} + +static u32 netc_reg_read(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static int netc_of_pci_get_bus_devfn(ofnode node) +{ + u32 reg[5]; + int error; + + error = ofnode_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xffff; +} + +static int netc_get_link_mii_protocol(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_MII: + return MII_PROT_MII; + case PHY_INTERFACE_MODE_RMII: + return MII_PROT_RMII; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + return MII_PROT_RGMII; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_XGMII: + case PHY_INTERFACE_MODE_USXGMII: + return MII_PROT_SERIAL; + default: + return -EINVAL; + } +} + +static int imx95_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting of MII protocol */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) | + MII_PROT(2, MII_PROT_SERIAL); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + if (bus_devfn == IMX95_ENETC2_BUS_DEVFN) + continue; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX95_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX95_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(2, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2), + PCS_PROT_10G_SXGMII); + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + +static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv) +{ + return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK); +} + +static int netc_lock_ierb(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK); + + return readl_poll_timeout(priv->prb + PRB_NETCSR, val, + !(val & NETCSR_STATE), 2000); +} + +static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv) +{ + u32 val; + + netc_reg_write(priv->prb, PRB_NETCRR, 0); + + return readl_poll_timeout(priv->prb + PRB_NETCRR, val, + !(val & NETCRR_LOCK), 100000); +} + +static int imx95_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + + /* EMDIO : No MSI-X intterupt */ + netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0); + /* ENETC0 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0); + /* ENETC0 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1); + /* ENETC0 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2); + /* ENETC1 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3); + /* ENETC1 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5); + /* ENETC1 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6); + /* ENETC2 PF */ + netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4); + /* ENETC2 VF0 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5); + /* ENETC2 VF1 */ + netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6); + /* NETC TIMER */ + netc_reg_write(priv->ierb, IERB_T0FAUXR, 7); + + return 0; +} + +static int netc_ierb_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + int err; + + if (netc_ierb_is_locked(priv)) { + err = netc_unlock_ierb_with_warm_reset(priv); + if (err) { + dev_err(dev, "Unlock IERB failed.\n"); + return err; + } + } + + err = imx95_ierb_init(dev); + if (err) + return err; + + err = netc_lock_ierb(priv); + if (err) { + dev_err(dev, "Lock IERB failed.\n"); + return err; + } + + return 0; +} + +static int netc_prb_check_error(struct netc_blk_ctrl *priv) +{ + if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR) + return -1; + + return 0; +} + +static const struct udevice_id netc_blk_ctrl_match[] = { + { .compatible = "nxp,imx95-netc-blk-ctrl" }, + {}, +}; + +static int netc_blk_ctrl_probe(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + struct clk *ipg_clk; + fdt_addr_t regs; + int err; + + ipg_clk = devm_clk_get_optional(dev, "ipg"); + if (IS_ERR(ipg_clk)) { + dev_err(dev, "Set ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + err = clk_prepare_enable(ipg_clk); + if (err) { + dev_err(dev, "Enable ipg clock failed\n"); + return PTR_ERR(ipg_clk); + } + + regs = dev_read_addr_name(dev, "ierb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing IERB resource\n"); + return -EINVAL; + } + + priv->ierb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "prb"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing PRB resource\n"); + return -EINVAL; + } + + priv->prb = (void __iomem *)regs; + regs = dev_read_addr_name(dev, "netcmix"); + if (regs == FDT_ADDR_T_NONE) { + dev_err(dev, "Missing NETCMIX resource\n"); + return -EINVAL; + } + + priv->netcmix = (void __iomem *)regs; + + err = imx95_netcmix_init(dev); + if (err) { + dev_err(dev, "Initializing NETCMIX failed\n"); + return err; + } + + err = netc_ierb_init(dev); + if (err) { + dev_err(dev, "Initializing IERB failed\n"); + return err; + } + + if (netc_prb_check_error(priv) < 0) + dev_warn(dev, "The current IERB configuration is invalid\n"); + + return 0; +} + +U_BOOT_DRIVER(netc_blk_ctrl_drv) = { + .name = "netc_blk_ctrl", + .id = UCLASS_SIMPLE_BUS, + .of_match = netc_blk_ctrl_match, + .probe = netc_blk_ctrl_probe, + .priv_auto = sizeof(struct netc_blk_ctrl), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/net/mdio_gpio.c b/drivers/net/mdio_gpio.c new file mode 100644 index 00000000000..a2a41f95190 --- /dev/null +++ b/drivers/net/mdio_gpio.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO based MDIO bitbang driver. + * + * Copyright 2024 Markus Gothe <markus.gothe@genexis.eu> + * + * This file is based on the Linux kernel drivers drivers/net/phy/mdio-gpio.c + * and drivers/net/phy/mdio-bitbang.c which have the following copyrights: + * + * Copyright (c) 2008 CSE Semaphore Belgium. + * by Laurent Pinchart <laurentp@cse-semaphore.com> + * + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * Author: Scott Wood <scottwood@freescale.com> + * Copyright (c) 2007 Freescale Semiconductor + * + * Copyright (c) 2003 Intracom S.A. + * by Pantelis Antoniou <panto@intracom.gr> + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + */ + +#include <dm.h> +#include <log.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> + +#define MDIO_READ 2 +#define MDIO_WRITE 1 + +#define MDIO_C45 BIT(15) +#define MDIO_C45_ADDR (MDIO_C45 | 0) +#define MDIO_C45_READ (MDIO_C45 | 3) +#define MDIO_C45_WRITE (MDIO_C45 | 1) + +/* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY + * is done twice per period. + */ +#define MDIO_DELAY 250 + +/* The PHY may take up to 300 ns to produce data, plus some margin + * for error. + */ +#define MDIO_READ_DELAY 350 + +#define MDIO_GPIO_MDC 0 +#define MDIO_GPIO_MDIO 1 +#define MDIO_GPIO_MDO 2 + +struct mdio_gpio_priv { + struct gpio_desc mdc, mdio, mdo; +}; + +static void mdio_dir(struct udevice *mdio_dev, int dir) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) { + /* Separate output pin. Always set its value to high + * when changing direction. If direction is input, + * assume the pin serves as pull-up. If direction is + * output, the default value is high. + */ + dm_gpio_set_value(&priv->mdo, 1); + return; + } + + if (dir) + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + else + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_IN); +} + +static int mdio_get(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + return dm_gpio_get_value(&priv->mdio); +} + +static void mdio_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) + dm_gpio_set_value(&priv->mdo, what); + else + dm_gpio_set_value(&priv->mdio, what); +} + +static void mdc_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + dm_gpio_set_value(&priv->mdc, what); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_bit(struct udevice *mdio_dev, int val) +{ + mdio_set(mdio_dev, val); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 0); +} + +/* MDIO must already be configured as input. */ +static int mdio_gpio_get_bit(struct udevice *mdio_dev) +{ + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_READ_DELAY); + mdc_set(mdio_dev, 0); + + return mdio_get(mdio_dev); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_num(struct udevice *mdio_dev, u16 val, int bits) +{ + int i; + + for (i = bits - 1; i >= 0; i--) + mdio_gpio_send_bit(mdio_dev, (val >> i) & 1); +} + +/* MDIO must already be configured as input. */ +static u16 mdio_gpio_get_num(struct udevice *mdio_dev, int bits) +{ + int i; + u16 ret = 0; + + for (i = bits - 1; i >= 0; i--) { + ret <<= 1; + ret |= mdio_gpio_get_bit(mdio_dev); + } + + return ret; +} + +/* Utility to send the preamble, address, and + * register (common to read and write). + */ +static void mdio_gpio_cmd(struct udevice *mdio_dev, int op, u8 phy, u8 reg) +{ + int i; + + mdio_dir(mdio_dev, 1); + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good + * measure. The IEEE spec says this is a PHY optional + * requirement. The AMD 79C874 requires one after power up and + * one after a MII communications error. This means that we are + * doing more preambles than we need, but it is safer and will be + * much more robust. + */ + for (i = 0; i < 32; i++) + mdio_gpio_send_bit(mdio_dev, 1); + + /* + * Send the start bit (01) and the read opcode (10) or write (01). + * Clause 45 operation uses 00 for the start and 11, 10 for + * read/write. + */ + mdio_gpio_send_bit(mdio_dev, 0); + if (op & MDIO_C45) + mdio_gpio_send_bit(mdio_dev, 0); + else + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, (op >> 1) & 1); + mdio_gpio_send_bit(mdio_dev, (op >> 0) & 1); + + mdio_gpio_send_num(mdio_dev, phy, 5); + mdio_gpio_send_num(mdio_dev, reg, 5); +} + +/* + * In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the + * lower 16 bits of the 21 bit address. This transfer is done identically to a + * MDIO_WRITE except for a different code. To enable clause 45 mode or + * MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices + * can exist on the same bus. Normal devices should ignore the MDIO_ADDR + * phase. + */ +static int mdio_gpio_cmd_addr(struct udevice *mdio_dev, int phy, u32 dev_addr, u32 reg) +{ + mdio_gpio_cmd(mdio_dev, MDIO_C45_ADDR, phy, dev_addr); + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, reg, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return dev_addr; +} + +static int mdio_gpio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + int ret, i; + + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_READ, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_READ, addr, reg); + } + + mdio_dir(mdio_dev, 0); + + /* check the turnaround bit: the PHY should be driving it to zero. + */ + if (mdio_gpio_get_bit(mdio_dev) != 0) { + /* PHY didn't drive TA low -- flush any bits it + * may be trying to send. + */ + for (i = 0; i < 32; i++) + mdio_gpio_get_bit(mdio_dev); + + return 0xffff; + } + + ret = mdio_gpio_get_num(mdio_dev, 16); + mdio_gpio_get_bit(mdio_dev); + + return ret; +} + +static int mdio_gpio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_WRITE, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_WRITE, addr, reg); + } + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, val, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return 0; +} + +static const struct mdio_ops mdio_gpio_ops = { + .read = mdio_gpio_read, + .write = mdio_gpio_write, + .reset = NULL, +}; + +/* + * Name the device, we use the device tree node name. + * This can be overwritten by MDIO class code if device-name property is + * present. + */ +static int mdio_gpio_bind(struct udevice *mdio_dev) +{ + if (ofnode_valid(dev_ofnode(mdio_dev))) + device_set_name(mdio_dev, ofnode_get_name(dev_ofnode(mdio_dev))); + + return 0; +} + +static int mdio_gpio_probe(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + int ret = 0; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDC, &priv->mdc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDIO, &priv->mdio, GPIOD_IS_IN); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDO, &priv->mdo, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) + return ret; + + return 0; +} + +static const struct udevice_id mdio_gpio_ids[] = { + { .compatible = "virtual,mdio-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_mdio) = { + .name = "gpio_mdio", + .id = UCLASS_MDIO, + .of_match = mdio_gpio_ids, + .bind = mdio_gpio_bind, + .probe = mdio_gpio_probe, + .ops = &mdio_gpio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), + .priv_auto = sizeof(struct mdio_gpio_priv), +}; diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5098afef8a8..454caa3cd3a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -29,8 +29,8 @@ #include "mtk_eth.h" -#define NUM_TX_DESC 24 -#define NUM_RX_DESC 24 +#define NUM_TX_DESC 32 +#define NUM_RX_DESC 32 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) @@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, } /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), - SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), @@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_priv *priv) if (!priv->force_mode) { if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) mtk_xphy_link_adjust(priv); else @@ -1281,8 +1282,7 @@ static int mtk_phy_probe(struct udevice *dev) static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN1 speed(1G) */ - clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500, 0); + clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); /* Enable SGMII AN */ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1305,8 +1305,9 @@ static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN2 speed(2.5G) */ - setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500); + clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, + SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) udelay(400); } +static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) +{ + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); + regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); + ndelay(1020); + regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); + ndelay(1020); + + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); + if (priv->gmac_id == 2) + regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); + udelay(150); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); + udelay(15); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); + udelay(100); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); + udelay(400); +} + static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) { mtk_xfi_pll_enable(priv); @@ -1432,11 +1498,23 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) mtk_usxgmii_setup_phya_an_10000(priv); } -static void mtk_mac_init(struct mtk_eth_priv *priv) +static void mtk_10gbaser_init(struct mtk_eth_priv *priv) +{ + mtk_xfi_pll_enable(priv); + mtk_usxgmii_reset(priv); + mtk_usxgmii_setup_phya_force_10000(priv); +} + +static int mtk_mac_init(struct mtk_eth_priv *priv) { - int i, ge_mode = 0; + int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { + mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, + INFRA_MISC2_BONDING_OPTION, priv->gmac_id); + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII: @@ -1444,18 +1522,28 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_2500BASEX: + if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { + printf("Error: SGMII is not supported on this platform\n"); + return -ENOTSUPP; + } + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, SGMII_QPHY_SEL); } - ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; + + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, + SYSCFG1_SGMII_SEL(priv->gmac_id)); + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) mtk_sgmii_an_init(priv); else mtk_sgmii_force_init(priv); + + ge_mode = GE_MODE_RGMII; break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -1469,9 +1557,9 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } /* set the gmac to the right mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), - ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); if (priv->force_mode) { mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | @@ -1512,26 +1600,37 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) RX_RST | RXC_DQSISEL); mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); } + + return 0; } -static void mtk_xmac_init(struct mtk_eth_priv *priv) +static int mtk_xmac_init(struct mtk_eth_priv *priv) { u32 force_link = 0; + if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { + printf("Error: 10Gb interface is not supported on this platform\n"); + return -ENOTSUPP; + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_USXGMII: mtk_usxgmii_an_init(priv); break; + case PHY_INTERFACE_MODE_10GBASER: + mtk_10gbaser_init(priv); + break; default: break; } /* Set GMAC to the correct mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), 0); - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && + if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && priv->gmac_id == 1) { mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); @@ -1546,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) /* Force GMAC link down */ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); + + return 0; } static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) @@ -1661,10 +1762,16 @@ static int mtk_eth_start(struct udevice *dev) if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); - } - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, - GDMA_CPU_BRIDGE_EN); + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && + priv->gmac_id != 0) { + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } } udelay(500); @@ -1790,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + invalidate_dcache_range((ulong)rxd->rxd1, + (ulong)rxd->rxd1 + PKTSIZE_ALIGN); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); @@ -1833,10 +1943,14 @@ static int mtk_eth_probe(struct udevice *dev) /* Set MAC mode */ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xmac_init(priv); + ret = mtk_xmac_init(priv); else - mtk_mac_init(priv); + ret = mtk_mac_init(priv); + + if (ret) + return ret; /* Probe phy if switch is not specified */ if (priv->sw == SW_NONE) @@ -1944,8 +2058,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) } } - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || - priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || + priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && + IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { /* get corresponding sgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", NULL, 0, 0, &args); @@ -1967,7 +2082,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) /* Upstream linux use mediatek,pnswap instead of pn_swap */ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ofnode_read_bool(args.node, "mediatek,pnswap"); - } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && + IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", NULL, 0, 0, &args); @@ -2096,6 +2213,7 @@ static const struct mtk_soc_data mt7981_data = { }; static const struct mtk_soc_data mt7629_data = { + .caps = MT7629_CAPS, .ana_rgc3 = 0x128, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, @@ -2112,6 +2230,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7622_data = { + .caps = MT7622_CAPS, .ana_rgc3 = 0x2028, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index fd31c782c7f..1aa037907c5 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -23,6 +23,8 @@ enum mkt_eth_capabilities { /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_MT7622_SGMII_BIT, + MTK_ETH_PATH_MT7629_GMAC2_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) @@ -36,6 +38,8 @@ enum mkt_eth_capabilities { #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) +#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -45,8 +49,12 @@ enum mkt_eth_capabilities { #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) +#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) + #define MT7623_CAPS (MTK_GMAC1_TRGMII) +#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) #define MT7986_CAPS (MTK_NETSYS_V2) @@ -65,11 +73,11 @@ enum mkt_eth_capabilities { /* Ethernet subsystem registers */ -#define ETHSYS_SYSCFG0_REG 0x14 -#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) -#define SYSCFG0_GE_MODE_M 0x3 -#define SYSCFG0_SGMII_SEL_M (0x3 << 8) -#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) +#define ETHSYS_SYSCFG1_REG 0x14 +#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) +#define SYSCFG1_GE_MODE_M 0x3 +#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) +#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) @@ -84,7 +92,10 @@ enum mkt_eth_capabilities { #define QPHY_SEL_MASK 0x3 #define SGMII_QPHY_SEL 0x2 -/* SYSCFG0_GE_MODE: GE Modes */ +#define MT7629_INFRA_MISC2_REG 0x70c +#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) + +/* SYSCFG1_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 #define GE_MODE_MII_PHY 2 @@ -108,7 +119,8 @@ enum mkt_eth_capabilities { #define SGMSYS_GEN2_SPEED 0x2028 #define SGMSYS_GEN2_SPEED_V2 0x128 -#define SGMSYS_SPEED_2500 BIT(2) +#define SGMSYS_SPEED_MASK GENMASK(3, 2) +#define SGMSYS_SPEED_2500 1 /* USXGMII subsystem config registers */ /* Register to control USXGMII XFI PLL digital */ diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b0a0b7fcb38..08608a99b9d 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -461,8 +461,7 @@ static int m88e151x_config(struct phy_device *phydev) reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) reg |= MIIM_88E151x_RGMII_RXTX_DELAY; else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) reg |= MIIM_88E151x_RGMII_RX_DELAY; diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 4d67203ee70..e1630e1c229 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Motorcomm 8531 PHY driver. + * Motorcomm YT8511/YT8531/YT8531S/YT8821/YT8521S PHY driver. * * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Copyright (C) 2024 Motorcomm Electronic Technology Co., Ltd. */ #include <config.h> @@ -13,6 +14,8 @@ #define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8531 0x4f51e91b #define PHY_ID_YT8821 0x4f51ea19 +#define PHY_ID_YT8531S 0x4f51e91a +#define PHY_ID_YT8521S 0x0000011a #define PHY_ID_MASK GENMASK(31, 0) /* Extended Register's Address Offset Register */ @@ -33,6 +36,17 @@ #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 +#define YT8521S_SCR_SYNCE_ENABLE BIT(5) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8521S_SCR_CLK_FRE_SEL_125M BIT(3) +#define YT8521S_SCR_CLK_SRC_MASK GENMASK(2, 1) +#define YT8521S_SCR_CLK_SRC_PLL_125M 0 +#define YT8521S_SCR_CLK_SRC_UTP_RX 1 +#define YT8521S_SCR_CLK_SRC_SDS_RX 2 +#define YT8521S_SCR_CLK_SRC_REF_25M 3 + #define YT8511_EXT_CLK_GATE 0x0c #define YT8511_EXT_DELAY_DRIVE 0x0d #define YT8511_EXT_SLEEP_CTRL 0x27 @@ -1114,6 +1128,151 @@ static int yt8821_startup(struct phy_device *phydev) return 0; } +static int yt8521s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8521S_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_SRC_MASK | + YT8521S_SCR_CLK_FRE_SEL_125M; + val = YT8521S_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8521S_SCR_CLK_SRC_MASK, + YT8521S_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_SRC_MASK | + YT8521S_SCR_CLK_FRE_SEL_125M; + val = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8521S_SCR_CLK_SRC_MASK, + YT8521S_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8531_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + ret = yt8531_parse_status(phydev); + if (ret) + return ret; + + return 0; +} + U_BOOT_PHY_DRIVER(motorcomm8511) = { .name = "YT8511 Gigabit Ethernet", .uid = PHY_ID_YT8511, @@ -1145,3 +1304,25 @@ U_BOOT_PHY_DRIVER(motorcomm8821) = { .startup = &yt8821_startup, .shutdown = &genphy_shutdown, }; + +U_BOOT_PHY_DRIVER(motorcomm8531S) = { + .name = "YT8531S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8531S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8531s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(motorcomm8521S) = { + .name = "YT8521S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8521S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8521s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..62d3f39f071 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -36,95 +36,94 @@ #define RSWITCH_MAX_CTAG_PCP 7 /* Registers */ -#define RSWITCH_COMA_OFFSET 0x00009000 -#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ -#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ +#define RSWITCH_COMA_OFFSET 0x00009000 +#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ +#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ #define RSWITCH_GWCA_OFFSET 0x00010000 #define RSWITCH_GWCA_SIZE 0x00002000 -#define FWRO 0 -#define CARO RSWITCH_COMA_OFFSET -#define GWRO 0 -#define TARO 0 -#define RMRO 0x1000 - -enum rswitch_reg { - EAMC = TARO + 0x0000, - EAMS = TARO + 0x0004, - EATDQDC = TARO + 0x0060, - EATTFC = TARO + 0x0138, - EATASRIRM = TARO + 0x03E4, - - GWMC = GWRO + 0x0000, - GWMS = GWRO + 0x0004, - GWMTIRM = GWRO + 0x0100, - GWVCC = GWRO + 0x0130, - GWTTFC = GWRO + 0x0138, - GWDCBAC0 = GWRO + 0x0194, - GWDCBAC1 = GWRO + 0x0198, - GWTRC = GWRO + 0x0200, - GWARIRM = GWRO + 0x0380, - GWDCC = GWRO + 0x0400, - - RRC = CARO + 0x0004, - RCEC = CARO + 0x0008, - RCDC = CARO + 0x000C, - CABPIRM = CARO + 0x0140, - - FWPC0 = FWRO + 0x0100, - FWPBFC = FWRO + 0x4A00, - FWPBFCSDC = FWRO + 0x4A04, - - MPSM = RMRO + 0x0000, - MPIC = RMRO + 0x0004, - MRMAC0 = RMRO + 0x0084, - MRMAC1 = RMRO + 0x0088, - MRAFC = RMRO + 0x008C, - MRSCE = RMRO + 0x0090, - MRSCP = RMRO + 0x0094, - MLVC = RMRO + 0x0180, - MLBC = RMRO + 0x0188, - MXGMIIC = RMRO + 0x0190, - MPCH = RMRO + 0x0194, - MANM = RMRO + 0x019C, - MMIS0 = RMRO + 0x0210, - MMIS1 = RMRO + 0x0220, -}; +#define FWRO 0 +#define CARO RSWITCH_COMA_OFFSET +#define GWRO 0 +#define TARO 0 +#define RMRO 0x1000 + +/* List of TSNA registers (ETHA) */ +#define EAMC (TARO + 0x0000) +#define EAMS (TARO + 0x0004) +#define EATDQDCR (TARO + 0x0060) +#define EATTFC (TARO + 0x0138) +#define EATASRIRM (TARO + 0x03e4) +/* Gateway CPU agent block (GWCA) */ +#define GWMC (GWRO + 0x0000) +#define GWMS (GWRO + 0x0004) +#define GWMTIRM (GWRO + 0x0100) +#define GWVCC (GWRO + 0x0130) +#define GWTTFC (GWRO + 0x0138) +#define GWDCBAC0 (GWRO + 0x0194) +#define GWDCBAC1 (GWRO + 0x0198) +#define GWTRCR (GWRO + 0x0200) +#define GWARIRM (GWRO + 0x0380) +#define GWDCCR (GWRO + 0x0400) +/* List of Common Agent registers (COMA) */ +#define RRC (CARO + 0x0004) +#define RCEC (CARO + 0x0008) +#define RCDC (CARO + 0x000c) +#define CABPIRM (CARO + 0x0140) +/* List of MFWD registers */ +#define FWPC (FWRO + 0x0100) +#define FWPBFCR (FWRO + 0x4a00) +#define FWPBFCSDCR (FWRO + 0x4a04) +/* List of RMAC registers (RMAC) */ +#define MPSM (RMRO + 0x0000) +#define MPIC (RMRO + 0x0004) +#define MRMAC0 (RMRO + 0x0084) +#define MRMAC1 (RMRO + 0x0088) +#define MRAFC (RMRO + 0x008c) +#define MRSCE (RMRO + 0x0090) +#define MRSCP (RMRO + 0x0094) +#define MLVC (RMRO + 0x0180) +#define MLBC (RMRO + 0x0188) +#define MXGMIIC (RMRO + 0x0190) +#define MPCH (RMRO + 0x0194) +#define MANM (RMRO + 0x019c) +#define MMIS0 (RMRO + 0x0210) +#define MMIS1 (RMRO + 0x0220) /* COMA */ -#define RRC_RR BIT(0) -#define RCEC_RCE BIT(16) +#define RRC_RR BIT(0) +#define RCEC_RCE BIT(16) -#define CABPIRM_BPIOG BIT(0) -#define CABPIRM_BPR BIT(1) +#define CABPIRM_BPIOG BIT(0) +#define CABPIRM_BPR BIT(1) /* MFWD */ -#define FWPC0(i) (FWPC0 + (i) * 0x10) -#define FWPC0_LTHTA BIT(0) -#define FWPC0_IP4UE BIT(3) -#define FWPC0_IP4TE BIT(4) -#define FWPC0_IP4OE BIT(5) -#define FWPC0_L2SE BIT(9) -#define FWPC0_IP4EA BIT(10) -#define FWPC0_IPDSA BIT(12) -#define FWPC0_IPHLA BIT(18) -#define FWPC0_MACSDA BIT(20) -#define FWPC0_MACHLA BIT(26) -#define FWPC0_MACHMA BIT(27) -#define FWPC0_VLANSA BIT(28) - -#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ - FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ - FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ - FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) - -#define FWPBFC(i) (FWPBFC + (i) * 0x10) -#define FWPBFCSDC(j, i) (FWPBFCSDC + (i) * 0x10 + (j) * 0x04) +#define FWPC0(i) (FWPC + (i) * 0x10) +#define FWPC0_LTHTA BIT(0) +#define FWPC0_IP4UE BIT(3) +#define FWPC0_IP4TE BIT(4) +#define FWPC0_IP4OE BIT(5) +#define FWPC0_L2SE BIT(9) +#define FWPC0_IP4EA BIT(10) +#define FWPC0_IPDSA BIT(12) +#define FWPC0_IPHLA BIT(18) +#define FWPC0_MACSDA BIT(20) +#define FWPC0_MACHLA BIT(26) +#define FWPC0_MACHMA BIT(27) +#define FWPC0_VLANSA BIT(28) + +#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ + FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ + FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ + FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) + +#define FWPBFC(i) (FWPBFCR + (i) * 0x10) +#define FWPBFCSDC(j, i) (FWPBFCSDCR + (i) * 0x10 + (j) * 0x04) /* ETHA */ #define EATASRIRM_TASRIOG BIT(0) #define EATASRIRM_TASRR BIT(1) -#define EATDQDC(q) (EATDQDC + (q) * 0x04) +#define EATDQDC(q) (EATDQDCR + (q) * 0x04) #define EATDQDC_DQD (0xff) /* RMAC */ @@ -149,8 +148,8 @@ enum rswitch_reg { #define MDIO_WRITE_C45 0x01 #define MDIO_ADDR_C45 0x00 -#define MDIO_READ_C22 0x02 -#define MDIO_WRITE_C22 0x01 +#define MDIO_READ_C22 0x02 +#define MDIO_WRITE_C22 0x01 #define MPSM_POP_MASK (0x03 << 13) #define MPSM_PRA_MASK (0x1f << 8) @@ -189,8 +188,8 @@ enum rswitch_gwca_mode { #define GWARIRM_ARR BIT(1) #define GWVCC_VEM_SC_TAG (0x3 << 16) #define GWDCBAC0_DCBAUP (0xff) -#define GWTRC(i) (GWTRC + (i) * 0x04) -#define GWDCC(i) (GWDCC + (i) * 0x04) +#define GWTRC(i) (GWTRCR + (i) * 0x04) +#define GWDCC(i) (GWDCCR + (i) * 0x04) #define GWDCC_DQT BIT(11) #define GWDCC_BALR BIT(24) @@ -356,15 +355,52 @@ static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv, return ret; } +static int rswitch_mii_access_c22(struct rswitch_etha *etha, bool read, + int phyad, int regad, int data) +{ + const u32 pop = read ? MDIO_READ_C22 : MDIO_WRITE_C22; + u32 val, pval; + int ret; + + /* Clear Station Management Mode : Clause 22 */ + clrbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + + /* Clear completion flags */ + writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); + + /* Submit C22 access to PHY */ + val = MPSM_PSME | (pop << 13) | (regad << 8) | (phyad << 3); + if (!read) + val |= data << 16; + writel(val, etha->addr + MPSM); + + ret = readl_poll_sleep_timeout(etha->addr + MPSM, pval, + !(pval & MPSM_PSME), + RSWITCH_SLEEP_US, + RSWITCH_TIMEOUT_US); + if (ret) + return ret; + + if (!read) + return 0; + + /* Read data */ + ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; + + /* Clear read completion flag */ + setbits_le32(etha->addr + MMIS1, MMIS1_PRACS); + + return ret; +} + static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read, int phyad, int devad, int regad, int data) { u32 pval, val; int ret; - /* No match device */ - if (devad == 0xffffffff) - return 0; + /* Set Station Management Mode : Clause 45 */ + setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); /* Clear completion flags */ writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); @@ -418,7 +454,6 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; int val; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -427,15 +462,17 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + val = rswitch_mii_access_c45(etha, true, phyad, 1, regad, 0); + else + val = rswitch_mii_access_c22(etha, true, phyad, regad, 0); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -450,7 +487,6 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega { struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -459,15 +495,17 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + rswitch_mii_access_c45(etha, false, phyad, 1, regad, data); + else + rswitch_mii_access_c22(etha, false, phyad, regad, data); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -837,6 +875,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; @@ -1112,6 +1151,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 73edb355160..d138867666b 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -4,6 +4,7 @@ config NVME bool "NVM Express device support" + select BLK help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 876a5fa57ee..4f876d39875 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -189,19 +189,19 @@ config PCI_MSC01 depends on TARGET_MALTA config PCI_RCAR_GEN2 - bool "Renesas RCar Gen2 PCIe driver" + bool "Renesas R-Car Gen2 PCIe driver" depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is + Renesas R-Car Gen2 SoCs. The PCIe controller on R-Car Gen2 is also used to access EHCI USB controller on the SoC. config PCI_RCAR_GEN3 - bool "Renesas RCar Gen3 PCIe driver" + bool "Renesas R-Car Gen3 PCIe driver" depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen3 SoCs. + Renesas R-Car Gen3 SoCs. config PCI_SANDBOX bool "Sandbox PCI support" @@ -371,6 +371,14 @@ config PCIE_DW_MESON Say Y here if you want to enable DW PCIe controller support on Amlogic SoCs. +config PCIE_DW_QCOM + bool "Qualcomm DesignWare based PCIe controller" + depends on ARCH_SNAPDRAGON + select PCIE_DW_COMMON + help + Say Y here if you want to enable DW PCIe controller support on + Qualcomm SoCs. + config PCIE_ROCKCHIP bool "Enable Rockchip PCIe driver" depends on ARCH_ROCKCHIP diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bf361cd0fba..ba53f594963 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie_mediatek_gen3.o obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o obj-$(CONFIG_PCIE_DW_ROCKCHIP) += pcie_dw_rockchip.o obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o +obj-$(CONFIG_PCIE_DW_QCOM) += pcie_dw_qcom.o obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 12c31e74087..08d5c4fbb8b 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 PCIEC driver + * Renesas R-Car Gen2 PCIEC driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 76878246f1e..d4b4037ce19 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 PCIEC driver + * Renesas R-Car Gen3 PCIEC driver * * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com> * diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 0673e516c6f..78961271a8e 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -267,6 +267,48 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, pcie->io.bus_start, pcie->io.size); } +/* + * These interfaces resemble the pci_find_*capability() interfaces, but these + * are for configuring host controllers, which are bridges *to* PCI devices but + * are not PCI devices themselves. + */ +static u8 pcie_dw_find_next_cap(struct pcie_dw *pci, u8 cap_ptr, u8 cap) +{ + u8 cap_id, next_cap_ptr; + u32 val; + u16 reg; + + if (!cap_ptr) + return 0; + + val = readl(pci->dbi_base + (cap_ptr & ~0x3)); + reg = pci_conv_32_to_size(val, cap_ptr, 2); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap) +{ + u8 next_cap_ptr; + u32 val; + u16 reg; + + val = readl(pci->dbi_base + (PCI_CAPABILITY_LIST & ~0x3)); + reg = pci_conv_32_to_size(val, PCI_CAPABILITY_LIST, 2); + + next_cap_ptr = (reg & 0x00ff); + + return pcie_dw_find_next_cap(pci, next_cap_ptr, cap); +} + /** * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion * diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index e0f7796f2a8..8cb99a12ea1 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -139,6 +139,8 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, u int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +u8 pcie_dw_find_capability(struct pcie_dw *pci, u8 cap); + static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en) { u32 val; diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c new file mode 100644 index 00000000000..39b4cd4efe2 --- /dev/null +++ b/drivers/pci/pcie_dw_qcom.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <pci.h> +#include <u-boot/crc.h> +#include <power-domain.h> +#include <reset.h> +#include <syscon.h> +#include <malloc.h> +#include <power/regulator.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <dm/device_compat.h> +#include <linux/iopoll.h> +#include <linux/delay.h> +#include <linux/log2.h> +#include <linux/bitfield.h> + +#include "pcie_dw_common.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct qcom_pcie; + +struct qcom_pcie_ops { + int (*config_sid)(struct qcom_pcie *priv); +}; + +#define NUM_SUPPLIES 2 + +struct qcom_pcie { + /* Must be first member of the struct */ + struct pcie_dw dw; + void *parf; + struct phy phy; + struct reset_ctl_bulk rsts; + struct clk_bulk clks; + struct gpio_desc rst_gpio; + struct qcom_pcie_ops *ops; + struct udevice *vregs[NUM_SUPPLIES]; +}; + +/* PARF registers */ +#define PARF_SYS_CTRL 0x00 +#define PARF_PM_CTRL 0x20 +#define PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_SWING 0x38 +#define PARF_PHY_CTRL 0x40 +#define PARF_PHY_REFCLK 0x4c +#define PARF_CONFIG_BITS 0x50 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +#define PARF_Q2A_FLUSH 0x1ac +#define PARF_LTSSM 0x1b0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24c +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 + +/* ELBI registers */ +#define ELBI_SYS_CTRL 0x04 + +/* DBI registers */ +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define MISC_CONTROL_1_REG 0x8bc + +/* MHI registers */ +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 + +/* PARF_SYS_CTRL register fields */ +#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define MST_WAKEUP_EN BIT(13) +#define SLV_WAKEUP_EN BIT(12) +#define MSTR_ACLK_CGC_DIS BIT(10) +#define SLV_ACLK_CGC_DIS BIT(9) +#define CORE_CLK_CGC_DIS BIT(6) +#define AUX_PWR_DET BIT(4) +#define L23_CLK_RMV_DIS BIT(2) +#define L1_CLK_RMV_DIS BIT(1) + +/* PARF_PM_CTRL register fields */ +#define REQ_NOT_ENTR_L1 BIT(5) + +/* PARF_PCS_DEEMPH register fields */ +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) + +/* PARF_PCS_SWING register fields */ +#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) +#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) + +/* PARF_PHY_CTRL register fields */ +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) +#define PHY_TEST_PWR_DOWN BIT(0) + +/* PARF_PHY_REFCLK register fields */ +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + +/* PARF_CONFIG_BITS register fields */ +#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) + +/* PARF_SLV_ADDR_SPACE_SIZE register value */ +#define SLV_ADDR_SPACE_SZ 0x10000000 + +/* PARF_MHI_CLOCK_RESET_CTRL register fields */ +#define AHB_CLK_EN BIT(0) +#define MSTR_AXI_CLK_EN BIT(1) +#define BYPASS BIT(4) + +/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ +#define EN BIT(31) + +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + +/* PARF_DEVICE_TYPE register fields */ +#define DEVICE_TYPE_RC 0x4 + +/* ELBI_SYS_CTRL register fields */ +#define ELBI_SYS_CTRL_LT_ENABLE BIT(0) + +/* AXI_MSTR_RESP_COMP_CTRL0 register fields */ +#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 +#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 + +/* AXI_MSTR_RESP_COMP_CTRL1 register fields */ +#define CFG_BRIDGE_SB_INIT BIT(0) + +/* MISC_CONTROL_1_REG register fields */ +#define DBI_RO_WR_EN 1 + +/* PCI_EXP_SLTCAP register fields */ +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) +#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ + PCI_EXP_SLTCAP_PCP | \ + PCI_EXP_SLTCAP_MRLSP | \ + PCI_EXP_SLTCAP_AIP | \ + PCI_EXP_SLTCAP_PIP | \ + PCI_EXP_SLTCAP_HPS | \ + PCI_EXP_SLTCAP_HPC | \ + PCI_EXP_SLTCAP_EIP | \ + PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ + PCIE_CAP_SLOT_POWER_LIMIT_SCALE) + +#define PERST_DELAY_US 1000 + +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP 100000 + +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) + +#define CRC8_TABLE_SIZE 256 + +static bool qcom_pcie_wait_link_up(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + unsigned int cnt = 0; + u16 val; + + do { + val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA); + + if ((val & PCI_EXP_LNKSTA_DLLLA)) + return true; + cnt++; + + udelay(LINK_WAIT_USLEEP); + } while (cnt < LINK_WAIT_MAX_RETRIES); + + return false; +} + +static void qcom_pcie_clear_aspm_l0s(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPM_L0S; + writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static void qcom_pcie_clear_hpc(struct qcom_pcie *priv) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); + val &= ~PCI_EXP_SLTCAP_HPC; + writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static void qcom_pcie_set_lanes(struct qcom_pcie *priv, unsigned int lanes) +{ + u8 offset = pcie_dw_find_capability(&priv->dw, PCI_CAP_ID_EXP); + u32 val; + + val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_MLW; + val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, lanes); + writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); +} + +static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *priv) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + void *bdf_to_sid_base = priv->parf + PARF_BDF_TO_SID_TABLE_N; + int i, nr_map, size = 0; + u32 smmu_sid_base; + + dev_read_prop(priv->dw.dev, "iommu-map", &size); + if (!size) + return 0; + + map = malloc(size); + if (!map) + return -ENOMEM; + + dev_read_u32_array(priv->dw.dev, "iommu-map", (u32 *)map, size / sizeof(u32)); + + nr_map = size / (sizeof(*map)); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Extract the SMMU SID base from the first entry of iommu-map */ + smmu_sid_base = map[0].smmu_sid; + + /* Look for an available entry to hold the mapping */ + for (i = 0; i < nr_map; i++) { + __be16 bdf_be = cpu_to_be16(map[i].bdf); + u32 val; + u8 hash; + + hash = crc8(QCOM_PCIE_CRC8_POLYNOMIAL, (u8 *)&bdf_be, sizeof(bdf_be)); + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If the register is already populated, look for next available entry */ + while (val) { + u8 current_hash = hash++; + u8 next_mask = 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + val |= (u32)hash; + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); + } + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + } + + free(map); + + return 0; +} + +static void qcom_pcie_configure(struct qcom_pcie *priv) +{ + u32 val; + + dw_pcie_dbi_write_enable(&priv->dw, true); + + val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; + val &= ~PORT_LINK_MODE_MASK; + val |= PORT_LINK_MODE_2_LANES; + writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); + + val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + val |= PORT_LOGIC_LINK_WIDTH_2_LANES; + writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + + qcom_pcie_set_lanes(priv, 2); + + dw_pcie_dbi_write_enable(&priv->dw, false); +} + +static int qcom_pcie_init_port(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + int vreg, ret; + u32 val; + + dm_gpio_set_value(&priv->rst_gpio, 1); + udelay(PERST_DELAY_US); + + ret = generic_phy_init(&priv->phy); + if (ret) { + dev_err(dev, "failed to init phy (%d)\n", ret); + return ret; + } + + udelay(PERST_DELAY_US); + + for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) { + ret = regulator_set_enable(priv->vregs[vreg], true); + if (ret && ret != -ENOSYS) + dev_warn(dev, "failed to enable regulator %d (%d)\n", vreg, ret); + } + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + dev_err(dev, "failed to enable clocks (%d)\n", ret); + goto err_power_off_phy; + } + + ret = reset_assert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to assert resets (%d)\n", ret); + goto err_disable_clks; + } + + udelay(PERST_DELAY_US); + + ret = reset_deassert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to deassert resets (%d)\n", ret); + goto err_power_off_phy; + } + + udelay(PERST_DELAY_US); + + /* configure PCIe to RC mode */ + writel(DEVICE_TYPE_RC, priv->parf + PARF_DEVICE_TYPE); + + /* enable PCIe clocks and resets */ + val = readl(priv->parf + PARF_PHY_CTRL); + val &= ~PHY_TEST_PWR_DOWN; + writel(val, priv->parf + PARF_PHY_CTRL); + + /* change DBI base address */ + writel(0, priv->parf + PARF_DBI_BASE_ADDR); + + /* MAC PHY_POWERDOWN MUX DISABLE */ + val = readl(priv->parf + PARF_SYS_CTRL); + val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; + writel(val, priv->parf + PARF_SYS_CTRL); + + val = readl(priv->parf + PARF_MHI_CLOCK_RESET_CTRL); + val |= BYPASS; + writel(val, priv->parf + PARF_MHI_CLOCK_RESET_CTRL); + + /* Enable L1 and L1SS */ + val = readl(priv->parf + PARF_PM_CTRL); + val &= ~REQ_NOT_ENTR_L1; + writel(val, priv->parf + PARF_PM_CTRL); + + val = readl(priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val |= EN; + writel(val, priv->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); + + ret = generic_phy_power_on(&priv->phy); + if (ret) { + dev_err(dev, "failed to power on phy (%d)\n", ret); + goto err_exit_phy; + } + + qcom_pcie_clear_aspm_l0s(priv); + qcom_pcie_clear_hpc(priv); + + mdelay(100); + dm_gpio_set_value(&priv->rst_gpio, 0); + udelay(PERST_DELAY_US); + + if (priv->ops && priv->ops->config_sid) { + ret = priv->ops->config_sid(priv); + if (ret) + goto err_deassert_bulk; + } + + qcom_pcie_configure(priv); + + pcie_dw_setup_host(&priv->dw); + + /* enable link training */ + val = readl(priv->parf + PARF_LTSSM); + val |= LTSSM_EN; + writel(val, priv->parf + PARF_LTSSM); + + return 0; +err_deassert_bulk: + reset_assert_bulk(&priv->rsts); +err_disable_clks: + clk_disable_bulk(&priv->clks); +err_power_off_phy: + generic_phy_power_off(&priv->phy); +err_exit_phy: + generic_phy_exit(&priv->phy); + + return ret; +} + +static const char *qcom_pcie_vregs[NUM_SUPPLIES] = { + "vdda-supply", + "vddpe-3v3-supply", +}; + +static int qcom_pcie_parse_dt(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + int vreg, ret; + + priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi"); + if (!priv->dw.dbi_base) + return -EINVAL; + + dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); + + priv->dw.atu_base = dev_read_addr_name_ptr(dev, "atu"); + if (!priv->dw.atu_base) + return -EINVAL; + + dev_dbg(dev, "ATU address is 0x%p\n", priv->dw.atu_base); + + priv->parf = dev_read_addr_name_ptr(dev, "parf"); + if (!priv->parf) + return -EINVAL; + + dev_dbg(dev, "PARF address is 0x%p\n", priv->parf); + + ret = gpio_request_by_name(dev, "perst-gpios", 0, + &priv->rst_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "failed to find reset-gpios property\n"); + return ret; + } + + ret = reset_get_bulk(dev, &priv->rsts); + if (ret) { + dev_err(dev, "failed to get resets (%d)\n", ret); + return ret; + } + + ret = clk_get_bulk(dev, &priv->clks); + if (ret) { + dev_err(dev, "failed to get clocks (%d)\n", ret); + return ret; + } + + ret = generic_phy_get_by_index(dev, 0, &priv->phy); + if (ret) { + dev_err(dev, "failed to get pcie phy (%d)\n", ret); + return ret; + } + + for (vreg = 0; vreg < NUM_SUPPLIES; ++vreg) { + ret = device_get_supply_regulator(dev, qcom_pcie_vregs[vreg], &priv->vregs[vreg]); + if (ret) + dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret); + } + + return 0; +} + +/** + * qcom_pcie_probe() - Probe the PCIe bus for active link + * + * @dev: A pointer to the device being operated on + * + * Probe for an active link on the PCIe bus and configure the controller + * to enable this port. + * + * Return: 0 on success, else -ENODEV + */ +static int qcom_pcie_probe(struct udevice *dev) +{ + struct qcom_pcie *priv = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + int ret = 0; + + priv->dw.first_busno = dev_seq(dev); + priv->dw.dev = dev; + + ret = qcom_pcie_parse_dt(dev); + if (ret) + return ret; + + ret = qcom_pcie_init_port(dev); + if (ret) { + dm_gpio_free(dev, &priv->rst_gpio); + return ret; + } + + if (qcom_pcie_wait_link_up(priv)) + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", + dev_seq(dev), pcie_dw_get_link_speed(&priv->dw), + pcie_dw_get_link_width(&priv->dw), + hose->first_busno); + else + printf("PCIE-%d: Link up timeout\n", dev_seq(dev)); + + return pcie_dw_prog_outbound_atu_unroll(&priv->dw, + PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + priv->dw.mem.phys_start, + priv->dw.mem.bus_start, + priv->dw.mem.size); +} + +static const struct dm_pci_ops qcom_pcie_ops = { + .read_config = pcie_dw_read_config, + .write_config = pcie_dw_write_config, +}; + +static const struct qcom_pcie_ops ops_1_9_0 = { + .config_sid = qcom_pcie_config_sid_1_9_0, +}; + +static const struct udevice_id qcom_pcie_ids[] = { + { .compatible = "qcom,pcie-sa8540p", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc7280", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sc8280xp", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sdm845" }, + { .compatible = "qcom,pcie-sdx55", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8150", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8250", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8350", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = (ulong)&ops_1_9_0 }, + { .compatible = "qcom,pcie-x1e80100", .data = (ulong)&ops_1_9_0 }, + { } +}; + +U_BOOT_DRIVER(qcom_dw_pcie) = { + .name = "pcie_dw_qcom", + .id = UCLASS_PCI, + .of_match = qcom_pcie_ids, + .ops = &qcom_pcie_ops, + .probe = qcom_pcie_probe, + .priv_auto = sizeof(struct qcom_pcie), +}; diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f9428c7ad12..be736629d51 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 USB PHY driver + * Renesas R-Car Gen2 USB PHY driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index b278f995f37..8c004eaf4c6 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 USB PHY driver + * Renesas R-Car Gen3 USB PHY driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 5c77203d606..61e5e2fca41 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -12,6 +12,12 @@ config PHY_QCOM_IPQ4019_USB help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QMP_PCIE + tristate "Qualcomm QMP PCIe PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the PCIe QMP PHY on various Qualcomm chipsets. + config PHY_QCOM_QMP_UFS tristate "Qualcomm QMP UFS PHY driver" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index dc3ed492696..1c4e7d8d391 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h b/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h new file mode 100644 index 00000000000..e4a4d2cd85e --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcie-qhp.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCIE_QHP_H_ +#define QCOM_PHY_QMP_PCIE_QHP_H_ + +/* PCIE GEN3 COM registers */ +#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 +#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 +#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 +#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 +#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 +#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 +#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 +#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c +#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 +#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc +#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc +#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 +#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 +#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c +#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 +#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 +#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 +#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 +#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc +#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 +#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 +#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 +#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 +#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc +#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c +#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 +#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c + +/* PCIE GEN3 QHP Lane registers */ +#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc +#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 +#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 +#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 +#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 +#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 +#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 +#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 +#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc +#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 +#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc +#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 +#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 +#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 +#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 +#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c +#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 +#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 +#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 +#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 +#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 +#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 +#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c +#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 +#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 +#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c +#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 +#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 +#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 +#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 +#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c +#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 +#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 +#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 +#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 +#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 +#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 +#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 +#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac +#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 +#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 +#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 +#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 +#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc + +/* PCIE GEN3 PCS registers */ +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 +#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 +#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c +#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c +#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcie.c b/drivers/phy/qcom/phy-qcom-qmp-pcie.c new file mode 100644 index 00000000000..2f6ff259b35 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcie.c @@ -0,0 +1,1131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> +#include <power/regulator.h> + +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/ioport.h> + +#include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-v5.h" +#include "phy-qcom-qmp-pcs-v6.h" +#include "phy-qcom-qmp-pcs-v6_20.h" +#include "phy-qcom-qmp-pcs-pcie-v6.h" +#include "phy-qcom-qmp-pcs-pcie-v6_20.h" +#include "phy-qcom-qmp-pcie-qhp.h" +#include "phy-qcom-qmp-qserdes-com-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6.h" +#include "phy-qcom-qmp-qserdes-txrx-v6_20.h" +#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" + +/* QPHY_SW_RESET bit */ +#define SW_RESET BIT(0) +/* QPHY_POWER_DOWN_CONTROL */ +#define SW_PWRDN BIT(0) +#define REFCLK_DRV_DSBL BIT(1) +/* QPHY_START_CONTROL bits */ +#define SERDES_START BIT(0) +#define PCS_START BIT(1) +/* QPHY_PCS_READY_STATUS bit */ +#define PCS_READY BIT(0) + +/* QPHY_PCS_STATUS bit */ +#define PHYSTATUS BIT(6) +#define PHYSTATUS_4_20 BIT(7) + +#define PHY_INIT_COMPLETE_TIMEOUT (200 * 10000) + +#define NUM_SUPPLIES 3 + +struct qmp_pcie_init_tbl { + unsigned int offset; + unsigned int val; + /* + * mask of lanes for which this register is written + * for cases when second lane needs different values + */ + u8 lane_mask; +}; + +#define QMP_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = 0xff, \ + } + +#define QMP_PHY_INIT_CFG_LANE(o, v, l) \ + { \ + .offset = o, \ + .val = v, \ + .lane_mask = l, \ + } + +/* set of registers with offsets different per-PHY */ +enum qphy_reg_layout { + /* PCS registers */ + QPHY_SW_RESET, + QPHY_START_CTRL, + QPHY_PCS_STATUS, + QPHY_PCS_POWER_DOWN_CONTROL, + /* Keep last to ensure regs_layout arrays are properly initialized */ + QPHY_LAYOUT_SIZE +}; + +static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, +}; + +static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), +}; + +static const struct qmp_pcie_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), +}; + +static const struct qmp_pcie_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), + QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), + QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), +}; + +static const struct qmp_pcie_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), +}; + +struct qmp_pcie_offsets { + u16 serdes; + u16 pcs; + u16 pcs_misc; + u16 tx; + u16 rx; + u16 tx2; + u16 rx2; + u16 ln_shrd; +}; + +struct qmp_pcie_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_pcie_init_tbl *serdes; + int serdes_num; + const struct qmp_pcie_init_tbl *tx; + int tx_num; + const struct qmp_pcie_init_tbl *rx; + int rx_num; + const struct qmp_pcie_init_tbl *pcs; + int pcs_num; + const struct qmp_pcie_init_tbl *pcs_misc; + int pcs_misc_num; + const struct qmp_pcie_init_tbl *ln_shrd; + int ln_shrd_num; +}; + +/* struct qmp_pcie_cfg - per-PHY initialization config */ +struct qmp_pcie_cfg { + int lanes; + + const struct qmp_pcie_offsets *offsets; + + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_pcie_cfg_tbls tbls; + + /* regulators to be requested */ + const char * const *vreg_list; + int num_vregs; + /* resets to be requested */ + const char * const *reset_list; + int num_resets; + + /* array of registers with different offsets */ + const unsigned int *regs; + + unsigned int pwrdn_ctrl; + /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ + unsigned int phy_status; + + bool has_nocsr_reset; +}; + +struct qmp_pcie_priv { + struct phy *phy; + + void __iomem *serdes; + void __iomem *pcs; + void __iomem *pcs_misc; + void __iomem *tx; + void __iomem *rx; + void __iomem *tx2; + void __iomem *rx2; + void __iomem *ln_shrd; + + struct clk *clks; + unsigned int clk_count; + + struct clk pipe_clk; + + struct reset_ctl *resets; + unsigned int reset_count; + + struct reset_ctl nocsr_reset; + + struct udevice *vregs[NUM_SUPPLIES]; + unsigned int vreg_count; + + const struct qmp_pcie_cfg *cfg; + struct udevice *dev; +}; + +static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg |= val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) +{ + u32 reg; + + reg = readl(base + offset); + reg &= ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +/* list of clocks required by phy */ +static const char * const qmp_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "rchng", +}; + +/* list of regulators */ +static const char * const qmp_phy_vreg_l[] = { + "vdda-phy-supply", "vdda-pll-supply", +}; + +static const char * const sm8550_qmp_phy_vreg_l[] = { + "vdda-phy-supply", "vdda-pll-supply", "vdda-qref-supply", +}; + +/* list of resets */ +static const char * const sdm845_pciephy_reset_l[] = { + "phy", +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { + .serdes = 0, + .pcs = 0x0200, + .pcs_misc = 0x0600, + .tx = 0x0e00, + .rx = 0x1000, + .tx2 = 0x1600, + .rx2 = 0x1800, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { + .serdes = 0x1000, + .pcs = 0x1200, + .pcs_misc = 0x1400, + .tx = 0x0000, + .rx = 0x0200, + .tx2 = 0x0800, + .rx2 = 0x0a00, + .ln_shrd = 0x0e00, +}; + +static const struct qmp_pcie_cfg sm8550_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tbls = { + .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_pcie_cfg sm8550_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), + .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static const struct qmp_pcie_cfg sm8650_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), + .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), + .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), + .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = sm8550_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static const struct qmp_pcie_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v6_20, + + .tbls = { + .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), + .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), + .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), + .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), + .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), + .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, + .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v6_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, + .has_nocsr_reset = true, +}; + +static void qmp_pcie_configure_lane(void __iomem *base, + const struct qmp_pcie_init_tbl tbl[], + int num, u8 lane_mask) +{ + int i; + const struct qmp_pcie_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) { + if (!(t->lane_mask & lane_mask)) + continue; + + writel(t->val, base + t->offset); + } +} + +static void qmp_pcie_configure(void __iomem *base, + const struct qmp_pcie_init_tbl tbl[], + int num) +{ + qmp_pcie_configure_lane(base, tbl, num, 0xff); +} + +static void qmp_pcie_init_registers(struct qmp_pcie_priv *qmp, const struct qmp_pcie_cfg *cfg) +{ + const struct qmp_pcie_cfg_tbls *tbls = &cfg->tbls; + void __iomem *serdes = qmp->serdes; + void __iomem *tx = qmp->tx; + void __iomem *rx = qmp->rx; + void __iomem *tx2 = qmp->tx2; + void __iomem *rx2 = qmp->rx2; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; + void __iomem *ln_shrd = qmp->ln_shrd; + + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); + + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >= 2) { + qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); + qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); + } + + qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); + qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); +} + +static int qmp_pcie_do_reset(struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + int i, ret; + + for (i = 0; i < qmp->reset_count; i++) { + ret = reset_assert(&qmp->resets[i]); + if (ret) + return ret; + } + + if (cfg->has_nocsr_reset) + reset_assert(&qmp->nocsr_reset); + + udelay(10); + + for (i = 0; i < qmp->reset_count; i++) { + ret = reset_deassert(&qmp->resets[i]); + if (ret) + return ret; + } + + udelay(50); + + return 0; +} + +static int qmp_pcie_power_on(struct phy *phy) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(phy->dev); + const struct qmp_pcie_cfg *cfg = qmp->cfg; + void __iomem *pcs = qmp->pcs; + void __iomem *status; + unsigned int mask, val; + int ret, i; + + for (i = 0; i < qmp->vreg_count; i++) { + ret = regulator_set_enable(qmp->vregs[i], true); + if (ret && ret != -ENOSYS) + dev_err(phy->dev, "failed to enable regulator %d (%d)\n", i, ret); + } + + ret = qmp_pcie_do_reset(qmp); + if (ret) + return ret; + + for (i = 0; i < qmp->clk_count; i++) { + ret = clk_enable(&qmp->clks[i]); + if (ret && ret != -ENOSYS) { + dev_err(phy->dev, "failed to enable clock %d\n", i); + return ret; + } + } + + /* Power down PHY */ + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); + + qmp_pcie_init_registers(qmp, cfg); + + clk_enable(&qmp->pipe_clk); + + if (cfg->has_nocsr_reset) + reset_deassert(&qmp->nocsr_reset); + + /* Pull PHY out of reset state */ + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* start SerDes */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); + + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ret = readl_poll_timeout(status, val, !(val & mask), PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(phy->dev, "phy initialization timed-out\n"); + return ret; + } + + return 0; +} + +static int qmp_pcie_power_off(struct phy *phy) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(phy->dev); + const struct qmp_pcie_cfg *cfg = qmp->cfg; + + clk_disable(&qmp->pipe_clk); + + /* PHY reset */ + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], + SERDES_START | PCS_START); + + /* Put PHY into POWER DOWN state: active low */ + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + + return 0; +} + +static int qmp_pcie_vreg_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + unsigned int vreg; + int ret; + + qmp->vreg_count = cfg->num_vregs; + + for (vreg = 0; vreg < NUM_SUPPLIES && vreg < qmp->vreg_count; ++vreg) { + ret = device_get_supply_regulator(dev, cfg->vreg_list[vreg], &qmp->vregs[vreg]); + if (ret) + dev_warn(dev, "failed to get regulator %d (%d)\n", vreg, ret); + + regulator_set_enable(qmp->vregs[vreg], true); + } + + return 0; +} + +static int qmp_pcie_reset_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_cfg *cfg = qmp->cfg; + int num = cfg->num_resets; + int i, ret; + + qmp->reset_count = 0; + qmp->resets = devm_kcalloc(dev, num, sizeof(*qmp->resets), GFP_KERNEL); + if (!qmp->resets) + return -ENOMEM; + + for (i = 0; i < num; i++) { + ret = reset_get_by_name(dev, cfg->reset_list[i], &qmp->resets[i]); + if (ret) { + dev_err(dev, "failed to get reset %d\n", i); + goto reset_get_err; + } + + ++qmp->reset_count; + } + + if (cfg->has_nocsr_reset) { + ret = reset_get_by_name(dev, "phy_nocsr", &qmp->nocsr_reset); + if (ret) + dev_warn(dev, "failed to get nocsr reset\n"); + } + + return 0; + +reset_get_err: + reset_release_all(qmp->resets, qmp->reset_count); + + return ret; +} + +static int qmp_pcie_clk_init(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + int num = ARRAY_SIZE(qmp_pciephy_clk_l); + int i, ret; + + qmp->clk_count = 0; + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i = 0; i < num; i++) { + ret = clk_get_by_name(dev, qmp_pciephy_clk_l[i], &qmp->clks[i]); + /* Ignore failure to get ref clock */ + if (ret && strcmp(qmp_pciephy_clk_l[i], "ref") != 0) { + dev_err(dev, "failed to get clock %d\n", i); + goto clk_get_err; + } + + ++qmp->clk_count; + } + + ret = clk_get_by_name(dev, "pipe", &qmp->pipe_clk); + if (ret) + dev_warn(dev, "failed to get pipe clock\n"); + + return 0; + +clk_get_err: + clk_release_all(qmp->clks, qmp->clk_count); + + return ret; +} + +static int qmp_pcie_parse_dt(struct udevice *dev, struct qmp_pcie_priv *qmp) +{ + const struct qmp_pcie_offsets *offs = qmp->cfg->offsets; + const struct qmp_pcie_cfg *cfg = qmp->cfg; + struct resource res; + int ret; + + if (!qmp->cfg->offsets) { + dev_err(dev, "missing PCIE offsets\n"); + return -EINVAL; + } + + ret = ofnode_read_resource(dev_ofnode(dev), 0, &res); + if (ret) { + dev_err(dev, "can't get reg property\n"); + return ret; + } + + qmp->serdes = (void __iomem *)res.start + offs->serdes; + qmp->pcs = (void __iomem *)res.start + offs->pcs; + qmp->pcs_misc = (void __iomem *)res.start + offs->pcs_misc; + qmp->tx = (void __iomem *)res.start + offs->tx; + qmp->rx = (void __iomem *)res.start + offs->rx; + + if (qmp->cfg->lanes >= 2) { + qmp->tx2 = (void __iomem *)res.start + offs->tx2; + qmp->rx2 = (void __iomem *)res.start + offs->rx2; + } + + if (cfg->tbls.ln_shrd) + qmp->ln_shrd = (void __iomem *)res.start + offs->ln_shrd; + + return 0; +} + +static int qmp_pcie_probe(struct udevice *dev) +{ + struct qmp_pcie_priv *qmp = dev_get_priv(dev); + int ret; + + qmp->serdes = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qmp->serdes)) + return PTR_ERR(qmp->serdes); + + qmp->cfg = (const struct qmp_pcie_cfg *)dev_get_driver_data(dev); + if (!qmp->cfg) + return -EINVAL; + + ret = qmp_pcie_clk_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE clks\n"); + return ret; + } + + ret = qmp_pcie_vreg_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE voltage regulators\n"); + return ret; + } + + ret = qmp_pcie_reset_init(dev, qmp); + if (ret) { + dev_err(dev, "failed to get PCIE resets\n"); + return ret; + } + + qmp->dev = dev; + + return qmp_pcie_parse_dt(dev, qmp); +} + +static struct phy_ops qmp_pcie_ops = { + .power_on = qmp_pcie_power_on, + .power_off = qmp_pcie_power_off, +}; + +static const struct udevice_id qmp_pcie_ids[] = { + { + .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", + .data = (ulong)&sm8650_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", + .data = (ulong)&sm8550_qmp_gen3x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", + .data = (ulong)&x1e80100_qmp_gen4x2_pciephy_cfg + }, { + .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", + .data = (ulong)&x1e80100_qmp_gen4x2_pciephy_cfg + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(qcom_qmp_pcie) = { + .name = "qcom-qmp-pcie", + .id = UCLASS_PHY, + .of_match = qmp_pcie_ids, + .ops = &qmp_pcie_ops, + .probe = qmp_pcie_probe, + .priv_auto = sizeof(struct qmp_pcie_priv), +}; diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h new file mode 100644 index 00000000000..a45bd301bc9 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-misc-v3.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_ +#define QCOM_PHY_QMP_PCS_MISC_V3_H_ + +/* Only for QMP V3 PHY - PCS_MISC registers */ +#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c +#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c +#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c +#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h new file mode 100644 index 00000000000..4cc02288d41 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_H_ + +/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 +#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c +#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 +#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 +#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 +#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 +#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 +#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 +#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 +#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 +#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 +#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c +#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 +#define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 +#define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 +#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c +#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 +#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 +#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 +#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc +#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 +#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc +#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 +#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 +#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 +#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec +#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h new file mode 100644 index 00000000000..ac872a9eff9 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ + +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 +#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 +#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h new file mode 100644 index 00000000000..2801bcf10f2 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_H_ + +/* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h new file mode 100644 index 00000000000..cdf8c04ea07 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_ + +/* Only for QMP V5_20 PHY - PCIe PCS registers */ +#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 +#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 +#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 +#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc +#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 +#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c +#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 +#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 +#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h new file mode 100644 index 00000000000..0ca79333d94 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_H_ + +/* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4 +#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4 +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h new file mode 100644 index 00000000000..dfcecf31a60 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ + +/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h new file mode 100644 index 00000000000..36cc80bb905 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v5.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_H_ +#define QCOM_PHY_QMP_PCS_V5_H_ + +/* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_SW_RESET 0x000 +#define QPHY_V5_PCS_PCS_STATUS1 0x014 +#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V5_PCS_START_CONTROL 0x044 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V5_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V5_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V5_PCS_RX_CONFIG 0x1b0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V5_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V5_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V5_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 +#define QPHY_V5_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h new file mode 100644 index 00000000000..08299d2b78f --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_H_ +#define QCOM_PHY_QMP_PCS_V6_H_ + +/* Only for QMP V6 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_PCS_SW_RESET 0x000 +#define QPHY_V6_PCS_PCS_STATUS1 0x014 +#define QPHY_V6_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V6_PCS_START_CONTROL 0x044 +#define QPHY_V6_PCS_POWER_STATE_CONFIG1 0x090 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1 0x0c4 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2 0x0c8 +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3 0x0cc +#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6 0x0d8 +#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V6_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V6_PCS_EQ_CONFIG1 0x1dc +#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0 +#define QPHY_V6_PCS_EQ_CONFIG5 0x1ec + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h new file mode 100644 index 00000000000..4d9615cc038 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v6_20.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_V6_20_H_ +#define QCOM_PHY_QMP_PCS_V6_20_H_ + +/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170 +#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h new file mode 100644 index 00000000000..c8afdf7bc1e --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V5_H_ + +/* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_ATB_SEL1 0x000 +#define QSERDES_V5_COM_ATB_SEL2 0x004 +#define QSERDES_V5_COM_FREQ_UPDATE 0x008 +#define QSERDES_V5_COM_BG_TIMER 0x00c +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V5_COM_SSC_PER1 0x01c +#define QSERDES_V5_COM_SSC_PER2 0x020 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 +#define QSERDES_V5_COM_POST_DIV 0x03c +#define QSERDES_V5_COM_POST_DIV_MUX 0x040 +#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 +#define QSERDES_V5_COM_CLK_ENABLE1 0x048 +#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V5_COM_PLL_EN 0x054 +#define QSERDES_V5_COM_PLL_IVCO 0x058 +#define QSERDES_V5_COM_CMN_IETRIM 0x05c +#define QSERDES_V5_COM_CMN_IPTRIM 0x060 +#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 +#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 +#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 +#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V5_COM_PLL_CNTRL 0x08c +#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 +#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 +#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c +#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 +#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 +#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 +#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 +#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 +#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 +#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 +#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 +#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 +#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c +#define QSERDES_V5_COM_CMN_STATUS 0x140 +#define QSERDES_V5_COM_RESET_SM_STATUS 0x144 +#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 +#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c +#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 +#define QSERDES_V5_COM_CLK_SELECT 0x154 +#define QSERDES_V5_COM_HSCLK_SEL 0x158 +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 +#define QSERDES_V5_COM_PLL_ANALOG 0x164 +#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V5_COM_SW_RESET 0x170 +#define QSERDES_V5_COM_CORE_CLK_EN 0x174 +#define QSERDES_V5_COM_C_READY_STATUS 0x178 +#define QSERDES_V5_COM_CMN_CONFIG 0x17c +#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 +#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V5_COM_DEBUG_BUS0 0x188 +#define QSERDES_V5_COM_DEBUG_BUS1 0x18c +#define QSERDES_V5_COM_DEBUG_BUS2 0x190 +#define QSERDES_V5_COM_DEBUG_BUS3 0x194 +#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 +#define QSERDES_V5_COM_CMN_MISC1 0x19c +#define QSERDES_V5_COM_CMN_MODE 0x1a0 +#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 +#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V5_COM_RESERVED_1 0x1c0 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h new file mode 100644 index 00000000000..86d7d796d5d --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-ln-shrd-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ +#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ + +#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0 +#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0 +#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c +#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h new file mode 100644 index 00000000000..fe8f3e330d0 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h @@ -0,0 +1,231 @@ + +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ + +/* Only for QMP V5 PHY - TX registers */ +#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V5_TX_BIST_INVERT 0x004 +#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 +#define QSERDES_V5_TX_TX_DRV_LVL 0x014 +#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 +#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c +#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 +#define QSERDES_V5_TX_TX_BAND 0x024 +#define QSERDES_V5_TX_SLEW_CNTL 0x028 +#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c +#define QSERDES_V5_TX_LPB_EN 0x030 +#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V5_TX_PERL_LENGTH1 0x044 +#define QSERDES_V5_TX_PERL_LENGTH2 0x048 +#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c +#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 +#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V5_TX_TX_POL_INV 0x05c +#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 +#define QSERDES_V5_TX_BIST_PATTERN1 0x064 +#define QSERDES_V5_TX_BIST_PATTERN2 0x068 +#define QSERDES_V5_TX_BIST_PATTERN3 0x06c +#define QSERDES_V5_TX_BIST_PATTERN4 0x070 +#define QSERDES_V5_TX_BIST_PATTERN5 0x074 +#define QSERDES_V5_TX_BIST_PATTERN6 0x078 +#define QSERDES_V5_TX_BIST_PATTERN7 0x07c +#define QSERDES_V5_TX_BIST_PATTERN8 0x080 +#define QSERDES_V5_TX_LANE_MODE_1 0x084 +#define QSERDES_V5_TX_LANE_MODE_2 0x088 +#define QSERDES_V5_TX_LANE_MODE_3 0x08c +#define QSERDES_V5_TX_LANE_MODE_4 0x090 +#define QSERDES_V5_TX_LANE_MODE_5 0x094 +#define QSERDES_V5_TX_ATB_SEL1 0x098 +#define QSERDES_V5_TX_ATB_SEL2 0x09c +#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 +#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V5_TX_PRBS_SEED1 0x0a8 +#define QSERDES_V5_TX_PRBS_SEED2 0x0ac +#define QSERDES_V5_TX_PRBS_SEED3 0x0b0 +#define QSERDES_V5_TX_PRBS_SEED4 0x0b4 +#define QSERDES_V5_TX_RESET_GEN 0x0b8 +#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc +#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc +#define QSERDES_V5_TX_BIST_STATUS 0x0d0 +#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 +#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc +#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 +#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 +#define QSERDES_V5_TX_PRE_EMPH 0x0e8 +#define QSERDES_V5_TX_SW_RESET 0x0ec +#define QSERDES_V5_TX_DCC_OFFSET 0x0f0 +#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc +#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 +#define QSERDES_V5_TX_DEBUG_BUS0 0x104 +#define QSERDES_V5_TX_DEBUG_BUS1 0x108 +#define QSERDES_V5_TX_DEBUG_BUS2 0x10c +#define QSERDES_V5_TX_DEBUG_BUS3 0x110 +#define QSERDES_V5_TX_READ_EQCODE 0x114 +#define QSERDES_V5_TX_READ_OFFSETCODE 0x118 +#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c +#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 +#define QSERDES_V5_TX_VGA_READ_CODE 0x124 +#define QSERDES_V5_TX_VTH_READ_CODE 0x128 +#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c +#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 +#define QSERDES_V5_TX_IDAC_STATUS_I 0x134 +#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 +#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c +#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 +#define QSERDES_V5_TX_IDAC_STATUS_A 0x144 +#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 +#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c +#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 +#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 +#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 +#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c + +/* Only for QMP V5 PHY - RX registers */ +#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 +#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V5_RX_AUX_CONTROL 0x05c +#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c +#define QSERDES_V5_RX_AC_JTAG_INITN 0x070 +#define QSERDES_V5_RX_AC_JTAG_LVL 0x074 +#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c +#define QSERDES_V5_RX_RX_TERM_BW 0x080 +#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 +#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 +#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c +#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 +#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 +#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 +#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c +#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 +#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 +#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 +#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac +#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 +#define QSERDES_V5_RX_DFE_1 0x0b4 +#define QSERDES_V5_RX_DFE_2 0x0b8 +#define QSERDES_V5_RX_DFE_3 0x0bc +#define QSERDES_V5_RX_DFE_4 0x0c0 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 +#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V5_RX_GM_CAL 0x0dc +#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 +#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 +#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 +#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c +#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V5_RX_SIGDET_LVL 0x120 +#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V5_RX_RX_BAND 0x128 +#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c +#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 +#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 +#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 +#define QSERDES_V5_RX_SJ_AMP1 0x13c +#define QSERDES_V5_RX_SJ_AMP2 0x140 +#define QSERDES_V5_RX_SJ_PER1 0x144 +#define QSERDES_V5_RX_SJ_PER2 0x148 +#define QSERDES_V5_RX_PPM_OFFSET1 0x14c +#define QSERDES_V5_RX_PPM_OFFSET2 0x150 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 +#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V5_RX_PHPRE_CTRL 0x198 +#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c +#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V5_RX_DCC_CTRL2 0x1ac +#define QSERDES_V5_RX_VTH_CODE 0x1b0 +#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 +#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc +#define QSERDES_V5_RX_PI_CTRL1 0x1c0 +#define QSERDES_V5_RX_PI_CTRL2 0x1c4 +#define QSERDES_V5_RX_PI_QUAD 0x1c8 +#define QSERDES_V5_RX_IDATA1 0x1cc +#define QSERDES_V5_RX_IDATA2 0x1d0 +#define QSERDES_V5_RX_AUX_DATA1 0x1d4 +#define QSERDES_V5_RX_AUX_DATA2 0x1d8 +#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc +#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 +#define QSERDES_V5_RX_RX_SIGDET 0x1e4 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8 + +/* Only for QMP V5 UFS ? */ +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h new file mode 100644 index 00000000000..23ffcfae9ef --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ + +#define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 +#define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c +#define QSERDES_V6_TX_TX_DRV_LVL 0x14 +#define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c +#define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 +#define QSERDES_V6_TX_TX_BAND 0x24 +#define QSERDES_V6_TX_INTERFACE_SELECT 0x2c +#define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 +#define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c +#define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 +#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 +#define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 +#define QSERDES_V6_TX_TX_POL_INV 0x5c +#define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 +#define QSERDES_V6_TX_BIST_PATTERN7 0x7c +#define QSERDES_V6_TX_LANE_MODE_1 0x84 +#define QSERDES_V6_TX_LANE_MODE_2 0x88 +#define QSERDES_V6_TX_LANE_MODE_3 0x8c +#define QSERDES_V6_TX_LANE_MODE_4 0x90 +#define QSERDES_V6_TX_LANE_MODE_5 0x94 +#define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 +#define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 +#define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 +#define QSERDES_V6_TX_VMODE_CTRL1 0xc8 +#define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 + +#define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 +#define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 +#define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 +#define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c +#define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 +#define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 +#define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c +#define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 +#define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 +#define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 +#define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 +#define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc +#define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 +#define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 +#define QSERDES_V6_RX_GM_CAL 0xdc +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 +#define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 +#define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc +#define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V6_RX_SIDGET_ENABLES 0x118 +#define QSERDES_V6_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V6_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V6_RX_VTH_CODE 0x1b0 +#define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 +#define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h new file mode 100644 index 00000000000..7bac5d5c6c3 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v6_20.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ + +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 +#define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac +#define QSERDES_V6_20_TX_LANE_MODE_1 0x78 +#define QSERDES_V6_20_TX_LANE_MODE_2 0x7c +#define QSERDES_V6_20_TX_LANE_MODE_3 0x80 + +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 +#define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c +#define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18 +#define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 +#define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 +#define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c +#define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 +#define QSERDES_V6_20_RX_DFE_1 0xac +#define QSERDES_V6_20_RX_DFE_2 0xb0 +#define QSERDES_V6_20_RX_DFE_3 0xb4 +#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4 +#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0 +#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 +#define QSERDES_V6_20_RX_GM_CAL 0x10c +#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 +#define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148 +#define QSERDES_V6_20_RX_PHPRE_CTRL 0x188 +#define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 +#define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc +#define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4 +#define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8 +#define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc +#define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200 +#define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204 +#define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208 +#define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c +#define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210 +#define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214 +#define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218 +#define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c +#define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 +#define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 +#define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 +#define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c + +#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 5c90d60e7d1..449b9767778 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -33,8 +33,10 @@ #include "phy-qcom-qmp-pcs-ufs-v6.h" #include "phy-qcom-qmp-qserdes-com-v4.h" +#include "phy-qcom-qmp-qserdes-com-v5.h" #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v4.h" +#include "phy-qcom-qmp-qserdes-txrx-v5.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" /* QPHY_SW_RESET bit */ @@ -97,6 +99,13 @@ static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, @@ -458,6 +467,128 @@ static const struct qmp_ufs_init_tbl sm8650_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), }; +static const struct qmp_ufs_init_tbl sm8350_ufsphy_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_ufs_init_tbl sm8650_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), @@ -690,6 +821,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = { "ref", "ref_aux", }; +/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const sm8450_ufs_phy_clk_l[] = { + "qref", "ref", "ref_aux", +}; + /* list of regulators */ static const char * const qmp_ufs_vreg_l[] = { "vdda-phy", "vdda-pll", @@ -909,6 +1045,40 @@ static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = { .regs = ufsphy_v4_regs_layout, }; +static const struct qmp_ufs_cfg sa8775p_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .regs = ufsphy_v5_regs_layout, +}; + static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_ufs_init_tbl tbl[], int num, @@ -1295,6 +1465,7 @@ static struct phy_ops qmp_ufs_ops = { }; static const struct udevice_id qmp_ufs_ids[] = { + { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg }, diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index b1960c56b51..54cec37327c 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -219,7 +219,7 @@ int imx_pinctrl_probe(struct udevice *dev, if (info->flags & IMX8_USE_SCU) return 0; - addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size); + addr = ofnode_get_addr_size_index(node, 0, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; @@ -228,7 +228,7 @@ int imx_pinctrl_probe(struct udevice *dev, return -ENOMEM; priv->info = info; - info->mux_mask = ofnode_read_u32(node, "fsl,mux_mask", 0); + info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0); /* * Refer to linux documentation for details: * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 4f93a34281d..d3eb6998551 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -83,6 +83,13 @@ config PINCTRL_QCOM_SM8650 Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_X1E80100 + bool "Qualcomm X1E80100 GCC" + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC, + as well as the associated GPIO driver. + endmenu endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43d0dd29222..06d3c95f93a 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o obj-$(CONFIG_PINCTRL_QCOM_SM8650) += pinctrl-sm8650.o +obj-$(CONFIG_PINCTRL_QCOM_X1E80100) += pinctrl-x1e80100.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index c65dfe0435e..25b972a6d82 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -16,6 +16,7 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"qup1_se7", 1}, {"gpio", 0}, + {"pcie1_clk_req_n", 1}, }; #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index 58fc94e71ac..9146d6abd9a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -16,6 +16,8 @@ static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const struct pinctrl_function msm_pinctrl_functions[] = { {"qup2_se7", 1}, {"gpio", 0}, + {"pcie0_clk_req_n", 1}, + {"pcie1_clk_req_n", 1}, }; #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c new file mode 100644 index 00000000000..f39dc426d68 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm x1e80100 pinctrl + * + * (C) Copyright 2024 Linaro Ltd. + * + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup2_se5", 1}, + {"pcie3_clk", 1}, + {"pcie4_clk", 1}, + {"pcie5_clk", 1}, + {"pcie6a_clk", 1}, + {"pcie6b_clk", 1}, + {"gpio", 0}, +}; + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, ctl) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = ctl + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data msm_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", 0xf9000), + [1] = SDC_QDSD_PINGROUP("sdc2_clk", 0xf2000, 14, 6), + [2] = SDC_QDSD_PINGROUP("sdc2_cmd", 0xf2000, 11, 3), + [3] = SDC_QDSD_PINGROUP("sdc2_data", 0xf2000, 9, 0), +}; + +static const char *x1e80100_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *x1e80100_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= 238 && selector <= 241) + snprintf(pin_name, MAX_PIN_NAME_LEN, + msm_special_pins_data[selector - 238].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data x1e80100_data = { + .pin_data = { + .pin_count = 242, + .special_pins_start = 238, + .special_pins_data = msm_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = x1e80100_get_function_name, + .get_function_mux = x1e80100_get_function_mux, + .get_pin_name = x1e80100_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,x1e80100-tlmm", .data = (ulong)&x1e80100_data }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_x1e80100) = { + .name = "pinctrl_x1e80100", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; + diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 57e88604aa2..560f7275454 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -11,35 +11,46 @@ config PINCTRL_PFC both the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_PFC_FULL + bool "Renesas pin control drivers (full size)" + depends on PINCTRL_PFC + help + By default the pin multiplexing tables used by U-Boot are reduced + to keep the size of the bootloader low. Enable this option to use + full pin multiplexing tables the same way they are included in the + Linux kernel. This includes pin multiplexing options for Audio, CAN, + CANFD, DU, INTC, INTC-EX, MSIOF, PWM, SSI, for which there is no + U-Boot driver. + config PINCTRL_PFC_R8A7790 - bool "Renesas RCar Gen2 R8A7790 pin control driver" + bool "Renesas R-Car Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7790 SoCs. config PINCTRL_PFC_R8A7791 - bool "Renesas RCar Gen2 R8A7791 pin control driver" + bool "Renesas R-Car Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7791 SoCs. config PINCTRL_PFC_R8A7792 - bool "Renesas RCar Gen2 R8A7792 pin control driver" + bool "Renesas R-Car Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7792 SoCs. config PINCTRL_PFC_R8A7793 - bool "Renesas RCar Gen2 R8A7793 pin control driver" + bool "Renesas R-Car Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7793 SoCs. config PINCTRL_PFC_R8A7794 - bool "Renesas RCar Gen2 R8A7794 pin control driver" + bool "Renesas R-Car Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7794 SoCs. config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" @@ -66,76 +77,76 @@ config PINCTRL_PFC_R8A774E1 Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. config PINCTRL_PFC_R8A77951 - bool "Renesas RCar Gen3 R8A7795 pin control driver" + bool "Renesas R-Car Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A7795 SoCs. config PINCTRL_PFC_R8A77960 - bool "Renesas RCar Gen3 R8A77960 pin control driver" + bool "Renesas R-Car Gen3 R8A77960 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77960 SoCs. config PINCTRL_PFC_R8A77961 - bool "Renesas RCar Gen3 R8A77961 pin control driver" + bool "Renesas R-Car Gen3 R8A77961 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77961 SoCs. config PINCTRL_PFC_R8A77965 - bool "Renesas RCar Gen3 R8A77965 pin control driver" + bool "Renesas R-Car Gen3 R8A77965 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77965 SoCs. config PINCTRL_PFC_R8A77970 - bool "Renesas RCar Gen3 R8A77970 pin control driver" + bool "Renesas R-Car Gen3 R8A77970 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77970 SoCs. config PINCTRL_PFC_R8A77980 - bool "Renesas RCar Gen3 R8A77980 pin control driver" + bool "Renesas R-Car Gen3 R8A77980 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77980 SoCs. config PINCTRL_PFC_R8A77990 - bool "Renesas RCar Gen3 R8A77990 pin control driver" + bool "Renesas R-Car Gen3 R8A77990 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77990 SoCs. config PINCTRL_PFC_R8A77995 - bool "Renesas RCar Gen3 R8A77995 pin control driver" + bool "Renesas R-Car Gen3 R8A77995 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77995 SoCs. config PINCTRL_PFC_R8A779A0 - bool "Renesas RCar Gen3 R8A779A0 pin control driver" + bool "Renesas R-Car Gen3 R8A779A0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A779A0 SoCs. config PINCTRL_PFC_R8A779F0 - bool "Renesas RCar Gen4 R8A779F0 pin control driver" + bool "Renesas R-Car Gen4 R8A779F0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779F0 SoCs. config PINCTRL_PFC_R8A779G0 - bool "Renesas RCar Gen4 R8A779G0 pin control driver" + bool "Renesas R-Car Gen4 R8A779G0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779G0 SoCs. config PINCTRL_PFC_R8A779H0 - bool "Renesas RCar Gen4 R8A779H0 pin control driver" + bool "Renesas R-Car Gen4 R8A779H0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779H0 SoCs. config PINCTRL_RZA1 bool "Renesas RZ/A1 R7S72100 pin control driver" diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index acd6b01f497..4d6ce06cf16 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -1745,6 +1745,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -1795,6 +1796,8 @@ static const unsigned int audio_clkout_d_pins[] = { static const unsigned int audio_clkout_d_mux[] = { AUDIO_CLKOUT_D_MARK, }; +#endif + /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { RCAR_GP_PIN(3, 11), @@ -1870,6 +1873,8 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN0 ----------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* CAN0 RX */ @@ -2048,6 +2053,8 @@ static const unsigned int du2_clk_in_pins[] = { static const unsigned int du2_clk_in_mux[] = { DU_DOTCLKIN2_MARK, }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2363,6 +2370,8 @@ static const unsigned int iic3_pins[] = { static const unsigned int iic3_mux[] = { IIC3_SCL_MARK, IIC3_SDA_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2392,6 +2401,7 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7790 /* - MLB+ ------------------------------------------------------------------- */ @@ -2441,6 +2451,8 @@ static const unsigned int mmc1_ctrl_pins[] = { static const unsigned int mmc1_ctrl_mux[] = { MMC1_CLK_MARK, MMC1_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2769,6 +2781,8 @@ static const unsigned int pwm6_pins[] = { static const unsigned int pwm6_mux[] = { PWM6_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3394,6 +3408,8 @@ static const unsigned int sdhi3_wp_pins[] = { static const unsigned int sdhi3_wp_mux[] = { SD3_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA0 */ @@ -3577,6 +3593,8 @@ static const unsigned int ssi9_ctrl_pins[] = { static const unsigned int ssi9_ctrl_mux[] = { SSI_SCK9_MARK, SSI_WS9_MARK, }; +#endif + /* - TPU0 ------------------------------------------------------------------- */ static const unsigned int tpu0_to0_pins[] = { /* TO */ @@ -3630,6 +3648,8 @@ static const unsigned int usb2_pins[] = { static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -4024,6 +4044,7 @@ static const unsigned int vin3_clk_pins[] = { static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[311]; @@ -4032,6 +4053,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clk_c), @@ -4039,12 +4061,14 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clkout_c), SH_PFC_PIN_GROUP(audio_clkout_d), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -4063,6 +4087,7 @@ static const struct { SH_PFC_PIN_GROUP(du0_clk_in), SH_PFC_PIN_GROUP(du1_clk_in), SH_PFC_PIN_GROUP(du2_clk_in), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -4106,10 +4131,12 @@ static const struct { SH_PFC_PIN_GROUP(iic2_d), SH_PFC_PIN_GROUP(iic2_e), SH_PFC_PIN_GROUP(iic3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif BUS_DATA_PIN_GROUP(mmc0_data, 1), BUS_DATA_PIN_GROUP(mmc0_data, 4), BUS_DATA_PIN_GROUP(mmc0_data, 8), @@ -4118,6 +4145,7 @@ static const struct { BUS_DATA_PIN_GROUP(mmc1_data, 4), BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4165,6 +4193,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4257,6 +4286,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0129_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4283,6 +4313,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi8_c_data), SH_PFC_PIN_GROUP(ssi9_data), SH_PFC_PIN_GROUP(ssi9_ctrl), +#endif SH_PFC_PIN_GROUP(tpu0_to0), SH_PFC_PIN_GROUP(tpu0_to1), SH_PFC_PIN_GROUP(tpu0_to2), @@ -4292,6 +4323,7 @@ static const struct { SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1), SH_PFC_PIN_GROUP(usb2), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4343,6 +4375,7 @@ static const struct { SH_PFC_PIN_GROUP(vin3_field), SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { @@ -4351,6 +4384,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", @@ -4360,6 +4394,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout_c", "audio_clkout_d", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4370,6 +4405,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4408,6 +4444,7 @@ static const char * const du1_groups[] = { static const char * const du2_groups[] = { "du2_clk_in", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4485,12 +4522,14 @@ static const char * const iic3_groups[] = { "iic3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", "intc_irq2", "intc_irq3", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7790 static const char * const mlb_groups[] = { @@ -4512,6 +4551,7 @@ static const char * const mmc1_groups[] = { "mmc1_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4591,6 +4631,7 @@ static const char * const pwm5_groups[] = { static const char * const pwm6_groups[] = { "pwm6", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -4729,6 +4770,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0129_ctrl", @@ -4757,6 +4799,7 @@ static const char * const ssi_groups[] = { "ssi9_data", "ssi9_ctrl", }; +#endif static const char * const tpu0_groups[] = { "tpu0_to0", @@ -4779,6 +4822,7 @@ static const char * const usb2_groups[] = { "usb2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -4841,6 +4885,7 @@ static const char * const vin3_groups[] = { "vin3_clkenb", "vin3_clk", }; +#endif static const struct { struct sh_pfc_function common[58]; @@ -4849,8 +4894,11 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), @@ -4858,6 +4906,7 @@ static const struct { SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4869,9 +4918,12 @@ static const struct { SH_PFC_FUNCTION(iic1), SH_PFC_FUNCTION(iic2), SH_PFC_FUNCTION(iic3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -4883,6 +4935,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -4898,15 +4951,19 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu0), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), SH_PFC_FUNCTION(vin3), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A7790 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index fa94a51e5e7..c6d761bb378 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -1802,6 +1802,7 @@ static const unsigned int adi_chsel2_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK */ @@ -1847,6 +1848,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1924,6 +1926,7 @@ static const unsigned int avb_gmii_mux[] = { AVB_COL_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { @@ -2160,6 +2163,8 @@ static const unsigned int du1_clk_in_c_pins[] = { static const unsigned int du1_clk_in_c_mux[] = { DU1_DOTCLKIN_C_MARK, }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2553,6 +2558,8 @@ static const unsigned int i2c8_c_pins[] = { static const unsigned int i2c8_c_mux[] = { IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ */ @@ -2582,6 +2589,7 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) /* - MLB+ ------------------------------------------------------------------- */ @@ -2623,6 +2631,8 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3192,6 +3202,8 @@ static const unsigned int pwm6_pins[] = { static const unsigned int pwm6_mux[] = { PWM6_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3872,6 +3884,7 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -4124,6 +4137,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_pins[] = { @@ -4169,6 +4183,8 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -4424,6 +4440,7 @@ static const unsigned int vin2_clk_pins[] = { static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[346]; @@ -4432,17 +4449,20 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clk_b_b), SH_PFC_PIN_GROUP(audio_clk_c), SH_PFC_PIN_GROUP(audio_clkout), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -4469,6 +4489,7 @@ static const struct { SH_PFC_PIN_GROUP(du1_clk_in), SH_PFC_PIN_GROUP(du1_clk_in_b), SH_PFC_PIN_GROUP(du1_clk_in_c), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -4524,15 +4545,18 @@ static const struct { SH_PFC_PIN_GROUP(i2c8), SH_PFC_PIN_GROUP(i2c8_b), SH_PFC_PIN_GROUP(i2c8_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), BUS_DATA_PIN_GROUP(mmc_data, 8, _b), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4614,6 +4638,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4712,6 +4737,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0_data_b), SH_PFC_PIN_GROUP(ssi0129_ctrl), @@ -4740,12 +4766,14 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tpu_to0), SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4778,6 +4806,7 @@ static const struct { SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { @@ -4807,6 +4836,7 @@ static const char * const adi_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", @@ -4814,6 +4844,7 @@ static const char * const audio_clk_groups[] = { "audio_clk_c", "audio_clkout", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4824,6 +4855,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4887,6 +4919,7 @@ static const char * const du1_groups[] = { "du1_clk_in_b", "du1_clk_in_c", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4976,12 +5009,14 @@ static const char * const i2c8_groups[] = { "i2c8_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", "intc_irq2", "intc_irq3", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) static const char * const mlb_groups[] = { @@ -4997,6 +5032,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5107,6 +5143,7 @@ static const char * const pwm5_groups[] = { static const char * const pwm6_groups[] = { "pwm6", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -5254,6 +5291,7 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0_data_b", @@ -5284,6 +5322,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl", "ssi9_ctrl_b", }; +#endif static const char * const tpu_groups[] = { "tpu_to0", @@ -5299,6 +5338,7 @@ static const char * const usb1_groups[] = { "usb1", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -5339,6 +5379,7 @@ static const char * const vin2_groups[] = { "vin2_clkenb", "vin2_clk", }; +#endif static const struct { struct sh_pfc_function common[58]; @@ -5347,14 +5388,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -5366,8 +5411,11 @@ static const struct { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c7), SH_PFC_FUNCTION(i2c8), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -5378,6 +5426,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -5398,13 +5447,17 @@ static const struct { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 7c1e6d40749..d2ff1d9d1a6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -831,6 +831,8 @@ static const unsigned int avb_avtp_match_pins[] = { static const unsigned int avb_avtp_match_mux[] = { AVB_AVTP_MATCH_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -996,6 +998,8 @@ static const unsigned int intc_irq3_pins[] = { static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; +#endif + /* - LBSC ------------------------------------------------------------------- */ static const unsigned int lbsc_cs0_pins[] = { /* CS0# */ @@ -1053,6 +1057,8 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1111,6 +1117,8 @@ static const unsigned int msiof1_tx_pins[] = { static const unsigned int msiof1_tx_mux[] = { MSIOF1_TXD_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -1231,6 +1239,8 @@ static const unsigned int sdhi0_wp_pins[] = { static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -1645,6 +1655,7 @@ static const unsigned int vin5_clk_pins[] = { static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -1654,6 +1665,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), SH_PFC_PIN_GROUP(avb_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), @@ -1672,6 +1684,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), +#endif SH_PFC_PIN_GROUP(lbsc_cs0), SH_PFC_PIN_GROUP(lbsc_cs1), SH_PFC_PIN_GROUP(lbsc_ex_cs0), @@ -1680,6 +1693,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_rx), @@ -1688,6 +1702,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof1_sync), SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -1706,6 +1721,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -1762,6 +1778,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }; static const char * const avb_groups[] = { @@ -1774,6 +1791,7 @@ static const char * const avb_groups[] = { "avb_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can_clk", @@ -1807,6 +1825,7 @@ static const char * const intc_groups[] = { "intc_irq2", "intc_irq3", }; +#endif static const char * const lbsc_groups[] = { "lbsc_cs0", @@ -1819,6 +1838,7 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1832,6 +1852,7 @@ static const char * const msiof1_groups[] = { "msiof1_rx", "msiof1_tx", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -1869,6 +1890,7 @@ static const char * const sdhi0_groups[] = { "sdhi0_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -1942,29 +1964,36 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(lbsc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), SH_PFC_FUNCTION(vin2), SH_PFC_FUNCTION(vin3), SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 2f550218182..a1fa1776bae 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -1500,6 +1500,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clka_pins[] = { /* CLKA */ @@ -1592,6 +1593,8 @@ static const unsigned int audio_clkout_c_pins[] = { static const unsigned int audio_clkout_c_mux[] = { AUDIO_CLKOUT_C_MARK, }; +#endif + /* - AVB -------------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { RCAR_GP_PIN(3, 26), @@ -1668,6 +1671,7 @@ static const unsigned int avb_gmii_mux[] = { AVB_COL_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN -------------------------------------------------------------------- */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -1950,6 +1954,8 @@ static const unsigned int du1_disp_pins[] = { static const unsigned int du1_disp_mux[] = { DU1_DISP_MARK }; +#endif + /* - ETH -------------------------------------------------------------------- */ static const unsigned int eth_link_pins[] = { /* LINK */ @@ -2316,6 +2322,8 @@ static const unsigned int i2c5_d_pins[] = { static const unsigned int i2c5_d_mux[] = { I2C5_SCL_D_MARK, I2C5_SDA_D_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { /* IRQ0 */ @@ -2387,6 +2395,8 @@ static const unsigned int intc_irq9_pins[] = { static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; +#endif + /* - MMCIF ------------------------------------------------------------------ */ static const unsigned int mmc_data_pins[] = { /* D[0:7] */ @@ -2406,6 +2416,8 @@ static const unsigned int mmc_ctrl_pins[] = { static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2722,6 +2734,8 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif + /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -3299,6 +3313,8 @@ static const unsigned int sdhi2_wp_pins[] = { static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA0 */ @@ -3538,6 +3554,8 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif + /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_pins[] = { RCAR_GP_PIN(3, 31), @@ -3629,6 +3647,8 @@ static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; + +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { /* B */ @@ -3761,8 +3781,10 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clka), SH_PFC_PIN_GROUP(audio_clka_b), SH_PFC_PIN_GROUP(audio_clka_c), @@ -3776,12 +3798,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clkout), SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clkout_c), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can0_data_c), @@ -3812,6 +3836,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du1_oddf), SH_PFC_PIN_GROUP(du1_cde), SH_PFC_PIN_GROUP(du1_disp), +#endif SH_PFC_PIN_GROUP(eth_link), SH_PFC_PIN_GROUP(eth_magic), SH_PFC_PIN_GROUP(eth_mdio), @@ -3862,6 +3887,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c5_b), SH_PFC_PIN_GROUP(i2c5_c), SH_PFC_PIN_GROUP(i2c5_d), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_irq0), SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), @@ -3872,10 +3898,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -3923,6 +3951,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm5_c), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi_ctrl), BUS_DATA_PIN_GROUP(qspi_data, 2), BUS_DATA_PIN_GROUP(qspi_data, 4), @@ -4006,6 +4035,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi0129_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4040,6 +4070,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_ctrl), SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tpu_to0), SH_PFC_PIN_GROUP(tpu_to0_b), SH_PFC_PIN_GROUP(tpu_to0_c), @@ -4054,6 +4085,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 24), BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), @@ -4072,8 +4104,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clka", "audio_clka_b", @@ -4089,6 +4123,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout_b", "audio_clkout_c", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4099,6 +4134,7 @@ static const char * const avb_groups[] = { "avb_gmii", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", "can0_data_b", @@ -4163,6 +4199,7 @@ static const char * const du1_groups[] = { "du1_cde", "du1_disp", }; +#endif static const char * const eth_groups[] = { "eth_link", @@ -4244,6 +4281,7 @@ static const char * const i2c5_groups[] = { "i2c5_d", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_groups[] = { "intc_irq0", "intc_irq1", @@ -4256,6 +4294,7 @@ static const char * const intc_groups[] = { "intc_irq8", "intc_irq9", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -4264,6 +4303,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4340,6 +4380,7 @@ static const char * const pwm6_groups[] = { "pwm6", "pwm6_b", }; +#endif static const char * const qspi_groups[] = { "qspi_ctrl", @@ -4484,6 +4525,7 @@ static const char * const sdhi2_groups[] = { "sdhi2_wp", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi0129_ctrl", @@ -4520,6 +4562,7 @@ static const char * const ssi_groups[] = { "ssi9_data_b", "ssi9_ctrl_b", }; +#endif static const char * const tpu_groups[] = { "tpu_to0", @@ -4544,6 +4587,7 @@ static const char * const usb1_groups[] = { "usb1", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data24", "vin0_data20", @@ -4567,15 +4611,20 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), +#endif SH_PFC_FUNCTION(eth), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4586,8 +4635,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -4598,6 +4650,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), @@ -4618,12 +4671,16 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 1cfdc335041..8ddcbfbbd64 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -1563,6 +1563,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1683,6 +1684,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1770,6 +1772,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1824,6 +1827,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - DRIF0 --------------------------------------------------------------- */ @@ -2042,6 +2046,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2122,6 +2127,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2409,6 +2415,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2452,6 +2459,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - MLB+ ------------------------------------------------------------------- */ @@ -2463,6 +2471,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3259,6 +3268,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3687,6 +3697,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3863,6 +3874,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3966,6 +3978,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4145,6 +4158,7 @@ static const unsigned int vin5_clk_mux[] = { /* CLK */ VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[328]; @@ -4153,6 +4167,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4170,6 +4185,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4181,6 +4197,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4196,6 +4213,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4234,6 +4252,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4352,6 +4371,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4415,6 +4435,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4440,6 +4461,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4453,6 +4475,7 @@ static const struct { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4481,6 +4504,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { @@ -4519,6 +4543,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4538,6 +4563,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4553,6 +4579,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4574,6 +4601,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const drif0_groups[] = { @@ -4619,6 +4647,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4629,6 +4658,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4701,6 +4731,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4709,6 +4740,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const mlb_3pin_groups[] = { @@ -4716,6 +4748,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4860,6 +4893,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4966,6 +5000,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4993,6 +5028,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5028,6 +5064,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5061,6 +5098,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[55]; @@ -5069,14 +5107,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5088,6 +5130,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5100,6 +5143,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), @@ -5114,7 +5158,9 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), @@ -5122,8 +5168,10 @@ static const struct { SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(usb2_ch3), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a289397fb8f..7bc9fb709ea 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1568,6 +1568,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1689,6 +1690,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1776,6 +1778,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1830,6 +1833,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ @@ -2048,6 +2052,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2128,6 +2133,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2415,6 +2421,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2458,6 +2465,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - MLB+ ------------------------------------------------------------------- */ @@ -2469,6 +2477,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3266,6 +3275,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3679,6 +3689,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3855,6 +3866,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3942,6 +3954,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4121,6 +4134,7 @@ static const unsigned int vin5_clk_mux[] = { /* CLK */ VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[324]; @@ -4129,6 +4143,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4146,6 +4161,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4157,6 +4173,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4172,6 +4189,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4210,6 +4228,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4328,6 +4347,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4389,6 +4409,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4414,6 +4435,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4425,6 +4447,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4453,6 +4476,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { @@ -4491,6 +4515,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4510,6 +4535,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4525,6 +4551,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4546,6 +4573,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { @@ -4591,6 +4619,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4601,6 +4630,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4673,6 +4703,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4681,6 +4712,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const mlb_3pin_groups[] = { @@ -4688,6 +4720,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4832,6 +4865,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4933,6 +4967,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4960,6 +4995,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -4987,6 +5023,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5020,6 +5057,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[52]; @@ -5028,14 +5066,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5047,6 +5089,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5059,6 +5102,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), @@ -5072,14 +5116,18 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 2852ae64ec0..97fde005de6 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -1572,6 +1572,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_a_pins[] = { /* CLK A */ @@ -1693,6 +1694,7 @@ static const unsigned int audio_clkout3_b_pins[] = { static const unsigned int audio_clkout3_b_mux[] = { AUDIO_CLKOUT3_B_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1780,6 +1782,7 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1845,6 +1848,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - DRIF0 --------------------------------------------------------------- */ @@ -2122,6 +2126,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -2217,6 +2222,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -2566,6 +2572,7 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2609,6 +2616,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 /* - MLB+ ------------------------------------------------------------------- */ @@ -2620,6 +2628,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3416,6 +3425,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3884,6 +3894,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -4060,6 +4071,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -4158,6 +4170,7 @@ static const unsigned int usb30_mux[] = { USB30_PWEN_MARK, USB30_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), @@ -4355,6 +4368,7 @@ static const unsigned int vin5_clk_pins[] = { static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[326]; @@ -4363,6 +4377,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), SH_PFC_PIN_GROUP(audio_clk_a_c), @@ -4380,6 +4395,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -4391,6 +4407,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), @@ -4406,6 +4423,7 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4444,6 +4462,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -4562,6 +4581,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), BUS_DATA_PIN_GROUP(qspi0_data, 4), @@ -4625,6 +4645,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a), @@ -4650,6 +4671,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4661,6 +4683,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4689,6 +4712,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { @@ -4727,6 +4751,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a_a", "audio_clk_a_b", @@ -4746,6 +4771,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_a", "audio_clkout3_b", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4761,6 +4787,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -4782,6 +4809,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const drif0_groups[] = { @@ -4827,6 +4855,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4837,6 +4866,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -4909,6 +4939,7 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4917,6 +4948,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77965 static const char * const mlb_3pin_groups[] = { @@ -4924,6 +4956,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5068,6 +5101,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -5173,6 +5207,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -5200,6 +5235,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -5227,6 +5263,7 @@ static const char * const usb30_groups[] = { "usb30", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -5260,6 +5297,7 @@ static const char * const vin5_groups[] = { "vin5_clkenb", "vin5_clk", }; +#endif static const struct { struct sh_pfc_function common[53]; @@ -5268,14 +5306,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5287,6 +5329,7 @@ static const struct { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -5299,6 +5342,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(sata0), @@ -5313,14 +5357,18 @@ static const struct { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77965 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 00ebbbc7120..3a0a310c5fe 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -817,6 +817,7 @@ static const unsigned int avb0_avtp_match_mux[] = { AVB0_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD Clock ------------------------------------------------------------ */ static const unsigned int canfd_clk_a_pins[] = { /* CANFD_CLK */ @@ -911,6 +912,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1056,6 +1058,7 @@ static const unsigned int i2c4_mux[] = { SDA4_MARK, SCL4_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -1099,6 +1102,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1122,6 +1126,7 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1367,6 +1372,7 @@ static const unsigned int pwm4_b_pins[] = { static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1583,6 +1589,7 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), @@ -1674,6 +1681,7 @@ static const unsigned int vin1_clk_mux[] = { /* CLK */ VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_link), @@ -1685,6 +1693,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_avtp_pps), SH_PFC_PIN_GROUP(avb0_avtp_capture), SH_PFC_PIN_GROUP(avb0_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd_clk_a), SH_PFC_PIN_GROUP(canfd_clk_b), SH_PFC_PIN_GROUP(canfd0_data_a), @@ -1696,6 +1705,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -1714,16 +1724,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(i2c4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1758,6 +1771,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -1790,6 +1804,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 8), BUS_DATA_PIN_GROUP(vin0_data, 10), BUS_DATA_PIN_GROUP(vin0_data, 12), @@ -1804,6 +1819,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; static const char * const avb0_groups[] = { @@ -1818,6 +1834,7 @@ static const char * const avb0_groups[] = { "avb0_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd_clk_groups[] = { "canfd_clk_a", "canfd_clk_b", @@ -1840,6 +1857,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -1886,6 +1904,7 @@ static const char * const i2c4_groups[] = { "i2c4", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -1894,6 +1913,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -1902,6 +1922,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1962,6 +1983,7 @@ static const char * const pwm4_groups[] = { "pwm4_a", "pwm4_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2022,6 +2044,7 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data8", "vin0_data10", @@ -2041,13 +2064,16 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -2057,8 +2083,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2068,6 +2097,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2077,8 +2107,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(tmu), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index e3fc4045741..59f4bdde202 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -929,6 +929,7 @@ static const unsigned int avb_avtp_match_mux[] = { AVB_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_a_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1046,6 +1047,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - GETHER ----------------------------------------------------------------- */ static const unsigned int gether_link_a_pins[] = { @@ -1319,6 +1321,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -1362,6 +1365,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1406,6 +1410,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -1661,6 +1666,7 @@ static const unsigned int pwm4_b_pins[] = { static const unsigned int pwm4_b_mux[] = { PWM4_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1907,6 +1913,7 @@ static const unsigned int tpu_to3_mux[] = { TPU0TO3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN0 ------------------------------------------------------------------- */ static const unsigned int vin0_data_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), @@ -2032,6 +2039,7 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), @@ -2043,6 +2051,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_capture), SH_PFC_PIN_GROUP(avb_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data_a), SH_PFC_PIN_GROUP(canfd0_data_b), SH_PFC_PIN_GROUP(canfd1_data), @@ -2055,6 +2064,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(gether_link_a), SH_PFC_PIN_GROUP(gether_phy_int_a), SH_PFC_PIN_GROUP(gether_mdio_a), @@ -2087,12 +2097,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3), SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -2100,6 +2112,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2134,6 +2147,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -2170,6 +2184,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin0_data, 8), BUS_DATA_PIN_GROUP(vin0_data, 10), BUS_DATA_PIN_GROUP(vin0_data, 12), @@ -2188,6 +2203,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), +#endif }; static const char * const avb_groups[] = { @@ -2202,6 +2218,7 @@ static const char * const avb_groups[] = { "avb_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data_a", "canfd0_data_b", @@ -2225,6 +2242,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const gether_groups[] = { "gether_link_a", @@ -2291,6 +2309,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -2299,6 +2318,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2310,6 +2330,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2370,6 +2391,7 @@ static const char * const pwm4_groups[] = { "pwm4_a", "pwm4_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2437,6 +2459,7 @@ static const char * const tpu_groups[] = { "tpu_to3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin0_groups[] = { "vin0_data8", "vin0_data10", @@ -2460,13 +2483,16 @@ static const char * const vin1_groups[] = { "vin1_clkenb", "vin1_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd_clk), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(gether), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -2478,8 +2504,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2489,6 +2518,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2499,8 +2529,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tpu), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin0), SH_PFC_FUNCTION(vin1), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index e3a9c5e053d..75b7429bc0d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1314,6 +1314,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -1476,6 +1477,7 @@ static const unsigned int audio_clkout3_c_pins[] = { static const unsigned int audio_clkout3_c_mux[] = { AUDIO_CLKOUT3_C_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { @@ -1549,6 +1551,7 @@ static const unsigned int avb_avtp_capture_mux[] = { AVB_AVTP_CAPTURE_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_pins[] = { /* TX, RX */ @@ -1596,6 +1599,7 @@ static const unsigned int canfd1_data_pins[] = { static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - DRIF0 --------------------------------------------------------------- */ @@ -1792,6 +1796,7 @@ static const unsigned int drif3_data1_b_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -1879,6 +1884,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - HSCIF0 --------------------------------------------------*/ static const unsigned int hscif0_data_a_pins[] = { @@ -2300,6 +2306,7 @@ static const unsigned int i2c7_b_mux[] = { SCL7_B_MARK, SDA7_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2343,6 +2350,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - MLB+ ------------------------------------------------------------------- */ @@ -2354,6 +2362,7 @@ static const unsigned int mlb_3pin_mux[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2823,6 +2832,7 @@ static const unsigned int pwm6_b_pins[] = { static const unsigned int pwm6_b_mux[] = { PWM6_B_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -3293,6 +3303,7 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI -------------------------------------------------------------------- */ static const unsigned int ssi0_data_pins[] = { /* SDATA */ @@ -3482,6 +3493,7 @@ static const unsigned int ssi9_ctrl_b_pins[] = { static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +#endif /* - TMU -------------------------------------------------------------------- */ static const unsigned int tmu_tclk1_a_pins[] = { @@ -3567,6 +3579,7 @@ static const unsigned int usb30_id_mux[] = { USB3HS0_ID_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), @@ -3786,6 +3799,7 @@ static const unsigned int vin5_clk_b_pins[] = { static const unsigned int vin5_clk_b_mux[] = { VI5_CLK_B_MARK, }; +#endif static const struct { struct sh_pfc_pin_group common[261]; @@ -3794,6 +3808,7 @@ static const struct { #endif } pinmux_groups = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b_a), SH_PFC_PIN_GROUP(audio_clk_b_b), @@ -3812,6 +3827,7 @@ static const struct { SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(audio_clkout3_c), +#endif SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -3819,6 +3835,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match), SH_PFC_PIN_GROUP(avb_avtp_capture), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), @@ -3833,6 +3850,7 @@ static const struct { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(hscif0_data_a), SH_PFC_PIN_GROUP(hscif0_clk_a), SH_PFC_PIN_GROUP(hscif0_ctrl_a), @@ -3879,6 +3897,7 @@ static const struct { SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c7_a), SH_PFC_PIN_GROUP(i2c7_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), @@ -3936,6 +3955,7 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -3995,6 +4015,7 @@ static const struct { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(ssi1_data), @@ -4016,6 +4037,7 @@ static const struct { SH_PFC_PIN_GROUP(ssi9_data), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), +#endif SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), @@ -4025,6 +4047,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8, _a), BUS_DATA_PIN_GROUP(vin4_data, 10, _a), BUS_DATA_PIN_GROUP(vin4_data, 12, _a), @@ -4055,6 +4078,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb_a), SH_PFC_PIN_GROUP(vin5_clk_a), SH_PFC_PIN_GROUP(vin5_clk_b), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { @@ -4084,6 +4108,7 @@ static const struct { #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b_a", @@ -4104,6 +4129,7 @@ static const char * const audio_clk_groups[] = { "audio_clkout3_b", "audio_clkout3_c", }; +#endif static const char * const avb_groups[] = { "avb_link", @@ -4115,6 +4141,7 @@ static const char * const avb_groups[] = { "avb_avtp_capture", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data", }; @@ -4134,6 +4161,7 @@ static const char * const canfd0_groups[] = { static const char * const canfd1_groups[] = { "canfd1_data", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const drif0_groups[] = { @@ -4170,6 +4198,7 @@ static const char * const drif3_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4181,6 +4210,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data_a", @@ -4261,6 +4291,7 @@ static const char * const i2c7_groups[] = { "i2c7_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -4269,6 +4300,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const mlb_3pin_groups[] = { @@ -4276,6 +4308,7 @@ static const char * const mlb_3pin_groups[] = { }; #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4359,6 +4392,7 @@ static const char * const pwm6_groups[] = { "pwm6_a", "pwm6_b", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -4458,6 +4492,7 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi0_data", "ssi01239_ctrl", @@ -4481,6 +4516,7 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_a", "ssi9_ctrl_b", }; +#endif static const char * const tmu_groups[] = { "tmu_tclk1_a", @@ -4500,6 +4536,7 @@ static const char * const usb30_groups[] = { "usb30_id", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8_a", "vin4_data10_a", @@ -4535,6 +4572,7 @@ static const char * const vin5_groups[] = { "vin5_clk_a", "vin5_clk_b", }; +#endif static const struct { struct sh_pfc_function common[50]; @@ -4543,14 +4581,18 @@ static const struct { #endif } pinmux_functions = { .common = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -4562,6 +4604,7 @@ static const struct { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(i2c7), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -4574,6 +4617,7 @@ static const struct { SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm6), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -4587,12 +4631,16 @@ static const struct { SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb30), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), +#endif }, #ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index d3e2d842fa5..6fe2d743418 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -955,6 +955,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ------------------------------------------------------------- */ static const unsigned int audio_clk_a_pins[] = { /* CLK A */ @@ -984,6 +985,7 @@ static const unsigned int audio_clkout1_pins[] = { static const unsigned int audio_clkout1_mux[] = { AUDIO_CLKOUT1_MARK, }; +#endif /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb0_link_pins[] = { @@ -1078,6 +1080,7 @@ static const unsigned int avb0_avtp_capture_b_mux[] = { AVB0_AVTP_CAPTURE_B_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CAN ------------------------------------------------------------------ */ static const unsigned int can0_data_a_pins[] = { /* TX, RX */ @@ -1213,6 +1216,7 @@ static const unsigned int du_disp_pins[] = { static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +#endif /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { @@ -1288,6 +1292,7 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -1682,6 +1687,7 @@ static const unsigned int pwm3_c_pins[] = { static const unsigned int pwm3_c_mux[] = { PWM3_C_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -1929,6 +1935,7 @@ static const unsigned int scif_clk_mux[] = { SCIF_CLK_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ---------------------------------------------------------------*/ static const unsigned int ssi3_data_pins[] = { /* SDATA */ @@ -1972,6 +1979,7 @@ static const unsigned int ssi4_data_b_pins[] = { static const unsigned int ssi4_data_b_mux[] = { SSI_SDATA4_B_MARK, }; +#endif /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { @@ -1982,6 +1990,7 @@ static const unsigned int usb0_mux[] = { USB0_PWEN_MARK, USB0_OVC_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - VIN4 ------------------------------------------------------------------- */ static const unsigned int vin4_data18_pins[] = { RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), @@ -2061,12 +2070,15 @@ static const unsigned int vin4_clk_pins[] = { static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; +#endif static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clkout), SH_PFC_PIN_GROUP(audio_clkout1), +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), @@ -2079,6 +2091,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb0_avtp_pps_b), SH_PFC_PIN_GROUP(avb0_avtp_match_b), SH_PFC_PIN_GROUP(avb0_avtp_capture_b), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data_a), @@ -2094,6 +2107,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), +#endif SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), SH_PFC_PIN_GROUP(i2c2_a), @@ -2105,6 +2119,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2148,6 +2163,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), @@ -2185,13 +2201,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi3_data), SH_PFC_PIN_GROUP(ssi34_ctrl), SH_PFC_PIN_GROUP(ssi4_ctrl_a), SH_PFC_PIN_GROUP(ssi4_data_a), SH_PFC_PIN_GROUP(ssi4_ctrl_b), SH_PFC_PIN_GROUP(ssi4_data_b), +#endif SH_PFC_PIN_GROUP(usb0), +#ifdef CONFIG_PINCTRL_PFC_FULL BUS_DATA_PIN_GROUP(vin4_data, 8), BUS_DATA_PIN_GROUP(vin4_data, 10), BUS_DATA_PIN_GROUP(vin4_data, 12), @@ -2203,14 +2222,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), +#endif }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", "audio_clkout", "audio_clkout1", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2227,6 +2249,7 @@ static const char * const avb0_groups[] = { "avb0_avtp_capture_b", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const can0_groups[] = { "can0_data_a", "can0_data_b", @@ -2256,6 +2279,7 @@ static const char * const du_groups[] = { "du_cde", "du_disp", }; +#endif static const char * const i2c0_groups[] = { "i2c0", @@ -2285,6 +2309,7 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2351,6 +2376,7 @@ static const char * const pwm3_groups[] = { "pwm3_b", "pwm3_c", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2419,6 +2445,7 @@ static const char * const scif_clk_groups[] = { "scif_clk", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi3_data", "ssi34_ctrl", @@ -2427,11 +2454,13 @@ static const char * const ssi_groups[] = { "ssi4_ctrl_b", "ssi4_data_b", }; +#endif static const char * const usb0_groups[] = { "usb0", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const vin4_groups[] = { "vin4_data8", "vin4_data10", @@ -2445,22 +2474,28 @@ static const char * const vin4_groups[] = { "vin4_clkenb", "vin4_clk", }; +#endif static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -2469,6 +2504,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(rpc), @@ -2479,9 +2515,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(usb0), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(vin4), +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 6f898385027..39690bd5d07 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -1697,6 +1697,7 @@ static const unsigned int avb5_avtp_match_mux[] = { AVB5_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1817,6 +1818,7 @@ static const unsigned int du_oddf_pins[] = { static const unsigned int du_oddf_mux[] = { DU_ODDF_DISP_CDE_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1973,6 +1975,7 @@ static const unsigned int i2c6_mux[] = { SDA6_MARK, SCL6_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -2016,6 +2019,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -2060,6 +2064,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2368,6 +2373,7 @@ static const unsigned int pwm4_pins[] = { static const unsigned int pwm4_mux[] = { PWM4_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2651,6 +2657,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb5_avtp_capture), SH_PFC_PIN_GROUP(avb5_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), @@ -2665,6 +2672,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_clk_out), SH_PFC_PIN_GROUP(du_sync), SH_PFC_PIN_GROUP(du_oddf), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2687,12 +2695,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2702,6 +2712,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2744,6 +2755,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm2), SH_PFC_PIN_GROUP(pwm3), SH_PFC_PIN_GROUP(pwm4), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2852,6 +2864,7 @@ static const char * const avb5_groups[] = { "avb5_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2894,6 +2907,7 @@ static const char * const du_groups[] = { "du_sync", "du_oddf", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2947,6 +2961,7 @@ static const char * const i2c6_groups[] = { "i2c6", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -2955,6 +2970,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2966,6 +2982,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3039,6 +3056,7 @@ static const char * const pwm3_groups[] = { static const char * const pwm4_groups[] = { "pwm4", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -3105,6 +3123,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb4), SH_PFC_FUNCTION(avb5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), @@ -3116,6 +3135,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -3130,10 +3150,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -3146,6 +3169,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c index eec50210d92..2b629135f69 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -654,6 +654,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_pins[] = { /* IRQ0 */ @@ -697,6 +698,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -741,6 +743,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -916,6 +919,7 @@ static const unsigned int msiof3_rxd_pins[] = { static const unsigned int msiof3_rxd_mux[] = { MSIOF3_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -1308,12 +1312,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3), SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), BUS_DATA_PIN_GROUP(mmc_data, 8), @@ -1321,6 +1327,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -1345,6 +1352,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2), SH_PFC_PIN_GROUP(msiof3_txd), SH_PFC_PIN_GROUP(msiof3_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), SH_PFC_PIN_GROUP(pcie1_clkreq_n), SH_PFC_PIN_GROUP(qspi0_ctrl), @@ -1446,6 +1454,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0", "intc_ex_irq1", @@ -1454,6 +1463,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -1465,6 +1475,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -1500,6 +1511,7 @@ static const char * const msiof3_groups[] = { "msiof3_txd", "msiof3_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", @@ -1596,12 +1608,16 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), +#endif SH_PFC_FUNCTION(pcie), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 2a39d1c8884..f411be8b879 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -1237,6 +1237,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ----------------------------------------- */ static const unsigned int audio_clkin_pins[] = { /* CLK IN */ @@ -1252,6 +1253,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB0 ------------------------------------------------ */ static const unsigned int avb0_link_pins[] = { @@ -1487,6 +1489,7 @@ static const unsigned int avb2_avtp_match_mux[] = { AVB2_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1575,6 +1578,7 @@ static const unsigned int can_clk_pins[] = { static const unsigned int can_clk_mux[] = { CAN_CLK_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1766,6 +1770,7 @@ static const unsigned int i2c5_mux[] = { SDA5_MARK, SCL5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_a_pins[] = { /* IRQ0_A */ @@ -1849,6 +1854,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1893,6 +1899,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2156,6 +2163,7 @@ static const unsigned int msiof5_rxd_pins[] = { static const unsigned int msiof5_rxd_mux[] = { MSIOF5_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -2176,6 +2184,7 @@ static const unsigned int pcie1_clkreq_n_mux[] = { PCIE1_CLKREQ_N_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - PWM0 ------------------------------------------------------------------- */ static const unsigned int pwm0_pins[] = { /* PWM0 */ @@ -2281,6 +2290,7 @@ static const unsigned int pwm9_pins[] = { static const unsigned int pwm9_mux[] = { PWM9_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2471,6 +2481,7 @@ static const unsigned int scif_clk2_mux[] = { SCIF_CLK2_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ------------------------------------------------- */ static const unsigned int ssi_data_pins[] = { /* SSI_SD */ @@ -2486,6 +2497,7 @@ static const unsigned int ssi_ctrl_pins[] = { static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; +#endif /* - TPU -------------------------------------------------------------------- */ static const unsigned int tpu_to0_a_pins[] = { @@ -2618,9 +2630,10 @@ static const unsigned int tsn0_avtp_match_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clkin), SH_PFC_PIN_GROUP(audio_clkout), - +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), SH_PFC_PIN_GROUP(avb0_phy_int), @@ -2651,6 +2664,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb2_avtp_capture), SH_PFC_PIN_GROUP(avb2_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), @@ -2661,6 +2675,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(canfd6_data), SH_PFC_PIN_GROUP(canfd7_data), SH_PFC_PIN_GROUP(can_clk), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2688,6 +2703,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4), SH_PFC_PIN_GROUP(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0_a), SH_PFC_PIN_GROUP(intc_ex_irq0_b), SH_PFC_PIN_GROUP(intc_ex_irq1_a), @@ -2699,6 +2715,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4_a), SH_PFC_PIN_GROUP(intc_ex_irq4_b), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2708,6 +2725,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2749,10 +2767,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof5_ss2), SH_PFC_PIN_GROUP(msiof5_txd), SH_PFC_PIN_GROUP(msiof5_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), SH_PFC_PIN_GROUP(pcie1_clkreq_n), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(pwm0), SH_PFC_PIN_GROUP(pwm1_a), SH_PFC_PIN_GROUP(pwm1_b), @@ -2765,6 +2785,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm7), SH_PFC_PIN_GROUP(pwm8), SH_PFC_PIN_GROUP(pwm9), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2794,8 +2815,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi_data), SH_PFC_PIN_GROUP(ssi_ctrl), +#endif SH_PFC_PIN_GROUP(tpu_to0_a), SH_PFC_PIN_GROUP(tpu_to0_b), @@ -2816,10 +2839,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tsn0_avtp_match), }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clkin", "audio_clkout", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2857,6 +2882,7 @@ static const char * const avb2_groups[] = { "avb2_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2893,6 +2919,7 @@ static const char * const canfd7_groups[] = { static const char * const can_clk_groups[] = { "can_clk", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2948,6 +2975,7 @@ static const char * const i2c5_groups[] = { "i2c5", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0_a", "intc_ex_irq0_b", @@ -2961,6 +2989,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4_b", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2972,6 +3001,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3025,12 +3055,14 @@ static const char * const msiof5_groups[] = { "msiof5_txd", "msiof5_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", "pcie1_clkreq_n", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const pwm0_groups[] = { "pwm0", }; @@ -3072,6 +3104,7 @@ static const char * const pwm8_groups[] = { static const char * const pwm9_groups[] = { "pwm9", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -3123,10 +3156,12 @@ static const char * const scif_clk2_groups[] = { "scif_clk2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi_data", "ssi_ctrl", }; +#endif static const char * const tpu_groups[] = { "tpu_to0_a", @@ -3151,12 +3186,15 @@ static const char * const tsn0_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), SH_PFC_FUNCTION(avb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), @@ -3166,6 +3204,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(canfd6), SH_PFC_FUNCTION(canfd7), SH_PFC_FUNCTION(can_clk), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -3179,19 +3218,24 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(i2c5), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(msiof4), SH_PFC_FUNCTION(msiof5), +#endif SH_PFC_FUNCTION(pcie), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), @@ -3202,6 +3246,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm7), SH_PFC_FUNCTION(pwm8), SH_PFC_FUNCTION(pwm9), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), @@ -3213,7 +3258,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), diff --git a/drivers/pinctrl/renesas/pfc-r8a779h0.c b/drivers/pinctrl/renesas/pfc-r8a779h0.c index bfabf0c379a..87af037a8d3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779h0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779h0.c @@ -1193,6 +1193,7 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_NOGP_ALL(), }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - AUDIO CLOCK ----------------------------------------- */ static const unsigned int audio_clkin_pins[] = { /* CLK IN */ @@ -1208,6 +1209,7 @@ static const unsigned int audio_clkout_pins[] = { static const unsigned int audio_clkout_mux[] = { AUDIO_CLKOUT_MARK, }; +#endif /* - AVB0 ------------------------------------------------ */ static const unsigned int avb0_link_pins[] = { @@ -1491,6 +1493,7 @@ static const unsigned int avb2_avtp_match_mux[] = { AVB2_AVTP_MATCH_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - CANFD0 ----------------------------------------------------------------- */ static const unsigned int canfd0_data_pins[] = { /* CANFD0_TX, CANFD0_RX */ @@ -1535,6 +1538,7 @@ static const unsigned int can_clk_pins[] = { static const unsigned int can_clk_mux[] = { CAN_CLK_MARK, }; +#endif /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { @@ -1708,6 +1712,7 @@ static const unsigned int i2c3_mux[] = { SDA3_MARK, SCL3_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - INTC-EX ---------------------------------------------------------------- */ static const unsigned int intc_ex_irq0_a_pins[] = { /* IRQ0_A */ @@ -1791,6 +1796,7 @@ static const unsigned int intc_ex_irq5_pins[] = { static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#endif /* - MMC -------------------------------------------------------------------- */ static const unsigned int mmc_data_pins[] = { @@ -1835,6 +1841,7 @@ static const unsigned int mmc_ds_mux[] = { MMC_DS_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* MSIOF0_SCK */ @@ -2098,6 +2105,7 @@ static const unsigned int msiof5_rxd_pins[] = { static const unsigned int msiof5_rxd_mux[] = { MSIOF5_RXD_MARK, }; +#endif /* - PCIE ------------------------------------------------------------------- */ static const unsigned int pcie0_clkreq_n_pins[] = { @@ -2109,6 +2117,7 @@ static const unsigned int pcie0_clkreq_n_mux[] = { PCIE0_CLKREQ_N_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - PWM0 --------------------------------------------------------------------- */ static const unsigned int pwm0_a_pins[] = { /* PWM0_A */ @@ -2209,6 +2218,7 @@ static const unsigned int pwm4_pins[] = { static const unsigned int pwm4_mux[] = { PWM4_MARK, }; +#endif /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { @@ -2399,6 +2409,7 @@ static const unsigned int scif_clk2_mux[] = { SCIF_CLK2_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_FULL /* - SSI ------------------------------------------------- */ static const unsigned int ssi_data_pins[] = { /* SSI_SD */ @@ -2414,6 +2425,7 @@ static const unsigned int ssi_ctrl_pins[] = { static const unsigned int ssi_ctrl_mux[] = { SSI_SCK_MARK, SSI_WS_MARK, }; +#endif /* - TPU --------------------------------------------------------------------- */ static const unsigned int tpu_to0_a_pins[] = { @@ -2475,8 +2487,10 @@ static const unsigned int tpu_to3_b_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(audio_clkin), SH_PFC_PIN_GROUP(audio_clkout), +#endif SH_PFC_PIN_GROUP(avb0_link), SH_PFC_PIN_GROUP(avb0_magic), @@ -2510,11 +2524,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb2_avtp_capture), SH_PFC_PIN_GROUP(avb2_avtp_match), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(canfd0_data), SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(canfd2_data), SH_PFC_PIN_GROUP(canfd3_data), SH_PFC_PIN_GROUP(can_clk), +#endif SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), @@ -2540,6 +2556,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2), SH_PFC_PIN_GROUP(i2c3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(intc_ex_irq0_a), SH_PFC_PIN_GROUP(intc_ex_irq0_b), SH_PFC_PIN_GROUP(intc_ex_irq1_a), @@ -2551,6 +2568,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4_a), SH_PFC_PIN_GROUP(intc_ex_irq4_b), SH_PFC_PIN_GROUP(intc_ex_irq5), +#endif BUS_DATA_PIN_GROUP(mmc_data, 1), BUS_DATA_PIN_GROUP(mmc_data, 4), @@ -2560,6 +2578,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_wp), SH_PFC_PIN_GROUP(mmc_ds), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2601,9 +2620,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof5_ss2), SH_PFC_PIN_GROUP(msiof5_txd), SH_PFC_PIN_GROUP(msiof5_rxd), +#endif SH_PFC_PIN_GROUP(pcie0_clkreq_n), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(pwm0_a), SH_PFC_PIN_GROUP(pwm0_b), SH_PFC_PIN_GROUP(pwm1_a), @@ -2616,6 +2637,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), SH_PFC_PIN_GROUP(pwm4), +#endif SH_PFC_PIN_GROUP(qspi0_ctrl), BUS_DATA_PIN_GROUP(qspi0_data, 2), @@ -2645,8 +2667,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_PIN_GROUP(ssi_data), SH_PFC_PIN_GROUP(ssi_ctrl), +#endif SH_PFC_PIN_GROUP(tpu_to0_a), SH_PFC_PIN_GROUP(tpu_to0_b), @@ -2658,10 +2682,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_b), }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const audio_clk_groups[] = { "audio_clkin", "audio_clkout", }; +#endif static const char * const avb0_groups[] = { "avb0_link", @@ -2701,6 +2727,7 @@ static const char * const avb2_groups[] = { "avb2_avtp_match", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const canfd0_groups[] = { "canfd0_data", }; @@ -2720,6 +2747,7 @@ static const char * const canfd3_groups[] = { static const char * const can_clk_groups[] = { "can_clk", }; +#endif static const char * const hscif0_groups[] = { "hscif0_data", @@ -2767,6 +2795,7 @@ static const char * const i2c3_groups[] = { "i2c3", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const intc_ex_groups[] = { "intc_ex_irq0_a", "intc_ex_irq0_b", @@ -2780,6 +2809,7 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq4_b", "intc_ex_irq5", }; +#endif static const char * const mmc_groups[] = { "mmc_data1", @@ -2791,6 +2821,7 @@ static const char * const mmc_groups[] = { "mmc_ds", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -2844,11 +2875,13 @@ static const char * const msiof5_groups[] = { "msiof5_txd", "msiof5_rxd", }; +#endif static const char * const pcie_groups[] = { "pcie0_clkreq_n", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2875,6 +2908,7 @@ static const char * const pwm3_groups[] = { static const char * const pwm4_groups[] = { "pwm4", }; +#endif static const char * const qspi0_groups[] = { "qspi0_ctrl", @@ -2926,10 +2960,12 @@ static const char * const scif_clk2_groups[] = { "scif_clk2", }; +#ifdef CONFIG_PINCTRL_PFC_FULL static const char * const ssi_groups[] = { "ssi_data", "ssi_ctrl", }; +#endif static const char * const tpu_groups[] = { "tpu_to0_a", @@ -2943,17 +2979,21 @@ static const char * const tpu_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(audio_clk), +#endif SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(avb1), SH_PFC_FUNCTION(avb2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(canfd2), SH_PFC_FUNCTION(canfd3), SH_PFC_FUNCTION(can_clk), +#endif SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -2965,24 +3005,30 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(intc_ex), +#endif SH_PFC_FUNCTION(mmc), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(msiof4), SH_PFC_FUNCTION(msiof5), +#endif SH_PFC_FUNCTION(pcie), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), +#endif SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), @@ -2994,7 +3040,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif_clk2), +#ifdef CONFIG_PINCTRL_PFC_FULL SH_PFC_FUNCTION(ssi), +#endif SH_PFC_FUNCTION(tpu), }; diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 2f6c3b3d1c7..db6be39a528 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -961,90 +961,50 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (!priv->pfc.regs) return -ENOMEM; -#ifdef CONFIG_PINCTRL_PFC_R8A7790 - if (model == SH_PFC_R8A7790) + if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7790) && model == SH_PFC_R8A7790) priv->pfc.info = &r8a7790_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7791 - if (model == SH_PFC_R8A7791) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7791) && model == SH_PFC_R8A7791) priv->pfc.info = &r8a7791_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7792 - if (model == SH_PFC_R8A7792) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7792) && model == SH_PFC_R8A7792) priv->pfc.info = &r8a7792_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7793 - if (model == SH_PFC_R8A7793) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7793) && model == SH_PFC_R8A7793) priv->pfc.info = &r8a7793_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A7794 - if (model == SH_PFC_R8A7794) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7794) && model == SH_PFC_R8A7794) priv->pfc.info = &r8a7794_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77951 - if (model == SH_PFC_R8A7795) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77951) && model == SH_PFC_R8A7795) priv->pfc.info = &r8a77951_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77960 - if (model == SH_PFC_R8A77960) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77960) && model == SH_PFC_R8A77960) priv->pfc.info = &r8a77960_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77961 - if (model == SH_PFC_R8A77961) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77961) && model == SH_PFC_R8A77961) priv->pfc.info = &r8a77961_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774A1 - if (model == SH_PFC_R8A774A1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774A1) && model == SH_PFC_R8A774A1) priv->pfc.info = &r8a774a1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774B1 - if (model == SH_PFC_R8A774B1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774B1) && model == SH_PFC_R8A774B1) priv->pfc.info = &r8a774b1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774C0 - if (model == SH_PFC_R8A774C0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774C0) && model == SH_PFC_R8A774C0) priv->pfc.info = &r8a774c0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A774E1 - if (model == SH_PFC_R8A774E1) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774E1) && model == SH_PFC_R8A774E1) priv->pfc.info = &r8a774e1_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77965 - if (model == SH_PFC_R8A77965) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77965) && model == SH_PFC_R8A77965) priv->pfc.info = &r8a77965_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77970 - if (model == SH_PFC_R8A77970) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77970) && model == SH_PFC_R8A77970) priv->pfc.info = &r8a77970_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77980 - if (model == SH_PFC_R8A77980) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77980) && model == SH_PFC_R8A77980) priv->pfc.info = &r8a77980_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77990 - if (model == SH_PFC_R8A77990) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77990) && model == SH_PFC_R8A77990) priv->pfc.info = &r8a77990_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A77995 - if (model == SH_PFC_R8A77995) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77995) && model == SH_PFC_R8A77995) priv->pfc.info = &r8a77995_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779A0 - if (model == SH_PFC_R8A779A0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779A0) && model == SH_PFC_R8A779A0) priv->pfc.info = &r8a779a0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779F0 - if (model == SH_PFC_R8A779F0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779F0) && model == SH_PFC_R8A779F0) priv->pfc.info = &r8a779f0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779G0 - if (model == SH_PFC_R8A779G0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779G0) && model == SH_PFC_R8A779G0) priv->pfc.info = &r8a779g0_pinmux_info; -#endif -#ifdef CONFIG_PINCTRL_PFC_R8A779H0 - if (model == SH_PFC_R8A779H0) + else if (IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779H0) && model == SH_PFC_R8A779H0) priv->pfc.info = &r8a779h0_pinmux_info; -#endif + else + return -ENODEV; priv->pmx.pfc = &priv->pfc; sh_pfc_init_ranges(&priv->pfc); @@ -1054,127 +1014,127 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) } static const struct udevice_id sh_pfc_pinctrl_ids[] = { -#ifdef CONFIG_PINCTRL_PFC_R8A7790 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7790) { .compatible = "renesas,pfc-r8a7790", .data = SH_PFC_R8A7790, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7791 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7791) { .compatible = "renesas,pfc-r8a7791", .data = SH_PFC_R8A7791, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7792 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7792) { .compatible = "renesas,pfc-r8a7792", .data = SH_PFC_R8A7792, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7793 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7793) { .compatible = "renesas,pfc-r8a7793", .data = SH_PFC_R8A7793, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7794 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A7794) { .compatible = "renesas,pfc-r8a7794", .data = SH_PFC_R8A7794, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77951 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77951) { .compatible = "renesas,pfc-r8a7795", .data = SH_PFC_R8A7795, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77960 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77960) { .compatible = "renesas,pfc-r8a7796", .data = SH_PFC_R8A77960, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77961 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77961) { .compatible = "renesas,pfc-r8a77961", .data = SH_PFC_R8A77961, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774A1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774A1) { .compatible = "renesas,pfc-r8a774a1", .data = SH_PFC_R8A774A1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774B1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774B1) { .compatible = "renesas,pfc-r8a774b1", .data = SH_PFC_R8A774B1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774C0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774C0) { .compatible = "renesas,pfc-r8a774c0", .data = SH_PFC_R8A774C0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A774E1 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A774E1) { .compatible = "renesas,pfc-r8a774e1", .data = SH_PFC_R8A774E1, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77965 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77965) { .compatible = "renesas,pfc-r8a77965", .data = SH_PFC_R8A77965, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77970 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77970) { .compatible = "renesas,pfc-r8a77970", .data = SH_PFC_R8A77970, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77980 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77980) { .compatible = "renesas,pfc-r8a77980", .data = SH_PFC_R8A77980, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77990 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77990) { .compatible = "renesas,pfc-r8a77990", .data = SH_PFC_R8A77990, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A77995 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A77995) { .compatible = "renesas,pfc-r8a77995", .data = SH_PFC_R8A77995, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779A0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779A0) { .compatible = "renesas,pfc-r8a779a0", .data = SH_PFC_R8A779A0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779F0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779F0) { .compatible = "renesas,pfc-r8a779f0", .data = SH_PFC_R8A779F0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779G0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779G0) { .compatible = "renesas,pfc-r8a779g0", .data = SH_PFC_R8A779G0, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A779H0 +#if IS_ENABLED(CONFIG_PINCTRL_PFC_R8A779H0) { .compatible = "renesas,pfc-r8a779h0", .data = SH_PFC_R8A779H0, diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c index c3490db2a08..57d470521fc 100644 --- a/drivers/power/pmic/tps65941.c +++ b/drivers/power/pmic/tps65941.c @@ -74,7 +74,7 @@ static const struct udevice_id tps65941_ids[] = { { .compatible = "ti,tps659412", .data = TPS659411 }, { .compatible = "ti,tps659413", .data = TPS659413 }, { .compatible = "ti,lp876441", .data = LP876441 }, - { .compatible = "ti,tps65224", .data = TPS65224 }, + { .compatible = "ti,tps65224-q1", .data = TPS65224 }, { .compatible = "ti,tps6594-q1", .data = TPS659411 }, { .compatible = "ti,tps6593-q1", .data = TPS659413 }, { .compatible = "ti,lp8764-q1", .data = LP876441 }, diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index 2dc261d83e3..70df51b5fa4 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -536,6 +536,21 @@ static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = { {} }; +static const struct rpmh_vreg_init_data pmc8380_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"), + {} +}; + /* probe an individual regulator */ static int rpmh_regulator_probe(struct udevice *dev) { @@ -662,6 +677,10 @@ static const struct udevice_id rpmh_regulator_ids[] = { .compatible = "qcom,pm8550vs-rpmh-regulators", .data = (ulong)pm8550vs_vreg_data, }, + { + .compatible = "qcom,pmc8380-rpmh-regulators", + .data = (ulong)pmc8380_vreg_data, + }, { /* sentinal */ }, }; diff --git a/drivers/power/regulator/tps65219_regulator.c b/drivers/power/regulator/tps65219_regulator.c index b7124fed024..88abc896b3a 100644 --- a/drivers/power/regulator/tps65219_regulator.c +++ b/drivers/power/regulator/tps65219_regulator.c @@ -72,12 +72,12 @@ static int tps65219_buck_enable(struct udevice *dev, int op, bool *enable) static int tps65219_buck_volt2val(int uV) { - if (uV > TPS65219_BUCK_VOLT_MAX) + if (uV > TPS65219_BUCK_3V4) return -EINVAL; - else if (uV >= 1400000) - return (uV - 1400000) / 100000 + 0x20; - else if (uV >= 600000) - return (uV - 600000) / 25000 + 0x00; + else if (uV >= TPS65219_BUCK_1V4) + return (uV - TPS65219_BUCK_1V4) / TPS65219_VOLT_STEP_100MV + TPS65219_BUCK_REG_1V4; + else if (uV >= TPS65219_BUCK_0V6) + return (uV - TPS65219_BUCK_0V6) / TPS65219_VOLT_STEP_25MV + TPS65219_BUCK_REG_0V6; else return -EINVAL; } @@ -86,12 +86,12 @@ static int tps65219_buck_val2volt(int val) { if (val > TPS65219_VOLT_MASK) return -EINVAL; - else if (val > 0x34) - return TPS65219_BUCK_VOLT_MAX; - else if (val > 0x20) - return 1400000 + (val - 0x20) * 100000; - else if (val >= 0) - return 600000 + val * 25000; + else if (val > TPS65219_BUCK_REG_3V4) + return TPS65219_BUCK_3V4; + else if (val > TPS65219_BUCK_REG_1V4) + return TPS65219_BUCK_1V4 + (val - TPS65219_BUCK_REG_1V4) * TPS65219_VOLT_STEP_100MV; + else if (val >= TPS65219_BUCK_REG_0V6) + return TPS65219_BUCK_0V6 + val * TPS65219_VOLT_STEP_25MV; else return -EINVAL; } @@ -161,7 +161,7 @@ static int tps65219_ldo_volt2val(int idx, int uV) if (uV > max) return -EINVAL; else if (uV >= base) - return (uV - TPS65219_LDO12_VOLT_MIN) / 50000; + return (uV - TPS65219_LDO12_VOLT_MIN) / TPS65219_VOLT_STEP_50MV; else return -EINVAL; } @@ -187,7 +187,7 @@ static int tps65219_ldo_val2volt(int idx, int val) else if (val <= reg_base) return base; else if (val >= 0) - return TPS65219_LDO12_VOLT_MIN + (50000 * val); + return TPS65219_LDO12_VOLT_MIN + (TPS65219_VOLT_STEP_50MV * val); else return -EINVAL; } @@ -250,7 +250,7 @@ static int tps65219_ldo_probe(struct udevice *dev) /* idx must be in 1..TPS65219_LDO_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_LDO_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } @@ -271,7 +271,7 @@ static int tps65219_buck_probe(struct udevice *dev) /* idx must be in 1..TPS65219_BUCK_NUM */ idx = dev->driver_data; if (idx < 1 || idx > TPS65219_BUCK_NUM) { - printf("Wrong ID for regulator\n"); + pr_err("Wrong ID for regulator\n"); return -EINVAL; } diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index f7e357f24da..899d7585489 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -116,9 +116,20 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC. +config K3_INLINE_ECC + bool "Enable TI Inline ECC support" + depends on K3_DDRSS + help + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space + is used for ECC storage and the rest 8/9th is available for system + use. Enabling ECC increases boot time as the ECC protected regions + need to be primed with a predefined value prior to enabling ECC + check. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig" +source "drivers/ram/renesas/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6e9202b9579..05ea61bbfe9 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -6,6 +6,7 @@ */ #include <config.h> +#include <time.h> #include <clk.h> #include <div64.h> #include <dm.h> @@ -44,6 +45,11 @@ #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_V2A_INT_SET_REG 0x00a8 + +#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3) +#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4) +#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5) #define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 @@ -120,8 +126,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3 struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; }; struct k3_ddrss_desc { @@ -145,7 +151,9 @@ struct k3_ddrss_desc { lpddr4_privatedata pd; struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; u64 ecc_reserved_space; - bool ti_ecc_enabled; + u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS]; + u64 ddr_bank_size[CONFIG_NR_DRAM_BANKS]; + u64 ddr_ram_size; }; struct reginitdata { @@ -399,8 +407,6 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev) if (ret) dev_err(dev, "ddr fhs cnt not populated %d\n", ret); - ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable"); - return ret; } @@ -542,27 +548,174 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } } -static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); } -static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) +#define BIST_MODE_MEM_INIT 4 +#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */ +static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, + u64 addr, u64 size, + u32 pattern) { - int i; + lpddr4_obj *driverdt = ddrss->driverdt; + lpddr4_privatedata *pd = &ddrss->pd; + u32 status, offset, regval; + bool int_status; + int i = 0; + + /* Set BIST_START_ADDR_0 [31:0] */ + regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_START_ADDR_1 [32 or 34:32] */ + regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD)); + regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set ADDR_SPACE = log2(size) */ + regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a + * register with ADDR_SPACE and BIST_GO. + */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + /* Clear the address check bit */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_TEST_MODE[2:0] to memory initialize (4) */ + regval = BIST_MODE_MEM_INIT; + TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_DATA_PATTERN[31:0] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + /* Set BIST_DATA_PATTERN[63:32] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + udelay(1000); + + /* Enable the programmed BIST operation - BIST_GO = 1 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Wait for the BIST_DONE interrupt */ + while (i < BIST_MEM_INIT_TIMEOUT) { + status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, + &int_status); + if (!status & int_status) { + /* Clear LPDDR4_INTR_BIST_DONE */ + driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); + break; + } + udelay(1000); + i++; + } + + /* Before continuing we have to stop BIST - BIST_GO = 0 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0); + /* Timeout hit while priming the memory. We can't continue, + * since the memory is not fully initialized and we most + * likely get an uncorrectable error exception while booting. + */ + if (i == BIST_MEM_INIT_TIMEOUT) { + printf("ERROR: Timeout while priming the memory.\n"); + hang(); + } +} + +static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, + u64 total_size, u32 pattern) +{ + u32 done, max_size2; + + /* Get the max size (log2) supported in this config (16/32 lpddr4) + * from the start_addess width - 16bit: 8G, 32bit: 32G + */ + max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) + + TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1; + + /* ECC is enabled in dt but we can't preload the memory if + * the memory configuration is recognized and supported. + */ + if (!total_size || total_size > (1ull << max_size2) || + total_size & (total_size - 1)) { + printf("ECC: the memory configuration is not supported\n"); + hang(); + } printf("ECC is enabled, priming DDR which will take several seconds.\n"); + done = get_timer(0); + k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern); + printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); +} + +static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) +{ + int bank, na, ns, len, parent; + const fdt32_t *ptr, *end; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + ddrss->ddr_bank_base[bank] = 0; + ddrss->ddr_bank_size[bank] = 0; + } + + ofnode mem = ofnode_null(); + + do { + mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); + } while (!ofnode_is_enabled(mem)); + + const void *fdt = ofnode_to_fdt(mem); + int node = ofnode_to_offset(mem); + const char *property = "reg"; + + parent = fdt_parent_offset(fdt, node); + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + ptr = fdt_getprop(fdt, node, property, &len); + end = ptr + len / sizeof(*ptr); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (ptr + na + ns <= end) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) + ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr); + else + ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na); + + ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns); + } - for (i = 0; i < (size / 4); i++) - addr[i] = word; + ptr += na + ns; + } + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) + ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; } static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); - ddrss->ecc_reserved_space = gd->ram_size; + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9); /* Round to clean number */ @@ -571,25 +724,29 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val; /* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range); /* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG); - /* Preload ECC Mem region with 0's */ - k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, - 0x00000000); + /* Preload the full memory with 0's using the BIST engine of + * the LPDDR4 controller. + */ + k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0); /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); + writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN | + DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG); + /* Enable ECC Check */ val = readl(base + DDRSS_ECC_CTRL_REG); val |= DDRSS_ECC_CTRL_REG_ECC_CK; @@ -630,7 +787,9 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - if (ddrss->ti_ecc_enabled) { + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", __func__); @@ -640,8 +799,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss); /* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); } @@ -650,30 +809,24 @@ static int k3_ddrss_probe(struct udevice *dev) int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) { - struct k3_ddrss_desc *ddrss = dev_get_priv(dev); - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; int bank; + struct k3_ddrss_desc *ddrss = dev_get_priv(dev); if (ddrss->ecc_reserved_space == 0) return 0; for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { - if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { - ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; - bd->bi_dram[bank].size = 0; + if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) { + ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank]; + ddrss->ddr_bank_size[bank] = 0; } else { - bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; + ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space; break; } } - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; - } - - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base, + ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS); } static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info) diff --git a/drivers/ram/renesas/Kconfig b/drivers/ram/renesas/Kconfig new file mode 100644 index 00000000000..6a1ef2a0c63 --- /dev/null +++ b/drivers/ram/renesas/Kconfig @@ -0,0 +1,7 @@ +config RAM_RENESAS_DBSC5 + bool "Renesas R-Car V4H/V4M DBSC5 controller driver" + depends on SPL && RAM && (R8A779G0 || R8A779H0) + default n + help + Enable this to support the DBSC5 DRAM controller initialization + on Renesas R8A779G0/R8A779H0 SoCs. diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile index 705cc4b6fa5..578d05622d7 100644 --- a/drivers/ram/renesas/Makefile +++ b/drivers/ram/renesas/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/ +endif obj-$(CONFIG_RZN1) += rzn1/ diff --git a/drivers/ram/renesas/dbsc5/Makefile b/drivers/ram/renesas/dbsc5/Makefile new file mode 100644 index 00000000000..177be893e10 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += dbsc5.o dram.o qos.o rtvram.o diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c new file mode 100644 index 00000000000..d24b7c5c30a --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dbsc5.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <errno.h> +#include <linux/sizes.h> +#include <ram.h> +#include "dbsc5.h" + +static int renesas_dbsc5_probe(struct udevice *dev) +{ + struct udevice *pdev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &pdev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_NOP, "dbsc5_qos", &pdev); + if (ret) + return ret; + + return 0; +} + +int renesas_dbsc5_bind(struct udevice *dev) +{ + struct udevice *ramdev, *qosdev; + struct driver *ramdrv, *qosdrv; + int ret; + + ramdrv = lists_driver_lookup_name("dbsc5_dram"); + if (!ramdrv) + return -ENOENT; + + + qosdrv = lists_driver_lookup_name("dbsc5_qos"); + if (!qosdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", + dev_get_driver_data(dev), + dev_ofnode(dev), &ramdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(dev, qosdrv, "dbsc5_qos", 0, + dev_ofnode(dev), &qosdev); + if (ret) + device_unbind(ramdev); + + return ret; +} + +struct renesas_dbsc5_data r8a779g0_dbsc5_data = { + .clock_node = "renesas,r8a779g0-cpg-mssr", + .reset_node = "renesas,r8a779g0-rst" +}; + +static const struct udevice_id renesas_dbsc5_ids[] = { + { + .compatible = "renesas,r8a779g0-dbsc", + .data = (ulong)&r8a779g0_dbsc5_data + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5) = { + .name = "dbsc5", + .id = UCLASS_NOP, + .of_match = renesas_dbsc5_ids, + .bind = renesas_dbsc5_bind, + .probe = renesas_dbsc5_probe, +}; diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h new file mode 100644 index 00000000000..c410eb0c5ed --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dbsc5.h @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ + +/* + * DBSC5 ... 0xe678_0000..0xe67fffff + * - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0 + * - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0 + * - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM + * - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0 + * - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB) + */ +#define DBSC5_AXMM_OFFSET 0x00000 +#define DBSC5_DBSC_A_OFFSET 0x10000 +#define DBSC5_CCI_OFFSET 0x20000 +#define DBSC5_DBSC_D_OFFSET 0x24000 +#define DBSC5_QOS_OFFSET 0x60000 + +struct renesas_dbsc5_data { + const char *clock_node; + const char *reset_node; +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c new file mode 100644 index 00000000000..210a68f6496 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/dram.c @@ -0,0 +1,4532 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <hang.h> +#include <ram.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include "dbsc5.h" + +/* The number of channels V4H has */ +#define DRAM_CH_CNT 4 +/* The number of slices V4H has */ +#define SLICE_CNT 2 +/* The number of chip select V4H has */ +#define CS_CNT 2 + +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 +/* Number of array elements in Address Slice */ +#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 +/* Number of array elements in Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 +/* Number of array elements in PI Register */ +#define DDR_PI_REGSET_NUM_V4H 1381 + +/* Minimum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_LO 5 +/* Maximum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_HI 11 +/* The number of JS1 setting table */ +#define JS1_FREQ_TBL_NUM 12 +/* Macro to set the value of MR1 */ +#define JS1_MR1(f) (((f) << 4) | 0x00) /* CK mode = 0B */ +/* Macro to set the value of MR2 */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +#define JS2_tSR 0 /* Element for self refresh */ +#define JS2_tXP 1 /* Exit power-down mode to first valid command */ +#define JS2_tRCD 2 /* Active to read or write delay */ +#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ +#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ +#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ +#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ +#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ +#define JS2_tRRD 8 /* Active bank a to active bank b command */ +#define JS2_tPPD 9 /* Precharge Power Down */ +#define JS2_tFAW 10 /* Four bank ACT window */ +#define JS2_tMRR 11 /* Mode Register Read */ +#define JS2_tMRW 12 /* Mode Register Write */ +#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ +#define JS2_tZQCALns 14 /* ZQ Calibration */ +#define JS2_tZQLAT 15 /* ZQ Latency */ +#define JS2_tODTon_min 16 /* Minimum time on die termination */ +#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ +#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ +#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ +#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ +#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ +#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ +#define JS2_tDQ72DQns 25 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ +#define JS2_tCAENTns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ +#define JS2_tCSCAL 27 /* Minimum CA Low Duration time */ +#define JS2_TBLCNT 28 /* The number of table */ + +#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ +#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ +#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ +#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ +#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ +#define JS2_tPDN (JS2_TBLCNT + 5) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) +#define JS2_CNT (JS2_TBLCNT + 7) + +struct jedec_spec1 { + u32 fx3; /* Frequency */ + u8 RLset1; /* setting value of Read Latency */ + u8 RLset2; /* setting value of Read Latency */ + u8 WLsetA; /* setting value of Write Latency */ + u8 WLsetB; /* setting value of Write Latency */ + u32 nWR; /* Write-Recovery for Auto-Precharge commands */ + u32 nRBTP; /* the minimum interval from a READ command to a PRE command */ + u32 ODTLon; /* On Die Termination */ + u8 MR1; /* Mode Register 1 */ + u8 MR2; /* Mode Register 2 */ + u32 WCKENLR; /* The setting time from CAS command to the Start-up of WCK in READ operation */ + u32 WCKENLW; /* The setting time from CAS command to the Start-up of WCK in WRITE operation */ + u32 WCKENLF; /* The setting time from CAS command to the Start-up of WCK in FAST-sync operation */ + u32 WCKPRESTA; /* The setting time from the Start-up of WCK to WCK Clocling Start */ + u32 WCKPRETGLR; /* The setting time from WCK Clocling Start to Reflecting frequency of WCK */ +}; + +static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ +}; + +struct jedec_spec2 { + u16 ps; /* Value in pico seconds */ + u16 cyc; /* Value in cycle count */ +}; + +static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 18000, 2 }, /* tRCD */ + { 18000, 2 }, /* tRPpb */ + { 21000, 2 }, /* tRPab */ + { 42000, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 700, 0 }, /* tWCK2DQI_HF */ + { 1600, 0 }, /* tWCK2DQO_HF */ + { 900, 0 }, /* tWCK2DQI_LF */ + { 1900, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + }, { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 19875, 2 }, /* tRCD */ + { 19875, 2 }, /* tRPpb */ + { 22875, 2 }, /* tRPab */ + { 43875, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 715, 0 }, /* tWCK2DQI_HF */ + { 1635, 0 }, /* tWCK2DQO_HF */ + { 920, 0 }, /* tWCK2DQI_LF */ + { 1940, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + } +}; + +static const u16 jedec_spec2_tRFC_ab[] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +/* The address offsets of PI Register */ +#define DDR_PI_REGSET_OFS_V4H 0x0800 +/* The address offsets of Data Slice */ +#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 +/* The address offsets of Address Slice */ +#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 +/* The address offsets of Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFF) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFF) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFF) + +#define DDR_REGDEF(lsb, len, adr) \ + (((lsb) << 24) | ((len) << 16) | (adr)) + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1000) +#define PHY_PER_CS_TRAINING_MULTICAST_EN DDR_REGDEF(0x10, 0x01, 0x1006) +#define PHY_PER_CS_TRAINING_INDEX DDR_REGDEF(0x18, 0x01, 0x1006) +#define PHY_VREF_INITIAL_STEPSIZE DDR_REGDEF(0x18, 0x08, 0x100D) +#define PHY_RDLVL_BEST_THRSHLD DDR_REGDEF(0x00, 0x04, 0x100E) +#define PHY_RDLVL_VREF_OUTLIER DDR_REGDEF(0x10, 0x03, 0x100E) +#define SC_PHY_WCK_CALC DDR_REGDEF(0x18, 0x01, 0x101A) +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT DDR_REGDEF(0x10, 0x05, 0x102C) +#define PHY_CALVL_VREF_DRIVING_SLICE DDR_REGDEF(0x18, 0x01, 0x1030) +#define PHY_WRLVL_HARD0_DELAY_OBS DDR_REGDEF(0x00, 0x0A, 0x1038) +#define PHY_WRLVL_HARD1_DELAY_OBS DDR_REGDEF(0x10, 0x0A, 0x1038) +#define PHY_WRLVL_STATUS_OBS DDR_REGDEF(0x00, 0x1C, 0x1039) +#define PHY_WRLVL_ERROR_OBS DDR_REGDEF(0x00, 0x10, 0x103B) +#define PHY_GTLVL_STATUS_OBS DDR_REGDEF(0x00, 0x12, 0x103D) +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS DDR_REGDEF(0x10, 0x09, 0x103E) +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F) +#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043) +#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D) +#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050) +#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055) +#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055) +#define PHY_VREF_TRAINING_CTRL DDR_REGDEF(0x00, 0x02, 0x1056) +#define PHY_RDDQ0_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105D) +#define PHY_RDDQ1_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105D) +#define PHY_RDDQ2_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105E) +#define PHY_RDDQ3_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105E) +#define PHY_RDDQ4_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105F) +#define PHY_RDDQ5_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105F) +#define PHY_RDDQ6_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1060) +#define PHY_RDDQ7_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x1060) +#define PHY_RDDM_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1061) +#define PHY_RX_CAL_ALL_DLY DDR_REGDEF(0x18, 0x06, 0x1061) +#define PHY_RX_PCLK_CLK_SEL DDR_REGDEF(0x00, 0x03, 0x1062) +#define PHY_DATA_DC_CAL_CLK_SEL DDR_REGDEF(0x18, 0x03, 0x1063) +#define PHY_PAD_VREF_CTRL_DQ DDR_REGDEF(0x00, 0x0E, 0x1067) +#define PHY_PER_CS_TRAINING_EN DDR_REGDEF(0x00, 0x01, 0x1068) +#define PHY_RDDATA_EN_TSEL_DLY DDR_REGDEF(0x18, 0x05, 0x1069) +#define PHY_RDDATA_EN_OE_DLY DDR_REGDEF(0x00, 0x05, 0x106A) +#define PHY_RPTR_UPDATE DDR_REGDEF(0x10, 0x04, 0x106C) +#define PHY_WRLVL_RESP_WAIT_CNT DDR_REGDEF(0x08, 0x06, 0x106D) +#define PHY_RDLVL_DLY_STEP DDR_REGDEF(0x08, 0x04, 0x1070) +#define PHY_RDLVL_MAX_EDGE DDR_REGDEF(0x00, 0x09, 0x1071) +#define PHY_DATA_DC_WDQLVL_ENABLE DDR_REGDEF(0x08, 0x02, 0x1075) +#define PHY_RDDATA_EN_DLY DDR_REGDEF(0x10, 0x05, 0x1076) +#define PHY_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x08, 0x06, 0x1076) +#define PHY_DQ_DM_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1077) +#define PHY_DQ_DM_SWIZZLE1 DDR_REGDEF(0x00, 0x04, 0x1078) +#define PHY_CLK_WRDQS_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x107E) +#define PHY_WRITE_PATH_LAT_DEC DDR_REGDEF(0x10, 0x01, 0x107E) +#define PHY_RDDQS_GATE_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1088) +#define PHY_RDDQS_LATENCY_ADJUST DDR_REGDEF(0x10, 0x05, 0x1088) +#define PHY_WRITE_PATH_LAT_ADD DDR_REGDEF(0x18, 0x03, 0x1088) +#define PHY_WRITE_PATH_LAT_FRAC DDR_REGDEF(0x00, 0x08, 0x1089) +#define PHY_GTLVL_LAT_ADJ_START DDR_REGDEF(0x00, 0x05, 0x108A) +#define PHY_DATA_DC_DQS_CLK_ADJUST DDR_REGDEF(0x00, 0x08, 0x108C) +#define PHY_ADR_CALVL_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1202) +#define PHY_ADR_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x10, 0x01, 0x1203) +#define PHY_ADR_CALVL_RANK_CTRL DDR_REGDEF(0x18, 0x02, 0x1205) +#define PHY_ADR_CALVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x120A) +#define PHY_ADR_CALVL_OBS2 DDR_REGDEF(0x00, 0x20, 0x120B) +#define PHY_ADR_CALVL_DLY_STEP DDR_REGDEF(0x00, 0x04, 0x1210) +#define PHY_CS_ACS_ALLOCATION_BIT2_2 DDR_REGDEF(0x08, 0x02, 0x1215) +#define PHY_CS_ACS_ALLOCATION_BIT3_2 DDR_REGDEF(0x10, 0x02, 0x1215) +#define PHY_CSLVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x1221) +#define PHY_CLK_DC_CAL_CLK_SEL DDR_REGDEF(0x08, 0x03, 0x123A) +#define PHY_FREQ_SEL_MULTICAST_EN DDR_REGDEF(0x08, 0x01, 0x1301) +#define PHY_FREQ_SEL_INDEX DDR_REGDEF(0x10, 0x02, 0x1301) +#define SC_PHY_MANUAL_UPDATE DDR_REGDEF(0x18, 0x01, 0x1304) +#define PHY_SET_DFI_INPUT_RST_PAD DDR_REGDEF(0x18, 0x01, 0x1311) +#define PHY_CAL_MODE_0 DDR_REGDEF(0x00, 0x0D, 0x132C) +#define PHY_CAL_INTERVAL_COUNT_0 DDR_REGDEF(0x00, 0x20, 0x132D) +#define PHY_DATA_BYTE_ORDER_SEL DDR_REGDEF(0x00, 0x20, 0x133E) +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1348) +#define PHY_PLL_CTRL DDR_REGDEF(0x00, 0x0E, 0x134B) +#define PHY_PLL_CTRL_8X DDR_REGDEF(0x10, 0x0E, 0x134B) +#define PHY_CAL_CLK_SELECT_0 DDR_REGDEF(0x00, 0x03, 0x1360) + +#define PI_START DDR_REGDEF(0x00, 0x01, 0x0800) +#define PI_TRAIN_ALL_FREQ_REQ DDR_REGDEF(0x18, 0x01, 0x0802) +#define PI_CS_MAP DDR_REGDEF(0x08, 0x02, 0x0813) +#define PI_WRLVL_REQ DDR_REGDEF(0x10, 0x01, 0x081C) +#define PI_WRLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x081C) +#define PI_RDLVL_REQ DDR_REGDEF(0x18, 0x01, 0x0824) +#define PI_RDLVL_GATE_REQ DDR_REGDEF(0x00, 0x01, 0x0825) +#define PI_RDLVL_CS_SW DDR_REGDEF(0x08, 0x02, 0x0825) +#define PI_RDLVL_PERIODIC DDR_REGDEF(0x08, 0x01, 0x082E) +#define PI_RDLVL_INTERVAL DDR_REGDEF(0x08, 0x10, 0x0835) +#define PI_DRAMDCA_FLIP_MASK DDR_REGDEF(0x08, 0x02, 0x083B) +#define PI_DRAMDCA_LVL_REQ DDR_REGDEF(0x10, 0x01, 0x083D) +#define PI_DCMLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x083D) +#define PI_WRDCM_LVL_EN_F1 DDR_REGDEF(0x00, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F1 DDR_REGDEF(0x08, 0x02, 0x083F) +#define PI_WRDCM_LVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F2 DDR_REGDEF(0x00, 0x02, 0x0840) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0868) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0869) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x086A) +#define PI_TCKCKEL_F2 DDR_REGDEF(0x18, 0x04, 0x089D) +#define PI_WDQLVL_VREF_EN DDR_REGDEF(0x08, 0x04, 0x089E) +#define PI_WDQLVL_PERIODIC DDR_REGDEF(0x00, 0x01, 0x08A0) +#define PI_WDQLVL_INTERVAL DDR_REGDEF(0x00, 0x10, 0x08A4) +#define PI_INT_STATUS DDR_REGDEF(0x00, 0x20, 0x0900) +#define PI_INT_ACK_0 DDR_REGDEF(0x00, 0x20, 0x0902) +#define PI_INT_ACK_1 DDR_REGDEF(0x00, 0x03, 0x0903) +#define PI_LONG_COUNT_MASK DDR_REGDEF(0x10, 0x05, 0x090F) +#define PI_ADDR_MUX_0 DDR_REGDEF(0x00, 0x03, 0x0910) +#define PI_ADDR_MUX_1 DDR_REGDEF(0x08, 0x03, 0x0910) +#define PI_ADDR_MUX_2 DDR_REGDEF(0x10, 0x03, 0x0910) +#define PI_ADDR_MUX_3 DDR_REGDEF(0x18, 0x03, 0x0910) +#define PI_ADDR_MUX_4 DDR_REGDEF(0x00, 0x03, 0x0911) +#define PI_ADDR_MUX_5 DDR_REGDEF(0x08, 0x03, 0x0911) +#define PI_ADDR_MUX_6 DDR_REGDEF(0x10, 0x03, 0x0911) +#define PI_DATA_BYTE_SWAP_EN DDR_REGDEF(0x18, 0x01, 0x0911) +#define PI_DATA_BYTE_SWAP_SLICE0 DDR_REGDEF(0x00, 0x01, 0x0912) +#define PI_DATA_BYTE_SWAP_SLICE1 DDR_REGDEF(0x08, 0x01, 0x0912) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_DLL_RST DDR_REGDEF(0x00, 0x01, 0x0941) +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 DDR_REGDEF(0x00, 0x08, 0x0964) +#define PI_WRLAT_F2 DDR_REGDEF(0x10, 0x07, 0x096A) +#define PI_TWCKENL_WR_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x096A) +#define PI_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096B) +#define PI_TWCKPRE_STATIC_F2 DDR_REGDEF(0x08, 0x06, 0x096B) +#define PI_TWCKPRE_TOGGLE_RD_F2 DDR_REGDEF(0x18, 0x06, 0x096B) +#define PI_TWCKENL_FS_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096C) +#define PI_CASLAT_F2 DDR_REGDEF(0x08, 0x07, 0x096C) +#define PI_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x0971) +#define PI_TREF_F2 DDR_REGDEF(0x00, 0x14, 0x0972) +#define PI_TDFI_WRLVL_WW_F0 DDR_REGDEF(0x00, 0x0A, 0x0974) +#define PI_TDFI_WRLVL_WW_F1 DDR_REGDEF(0x00, 0x0A, 0x0975) +#define PI_WRLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x0975) +#define PI_TDFI_WRLVL_WW_F2 DDR_REGDEF(0x00, 0x0A, 0x0976) +#define PI_WRLVL_WCKOFF_F2 DDR_REGDEF(0x10, 0x08, 0x0976) +#define PI_RDLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x097A) +#define PI_RDLVL_GATE_EN_F2 DDR_REGDEF(0x00, 0x02, 0x097B) +#define PI_RDLVL_VREF_EN_F0 DDR_REGDEF(0x10, 0x04, 0x097B) +#define PI_RDLVL_VREF_EN_F1 DDR_REGDEF(0x00, 0x04, 0x097D) +#define PI_RDLVL_VREF_EN_F2 DDR_REGDEF(0x10, 0x04, 0x097E) +#define PI_RDLAT_ADJ_F2 DDR_REGDEF(0x00, 0x09, 0x0981) +#define PI_WRLAT_ADJ_F2 DDR_REGDEF(0x00, 0x07, 0x0982) +#define PI_TDFI_CALVL_CC_F2 DDR_REGDEF(0x00, 0x0A, 0x0985) +#define PI_TDFI_CALVL_CAPTURE_F2 DDR_REGDEF(0x10, 0x0A, 0x0985) +#define PI_CALVL_EN_F2 DDR_REGDEF(0x10, 0x02, 0x0986) +#define PI_TCAENT_F2 DDR_REGDEF(0x00, 0x0E, 0x0989) +#define PI_TVREF_SHORT_F2 DDR_REGDEF(0x00, 0x0A, 0x098F) +#define PI_TVREF_LONG_F2 DDR_REGDEF(0x10, 0x0A, 0x098F) +#define PI_TVRCG_ENABLE_F2 DDR_REGDEF(0x00, 0x0A, 0x0990) +#define PI_TVRCG_DISABLE_F2 DDR_REGDEF(0x10, 0x0A, 0x0990) +#define PI_CALVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x00, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x08, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x18, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x10, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x18, 0x07, 0x0992) +#define PI_TDFI_CALVL_STROBE_F2 DDR_REGDEF(0x08, 0x04, 0x0995) +#define PI_TXP_F2 DDR_REGDEF(0x10, 0x05, 0x0995) +#define PI_TMRWCKEL_F2 DDR_REGDEF(0x18, 0x08, 0x0995) +#define PI_TCKEHDQS_F2 DDR_REGDEF(0x10, 0x06, 0x099D) +#define PI_TFC_F2 DDR_REGDEF(0x00, 0x0A, 0x099E) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x10, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x18, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x09A4) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x08, 0x07, 0x09A4) +#define PI_TDFI_WDQLVL_WR_F2 DDR_REGDEF(0x00, 0x0A, 0x09A6) +#define PI_TDFI_WDQLVL_RW_F2 DDR_REGDEF(0x10, 0x0A, 0x09A6) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x00, 0x07, 0x09A7) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x08, 0x07, 0x09A7) +#define PI_WDQLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x09A7) +#define PI_MBIST_RDLAT_ADJ_F2 DDR_REGDEF(0x08, 0x09, 0x09A8) +#define PI_MBIST_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x09A8) +#define PI_TRTP_F2 DDR_REGDEF(0x18, 0x08, 0x09B3) +#define PI_TRP_F2 DDR_REGDEF(0x00, 0x08, 0x09B4) +#define PI_TRCD_F2 DDR_REGDEF(0x08, 0x08, 0x09B4) +#define PI_TWTR_S_F2 DDR_REGDEF(0x18, 0x06, 0x09B4) +#define PI_TWTR_L_F2 DDR_REGDEF(0x00, 0x06, 0x09B5) +#define PI_TWTR_F2 DDR_REGDEF(0x10, 0x06, 0x09B5) +#define PI_TWR_F2 DDR_REGDEF(0x18, 0x08, 0x09B5) +#define PI_TRAS_MIN_F2 DDR_REGDEF(0x10, 0x09, 0x09B6) +#define PI_TDQSCK_MAX_F2 DDR_REGDEF(0x00, 0x04, 0x09B7) +#define PI_TSR_F2 DDR_REGDEF(0x10, 0x08, 0x09B7) +#define PI_TMRD_F2 DDR_REGDEF(0x18, 0x08, 0x09B7) +#define PI_TDFI_CTRLUPD_MAX_F2 DDR_REGDEF(0x00, 0x15, 0x09BC) +#define PI_TDFI_CTRLUPD_INTERVAL_F2 DDR_REGDEF(0x00, 0x20, 0x09BD) +#define PI_TINIT_F2 DDR_REGDEF(0x00, 0x18, 0x09CC) +#define PI_TINIT1_F2 DDR_REGDEF(0x00, 0x18, 0x09CD) +#define PI_TINIT3_F2 DDR_REGDEF(0x00, 0x18, 0x09CE) +#define PI_TINIT4_F2 DDR_REGDEF(0x00, 0x18, 0x09CF) +#define PI_TINIT5_F2 DDR_REGDEF(0x00, 0x18, 0x09D0) +#define PI_TXSNR_F2 DDR_REGDEF(0x00, 0x10, 0x09D1) +#define PI_TZQCAL_F2 DDR_REGDEF(0x10, 0x0C, 0x09D6) +#define PI_TZQLAT_F2 DDR_REGDEF(0x00, 0x07, 0x09D7) +#define PI_ZQRESET_F2 DDR_REGDEF(0x10, 0x0C, 0x09D8) +#define PI_TDQ72DQ_F2 DDR_REGDEF(0x10, 0x0A, 0x09DD) +#define PI_TCBTRTW_F2 DDR_REGDEF(0x00, 0x06, 0x09DE) +#define PI_MC_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x09E1) +#define PI_CKE_MUX_0 DDR_REGDEF(0x00, 0x03, 0x09E6) +#define PI_CKE_MUX_1 DDR_REGDEF(0x08, 0x03, 0x09E6) +#define PI_SEQ_DEC_SW_CS DDR_REGDEF(0x00, 0x02, 0x0A4E) +#define PI_SW_SEQ_START DDR_REGDEF(0x10, 0x01, 0x0A4E) +#define PI_SW_SEQ_0 DDR_REGDEF(0x00, 0x1B, 0x0BF1) +#define PI_SW_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0BF2) +#define PI_DFS_ENTRY_SEQ_0 DDR_REGDEF(0x00, 0x1D, 0x0BFB) +#define PI_DFS_INITIALIZATION_SEQ_1 DDR_REGDEF(0x00, 0x1D, 0x0C24) +#define PI_DFS_INITIALIZATION_SEQ_9 DDR_REGDEF(0x00, 0x1D, 0x0C2C) +#define PI_DFS_INITIALIZATION_SEQ_10 DDR_REGDEF(0x00, 0x1D, 0x0C2D) +#define PI_RDLVL_TRAIN_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0C42) +#define PI_RDLVL_TRAIN_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0C43) +#define PI_RDLVL_TRAIN_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0C44) +#define PI_RDLVL_TRAIN_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x0C45) +#define PI_RDLVL_TRAIN_SEQ_5 DDR_REGDEF(0x00, 0x1B, 0x0C46) +#define PI_SEQ_WAIT_16_F2 DDR_REGDEF(0x00, 0x18, 0x0C77) +#define PI_SEQ_WAIT_17_F2 DDR_REGDEF(0x00, 0x18, 0x0C7A) +#define PI_SEQ_WAIT_18_F2 DDR_REGDEF(0x00, 0x18, 0x0C7D) +#define PI_SEQ_WAIT_19_F2 DDR_REGDEF(0x00, 0x18, 0x0C80) +#define PI_SEQ_WAIT_20_F2 DDR_REGDEF(0x00, 0x18, 0x0C83) +#define PI_SEQ_WAIT_21_F2 DDR_REGDEF(0x00, 0x18, 0x0C86) +#define PI_SEQ_WAIT_22_F2 DDR_REGDEF(0x00, 0x18, 0x0C89) +#define PI_SEQ_WAIT_23_F2 DDR_REGDEF(0x00, 0x18, 0x0C8C) +#define PI_SEQ_WAIT_24_F2 DDR_REGDEF(0x00, 0x18, 0x0C8F) +#define PI_SEQ_WAIT_25_F2 DDR_REGDEF(0x00, 0x18, 0x0C92) +#define PI_SEQ_WAIT_26_F2 DDR_REGDEF(0x00, 0x18, 0x0C95) +#define PI_SEQ_WAIT_30_F2 DDR_REGDEF(0x00, 0x18, 0x0CA1) +#define PI_DARRAY3_0_CS0_F0 DDR_REGDEF(0x00, 0x08, 0x0D0B) +#define PI_DARRAY3_1_CS0_F0 DDR_REGDEF(0x08, 0x08, 0x0D0B) +#define PI_DARRAY3_0_CS0_F1 DDR_REGDEF(0x00, 0x08, 0x0D15) +#define PI_DARRAY3_1_CS0_F1 DDR_REGDEF(0x08, 0x08, 0x0D15) +#define PI_DARRAY3_0_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D1F) +#define PI_DARRAY3_1_CS0_F2 DDR_REGDEF(0x08, 0x08, 0x0D1F) +#define PI_DARRAY3_4_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D20) +#define PI_DARRAY3_20_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D24) +#define PI_DARRAY3_0_CS1_F0 DDR_REGDEF(0x00, 0x08, 0x0D29) +#define PI_DARRAY3_1_CS1_F0 DDR_REGDEF(0x08, 0x08, 0x0D29) +#define PI_DARRAY3_0_CS1_F1 DDR_REGDEF(0x00, 0x08, 0x0D33) +#define PI_DARRAY3_1_CS1_F1 DDR_REGDEF(0x08, 0x08, 0x0D33) +#define PI_DARRAY3_0_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3D) +#define PI_DARRAY3_1_CS1_F2 DDR_REGDEF(0x08, 0x08, 0x0D3D) +#define PI_DARRAY3_4_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3E) +#define PI_DARRAY3_20_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D42) + +/* The setting table of Data Slice for V4H */ +static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { + 0x30020370, 0x00000000, 0x01000002, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x04000100, + 0x00010000, 0x01000000, 0x00000000, 0x00000000, + 0x00010000, 0x08010000, 0x00022003, 0x00000000, + 0x040F0100, 0x1404034F, 0x04040102, 0x04040404, + 0x00000100, 0x00000000, 0x00000000, 0x000800C0, + 0x000F18FF, 0x00000000, 0x00000001, 0x00070000, + 0x0000AAAA, 0x00005555, 0x0000B5B5, 0x00004A4A, + 0x00005656, 0x0000A9A9, 0x0000A9A9, 0x0000B5B5, + 0x00000000, 0xBFBF0000, 0xCCCCF7F7, 0x00000000, + 0x00000000, 0x00000000, 0x00080815, 0x08040000, + 0x00000004, 0x00103000, 0x000C0040, 0x00200200, + 0x01010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000004, 0x001F07FF, 0x08000303, + 0x10200080, 0x00000006, 0x00000401, 0x00000000, + 0x20CEC201, 0x00000001, 0x00017706, 0x01007706, + 0x00000000, 0x008D006D, 0x00100001, 0x03FF0100, + 0x00006E01, 0x00000301, 0x00000000, 0x00000000, + 0x00000000, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x0D000050, 0x10100004, 0x06102010, + 0x61619041, 0x07097000, 0x00644180, 0x00803280, + 0x00808001, 0x13010100, 0x02000016, 0x10001003, + 0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140, + 0x00000100, 0x000001D1, 0x05000068, 0x00030402, + 0x01400000, 0x80800300, 0x00160010, 0x76543210, + 0x00000008, 0x03010301, 0x03010301, 0x03010301, + 0x03010301, 0x03010301, 0x00000000, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00070087, 0x00000000, 0x08010007, 0x00000000, + 0x20202020, 0x20202020, 0x20202020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 +}; + +/* The setting table of Address Slice for V4H */ +static const u32 DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { + 0x00200030, 0x00200002, 0x76543210, 0x00010001, + 0x06543210, 0x03070000, 0x00001000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000807F, + 0x00000001, 0x00000003, 0x00000000, 0x000F0000, + 0x030C000F, 0x00020103, 0x0000000F, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x02000400, 0x0000002A, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00200101, + 0x10002C03, 0x00000003, 0x00030240, 0x00008008, + 0x00081020, 0x01200000, 0x00010001, 0x00000000, + 0x00100302, 0x003E4208, 0x01400140, 0x01400140, + 0x01400140, 0x01400140, 0x00000100, 0x00000100, + 0x00000100, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00020580, 0x03000040, + 0x00000000 +}; + +/* The setting table of Address Control Slice for V4H */ +static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { + 0x00000000, 0x00000100, 0x00000001, 0x23800000, + 0x00000000, 0x01000101, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00040101, 0x00000000, 0x00000000, 0x00000064, + 0x00000000, 0x00000000, 0x39421B42, 0x00010124, + 0x00520052, 0x00000052, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x07030102, + 0x01030307, 0x00000054, 0x00004096, 0x08200820, + 0x08200820, 0x08200820, 0x08200820, 0x00000820, + 0x004103B8, 0x0000003F, 0x000C0006, 0x00000000, + 0x000004C0, 0x00007A12, 0x00000208, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x03000000, 0x00000000, 0x00000000, 0x04102002, + 0x00041020, 0x01C98C98, 0x3F400000, 0x003F3F3F, + 0x00000000, 0x00000000, 0x76543210, 0x00010198, + 0x00000007, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x01032380, 0x00000100, 0x00000000, 0x31421342, + 0x00308000, 0x00000080, 0x00063F77, 0x00000006, + 0x0000033F, 0x00000000, 0x0000033F, 0x00000000, + 0x0000033F, 0x00000000, 0x00033F00, 0x00CC0000, + 0x00033F77, 0x00000000, 0x00033F00, 0x00EE0000, + 0x00033F00, 0x00EE0000, 0x00033F00, 0x00EE0000, + 0x00200106 +}; + +/* The setting table of PI Register for V4H */ +static const u32 DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { + 0x00000D00, 0x00010100, 0x00640004, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0x02010000, 0x00000003, 0x00000005, + 0x00000002, 0x00000000, 0x00000101, 0x0012080E, + 0x00000000, 0x001E2C0E, 0x00000000, 0x00030300, + 0x01010700, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x01000000, 0x00002807, 0x00000000, 0x32000300, + 0x00000000, 0x00000000, 0x04022004, 0x01040100, + 0x00010000, 0x00000100, 0x000000AA, 0x00000055, + 0x000000B5, 0x0000004A, 0x00000056, 0x000000A9, + 0x000000A9, 0x000000B5, 0x00000000, 0x01000000, + 0x00030300, 0x0000001A, 0x000007D0, 0x00000300, + 0x00000000, 0x00000000, 0x01000000, 0x00000101, + 0x00000000, 0x00000000, 0x00000000, 0x00000200, + 0x03030300, 0x01000000, 0x00000000, 0x00000100, + 0x00000003, 0x001100EF, 0x01A1120B, 0x00051400, + 0x001A0700, 0x001101FC, 0x00011A00, 0x00000000, + 0x001F0000, 0x00000000, 0x00000000, 0x00051500, + 0x001103FC, 0x00011A00, 0x00051500, 0x001102FC, + 0x00011A00, 0x00001A00, 0x00000000, 0x001F0000, + 0x001100FC, 0x00011A00, 0x01A1120B, 0x001A0701, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x001100EF, 0x01A1120B, 0x00051400, 0x01910480, + 0x01821009, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001A0700, 0x01A11E14, + 0x001101FC, 0x00211A00, 0x00051500, 0x001103FC, + 0x00011A00, 0x00051500, 0x001102FC, 0x00011A00, + 0x00031A00, 0x001A0701, 0x00000000, 0x001F0000, + 0x00000000, 0x00000000, 0x01A11E14, 0x01A1120B, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100FD, 0x00012E00, + 0x00051700, 0x01A1120B, 0x001A0701, 0x001F0000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x00051400, 0x001A0700, 0x001102FD, 0x00012E00, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00070700, 0x00000000, 0x01000000, 0x00000300, + 0x17030000, 0x00000000, 0x00000000, 0x00000000, + 0x0A0A140A, 0x10020201, 0x332A0002, 0x01010000, + 0x0B000404, 0x04030308, 0x00010100, 0x02020301, + 0x01001000, 0x00000034, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x55AA55AA, 0x33CC33CC, + 0x0FF00FF0, 0x0F0FF0F0, 0x00008E38, 0x00000001, + 0x00000002, 0x00020001, 0x00020001, 0x02010201, + 0x0000000F, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xAAAAA593, + 0xA5939999, 0x00000000, 0x00005555, 0x00003333, + 0x0000CCCC, 0x00000000, 0x0003FFFF, 0x00003333, + 0x0000CCCC, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01180400, + 0x03020100, 0x00060504, 0x00010100, 0x00000008, + 0x00080000, 0x00000001, 0x00000000, 0x0001AA00, + 0x00000100, 0x00000000, 0x00010000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00020000, 0x00000100, 0x00010000, 0x0000000B, + 0x0000001C, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x03010000, 0x01000100, + 0x01020001, 0x00010300, 0x05000104, 0x01060001, + 0x00010700, 0x00000000, 0x00000000, 0x00010000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000301, 0x00000000, 0x00000000, 0x01010000, + 0x00000000, 0x00000200, 0x00000000, 0xB8000000, + 0x010000FF, 0x0000FFE8, 0x00FFA801, 0xFFD80100, + 0x00007F10, 0x00000000, 0x00000034, 0x0000003D, + 0x00020079, 0x02000200, 0x02000204, 0x06000C06, + 0x04040200, 0x04100804, 0x14090004, 0x1C081024, + 0x0000120C, 0x00000015, 0x000000CF, 0x00000026, + 0x0000017F, 0x00000130, 0x04000C2E, 0x00000404, + 0x01080032, 0x01080032, 0x000F0032, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x00010301, + 0x03030000, 0x00000001, 0x00010303, 0x00030000, + 0x0013000C, 0x0A060037, 0x03030526, 0x000C0032, + 0x0017003D, 0x0025004B, 0x00010101, 0x0000000E, + 0x00000019, 0x010000C8, 0x000F000F, 0x0007000C, + 0x001A0100, 0x0015001A, 0x0100000B, 0x00C900C9, + 0x005100A1, 0x29003329, 0x33290033, 0x0A070600, + 0x0A07060D, 0x0D09070D, 0x000C000D, 0x00001000, + 0x00000C00, 0x00001000, 0x00000C00, 0x02001000, + 0x0002000E, 0x00160019, 0x1E1A00C8, 0x00100004, + 0x361C0008, 0x00000000, 0x0000000C, 0x0006000C, + 0x0300361C, 0x04001300, 0x000D0019, 0x0000361C, + 0x20003300, 0x00000000, 0x02000000, 0x04040802, + 0x00060404, 0x0003C34F, 0x05022001, 0x0203000A, + 0x04040408, 0xC34F0604, 0x10010005, 0x040A0502, + 0x0A080F11, 0x1C0A040A, 0x0022C34F, 0x0C0C1002, + 0x00019E0A, 0x0000102C, 0x000002FE, 0x00001DEC, + 0x0000185C, 0x0000F398, 0x04000400, 0x03030400, + 0x002AF803, 0x00002AF8, 0x0000D6D7, 0x00000003, + 0x0000006E, 0x00000016, 0x00004E20, 0x00004E20, + 0x00030D40, 0x00000005, 0x000000C8, 0x00000027, + 0x00027100, 0x00027100, 0x00186A00, 0x00000028, + 0x00000640, 0x01000136, 0x00530040, 0x00010004, + 0x00960040, 0x00010004, 0x04B00040, 0x00000318, + 0x00280005, 0x05040404, 0x00070603, 0x06030503, + 0x0503000D, 0x00640603, 0x06040608, 0x00040604, + 0x00260015, 0x01050130, 0x01000100, 0x00020201, + 0x04040000, 0x01010104, 0x03020302, 0x00000100, + 0x02020101, 0x00000000, 0x09910260, 0x11911600, + 0x19A21009, 0x19A10100, 0x19A10201, 0x19A10302, + 0x19A10A03, 0x19A10B04, 0x19A10C05, 0x19A10E07, + 0x19A10F08, 0x19A1110A, 0x19A1120B, 0x19A1130C, + 0x19A1140D, 0x19A00C00, 0x199F0000, 0x199F0000, + 0x199F0000, 0x199F0000, 0x01910300, 0x01A21009, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x001140BF, 0x01811009, 0x01850400, 0x01A10C05, + 0x01850300, 0x01A10C11, 0x01850300, 0x001100BF, + 0x01811009, 0x01850500, 0x019F0000, 0x019F0000, + 0x01510001, 0x01D102A0, 0x01E21009, 0x00051900, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x01510001, + 0x01D10290, 0x01E21009, 0x01510001, 0x01D10000, + 0x01E21009, 0x00051800, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x0011008F, 0x00910000, + 0x01811009, 0x01910040, 0x01A21009, 0x019F0000, + 0x01911000, 0x01A21009, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x01A10C05, + 0x01A10E07, 0x01A10F08, 0x01A1110A, 0x01A1120B, + 0x01A1130C, 0x01A1140D, 0x01A00C00, 0x01910800, + 0x01A21009, 0x019F0000, 0x019F0000, 0x019F0000, + 0x0101017F, 0x00010101, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x01000101, + 0x00000000, 0x00000000, 0x00050000, 0x00070100, + 0x000F0200, 0x00000000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A00B04, 0x00210D06, 0x01A1110A, + 0x01A1140D, 0x00098000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x00210D06, + 0x01A1110A, 0x00000000, 0x01A1140D, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x000A0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x000A0000, 0x01061300, + 0x00000000, 0x00000000, 0x00061180, 0x000612C0, + 0x00000000, 0x00000000, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01811009, 0x0011EFAF, + 0x01A1120B, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001100BF, + 0x01A1120B, 0x080D0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x080C0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x001F0000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00211F14, 0x00212014, + 0x00212116, 0x00212217, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x001A85FF, 0x00051E00, 0x001F0000, 0x00000000, + 0x00211F14, 0x00212015, 0x00212116, 0x00212217, + 0x01A1120B, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x08084340, 0x0011FFFF, + 0x2011FFFB, 0x00012E00, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x083E4340, 0x00212E00, + 0x01A1120B, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x08201020, + 0x28100020, 0x08083020, 0x08400020, 0x08402020, + 0x08483020, 0x10083020, 0x20180020, 0x30480020, + 0x78880020, 0x488010E0, 0x494B0000, 0x49089080, + 0x49080000, 0x490011C0, 0x0A000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x001100FF, 0x01810302, 0x001100DF, 0x00010D06, + 0x001100EF, 0x01A1120B, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x00010D06, 0x01810302, 0x0181160E, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x081A52FD, 0x001A12FF, + 0x00051A00, 0x001A13FF, 0x00051B00, 0x001F13FF, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x00032300, 0x00032400, + 0x001F0000, 0x001F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x081100DF, 0x08010D06, + 0x0011000F, 0x0181160E, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x009C0000, + 0x08010D06, 0x0181160E, 0x01A1120B, 0x001F0000, + 0x001F0000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x11910048, + 0x09910060, 0x19A21009, 0x19A10100, 0x19A10201, + 0x19A10302, 0x19A10A03, 0x19A10B04, 0x18051C00, + 0x19A1110A, 0x19A1120B, 0x19A1130C, 0x19A1140D, + 0x19A1160E, 0x181140BF, 0x19A11009, 0x19A10C05, + 0x19A00C00, 0x19A10E07, 0x19A10F08, 0x19910280, + 0x19A21009, 0x18051000, 0x18861101, 0x181F0000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18861100, + 0x19A11009, 0x101B0001, 0x181B0100, 0x18000500, + 0x181B0200, 0x00000000, 0x181B0600, 0x181B0C00, + 0x181B0100, 0x181B0200, 0x181B0300, 0x181B0400, + 0x181F0000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x004B1040, 0x001011C0, 0x00089080, + 0x000811C0, 0x040811C0, 0x02000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x5F407FAA, + 0x007B776F, 0x4AB555AA, 0xB5A9A956, 0x9F80BFAA, + 0x00BBB7AF, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00002AF8, 0x0000D6D7, 0x0000006E, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000000E, 0x00000019, 0x000000C8, + 0x00000001, 0x00000001, 0x00000003, 0x00000007, + 0x00000007, 0x00000009, 0x00000001, 0x00000001, + 0x00000003, 0x00000001, 0x00000001, 0x00000003, + 0x0000006E, 0x000000C8, 0x00000640, 0x00000001, + 0x00000001, 0x00000003, 0x00000002, 0x00000004, + 0x0000001C, 0x00000007, 0x0000000B, 0x00000051, + 0x0000000C, 0x00000015, 0x000000A1, 0x00000003, + 0x00000000, 0x0000000C, 0x00000000, 0x00000000, + 0x00000000, 0x0000000F, 0x0000000F, 0x0000000F, + 0x00002AF9, 0x00002AF9, 0x00002AF9, 0x00000034, + 0x0000001E, 0x0000003C, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000000C0, 0x00000000, 0x00000000, 0x55550000, + 0x00003C5A, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00D60000, + 0x50005000, 0x803E0050, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C61110, 0x2C002834, 0x0C06002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C6BBB0, + 0x2C002834, 0x0C06002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00D60000, 0x50005000, 0x803E0050, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C61110, + 0x2C002834, 0x082E002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C6BBB0, 0x2C002834, 0x082E002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x80808080, + 0x800D8080, 0x80808080, 0x17808080, 0x80808025, + 0x2221201F, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x0A030201, + 0x0E800C0B, 0x1211100F, 0x80161413, 0x08004C80, + 0x8080801E, 0x80804E80, 0x80808080, 0x80808080, + 0x80808080 +}; + +struct dbsc5_table_patch { + const u32 reg; + const u32 val; +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3200[] = { + { PHY_REGULATOR_EN_CNT, 0x10 }, + { PHY_RX_CAL_ALL_DLY, 0x07 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x08 }, + { PHY_RDDATA_EN_OE_DLY, 0x0B }, + { PHY_RPTR_UPDATE, 0x07 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x25 }, + { PHY_RDLVL_MAX_EDGE, 0x012D }, + { PHY_RDDATA_EN_DLY, 0x0B }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x05 }, + { PHY_GTLVL_LAT_ADJ_START, 0x03 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3200[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3200[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57 }, + { PI_TREF_F2, 0x613 }, + { PI_TDFI_WRLVL_WW_F0, 0x2B }, + { PI_TDFI_WRLVL_WW_F1, 0x2B }, + { PI_TDFI_WRLVL_WW_F2, 0x2B }, + { PI_RDLAT_ADJ_F2, 0x22 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1D }, + { PI_TDFI_CALVL_CC_F2, 0x43 }, + { PI_TVRCG_ENABLE_F2, 0x51 }, + { PI_TVRCG_DISABLE_F2, 0x29 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x64 }, + { PI_TCKEHDQS_F2, 0x12 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x10 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x1E }, + { PI_TWTR_S_F2, 0x05 }, + { PI_TWTR_L_F2, 0x05 }, + { PI_TWTR_F2, 0x05 }, + { PI_TWR_F2, 0x0E }, + { PI_TDQSCK_MAX_F2, 0x01 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0C26 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797C }, + { PI_TXSNR_F2, 0x9B }, + { PI_ZQRESET_F2, 0x0014 }, + { PI_TCBTRTW_F2, 0x04 }, + { PI_SEQ_WAIT_16_F2, 0x000064 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x000320 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x00000E }, + { PI_SEQ_WAIT_24_F2, 0x000029 }, + { PI_SEQ_WAIT_25_F2, 0x000051 }, + { PI_SEQ_WAIT_26_F2, 0x000003 }, + { PI_SEQ_WAIT_30_F2, 0x00002B }, + { PI_WRDCM_LVL_EN_F1, 0x00 }, + { PI_WRDCM_LVL_EN_F2, 0x00 }, + { PI_DRAMDCA_LVL_EN_F1, 0x00 }, + { PI_DRAMDCA_LVL_EN_F2, 0x00 }, + { PI_TINIT_F2, 0x013880 }, + { PI_TINIT1_F2, 0x013880 }, + { PI_TINIT3_F2, 0x0C3500 }, + { PI_TINIT4_F2, 0x000014 }, + { PI_TINIT5_F2, 0x000320 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3733[] = { + { PHY_REGULATOR_EN_CNT, 0x13 }, + { PHY_RX_CAL_ALL_DLY, 0x08 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0A }, + { PHY_RDDATA_EN_OE_DLY, 0x0D }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2A }, + { PHY_RDLVL_MAX_EDGE, 0x0149 }, + { PHY_RDDATA_EN_DLY, 0x0D }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x9C }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3733[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3733[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5B }, + { PI_TREF_F2, 0x717 }, + { PI_TDFI_WRLVL_WW_F0, 0x2C }, + { PI_TDFI_WRLVL_WW_F1, 0x2C }, + { PI_TDFI_WRLVL_WW_F2, 0x2C }, + { PI_RDLAT_ADJ_F2, 0x24 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1F }, + { PI_TDFI_CALVL_CC_F2, 0x45 }, + { PI_TVRCG_ENABLE_F2, 0x5F }, + { PI_TVRCG_DISABLE_F2, 0x30 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x75 }, + { PI_TCKEHDQS_F2, 0x13 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x12 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x20 }, + { PI_TWTR_S_F2, 0x06 }, + { PI_TWTR_L_F2, 0x06 }, + { PI_TWTR_F2, 0x06 }, + { PI_TWR_F2, 0x10 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0E2E }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCC }, + { PI_TXSNR_F2, 0xB5 }, + { PI_ZQRESET_F2, 0x0018 }, + { PI_TCBTRTW_F2, 0x05 }, + { PI_SEQ_WAIT_16_F2, 0x000075 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0003A6 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000011 }, + { PI_SEQ_WAIT_24_F2, 0x000030 }, + { PI_SEQ_WAIT_25_F2, 0x00005F }, + { PI_SEQ_WAIT_26_F2, 0x000005 }, + { PI_SEQ_WAIT_30_F2, 0x00002D }, + { PI_TINIT_F2, 0x016C90 }, + { PI_TINIT1_F2, 0x016C90 }, + { PI_TINIT3_F2, 0x0E3D98 }, + { PI_TINIT4_F2, 0x000018 }, + { PI_TINIT5_F2, 0x0003A6 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4266[] = { + { PHY_REGULATOR_EN_CNT, 0x16 }, + { PHY_RX_CAL_ALL_DLY, 0x09 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0B }, + { PHY_RDDATA_EN_OE_DLY, 0x0E }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2E }, + { PHY_RDLVL_MAX_EDGE, 0x0164 }, + { PHY_RDDATA_EN_DLY, 0x0E }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x30 }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4266[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4266[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64 }, + { PI_TREF_F2, 0x81C }, + { PI_TDFI_WRLVL_WW_F0, 0x2D }, + { PI_TDFI_WRLVL_WW_F1, 0x2D }, + { PI_TDFI_WRLVL_WW_F2, 0x2D }, + { PI_RDLAT_ADJ_F2, 0x2B }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x20 }, + { PI_TDFI_CALVL_CC_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x6C }, + { PI_TVRCG_DISABLE_F2, 0x37 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TFC_F2, 0x86 }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x13 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x27 }, + { PI_TWTR_S_F2, 0x07 }, + { PI_TWTR_L_F2, 0x07 }, + { PI_TWTR_F2, 0x07 }, + { PI_TWR_F2, 0x13 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1038 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230 }, + { PI_TXSNR_F2, 0xCF }, + { PI_ZQRESET_F2, 0x001B }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000086 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x00042B }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000013 }, + { PI_SEQ_WAIT_24_F2, 0x000037 }, + { PI_SEQ_WAIT_25_F2, 0x00006C }, + { PI_SEQ_WAIT_26_F2, 0x000006 }, + { PI_SEQ_WAIT_30_F2, 0x000032 }, + { PI_TINIT_F2, 0x01A0AB }, + { PI_TINIT1_F2, 0x01A0AB }, + { PI_TINIT3_F2, 0x1046AB }, + { PI_TINIT4_F2, 0x00001B }, + { PI_TINIT5_F2, 0x00042B } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4800[] = { + { PHY_REGULATOR_EN_CNT, 0x18 }, + { PHY_RX_CAL_ALL_DLY, 0x0A }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0D }, + { PHY_RDDATA_EN_OE_DLY, 0x10 }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x31 }, + { PHY_RDLVL_MAX_EDGE, 0x017F }, + { PHY_RDDATA_EN_DLY, 0x10 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6 }, + { PHY_GTLVL_LAT_ADJ_START, 0x05 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4800[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4800[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68 }, + { PI_RDLAT_ADJ_F2, 0x2D }, + { PI_TREF_F2, 0x920 }, + { PI_TDFI_WRLVL_WW_F0, 0x2E }, + { PI_TDFI_WRLVL_WW_F1, 0x2E }, + { PI_TDFI_WRLVL_WW_F2, 0x2E }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x21 }, + { PI_TDFI_CALVL_CC_F2, 0x47 }, + { PI_TVRCG_DISABLE_F2, 0x3D }, + { PI_TVRCG_ENABLE_F2, 0x79 }, + { PI_TXP_F2, 0x08 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TFC_F2, 0x96 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x15 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x29 }, + { PI_TWTR_S_F2, 0x08 }, + { PI_TWR_F2, 0x15 }, + { PI_TWTR_F2, 0x08 }, + { PI_TWTR_L_F2, 0x08 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1240 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680 }, + { PI_TXSNR_F2, 0x0E9 }, + { PI_ZQRESET_F2, 0x001E }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000096 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000008 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0004B0 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000015 }, + { PI_SEQ_WAIT_24_F2, 0x00003D }, + { PI_SEQ_WAIT_25_F2, 0x000079 }, + { PI_SEQ_WAIT_26_F2, 0x000008 }, + { PI_SEQ_WAIT_30_F2, 0x000034 }, + { PI_TINIT_F2, 0x01D4A9 }, + { PI_TINIT1_F2, 0x01D4A9 }, + { PI_TINIT3_F2, 0x124E91 }, + { PI_TINIT4_F2, 0x00001E }, + { PI_TINIT5_F2, 0x0004B0 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_5500[] = { + { PHY_REGULATOR_EN_CNT, 0x1C }, + { PHY_RX_CAL_ALL_DLY, 0x0C }, + { PHY_RDDATA_EN_TSEL_DLY, 0x10 }, + { PHY_RDDATA_EN_OE_DLY, 0x13 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x37 }, + { PHY_RDLVL_MAX_EDGE, 0x01A3 }, + { PHY_RDDATA_EN_DLY, 0x13 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x06 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x8F }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_5500[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_5500[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71 }, + { PI_RDLAT_ADJ_F2, 0x32 }, + { PI_TREF_F2, 0xA79 }, + { PI_TDFI_WRLVL_WW_F0, 0x30 }, + { PI_TDFI_WRLVL_WW_F1, 0x30 }, + { PI_TDFI_WRLVL_WW_F2, 0x30 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x23 }, + { PI_TDFI_CALVL_CC_F2, 0x49 }, + { PI_TVRCG_DISABLE_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x8B }, + { PI_TMRWCKEL_F2, 0x0B }, + { PI_TCKEHDQS_F2, 0x15 }, + { PI_TFC_F2, 0xAD }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_TDFI_WDQLVL_WR_F2, 0x17 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x2E }, + { PI_TWTR_S_F2, 0x09 }, + { PI_TWR_F2, 0x18 }, + { PI_TWTR_F2, 0x09 }, + { PI_TWTR_L_F2, 0x09 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x14F2 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174 }, + { PI_TXSNR_F2, 0x10B }, + { PI_ZQRESET_F2, 0x0023 }, + { PI_TCBTRTW_F2, 0x07 }, + { PI_SEQ_WAIT_16_F2, 0x0000AD }, + { PI_SEQ_WAIT_21_F2, 0x000561 }, + { PI_SEQ_WAIT_23_F2, 0x000019 }, + { PI_SEQ_WAIT_24_F2, 0x000046 }, + { PI_SEQ_WAIT_25_F2, 0x00008B }, + { PI_SEQ_WAIT_26_F2, 0x00000A }, + { PI_SEQ_WAIT_30_F2, 0x000038 }, + { PI_TINIT_F2, 0x0219AF }, + { PI_TINIT1_F2, 0x0219AF }, + { PI_TINIT3_F2, 0x1500CF }, + { PI_TINIT4_F2, 0x000023 }, + { PI_TINIT5_F2, 0x000561 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_6000[] = { + { PHY_REGULATOR_EN_CNT, 0x1F }, + { PHY_RDDATA_EN_TSEL_DLY, 0x12 }, + { PHY_RDDATA_EN_OE_DLY, 0x15 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x3A }, + { PHY_RDLVL_MAX_EDGE, 0x01BD }, + { PHY_RDDATA_EN_DLY, 0x15 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x07 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x1B }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_6000[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_6000[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75 }, + { PI_RDLAT_ADJ_F2, 0x34 }, + { PI_TREF_F2, 0xB6B }, + { PI_TDFI_WRLVL_WW_F0, 0x31 }, + { PI_TDFI_WRLVL_WW_F1, 0x31 }, + { PI_TDFI_WRLVL_WW_F2, 0x31 }, + { PI_TVRCG_DISABLE_F2, 0x4D }, + { PI_TVRCG_ENABLE_F2, 0x98 }, + { PI_TMRWCKEL_F2, 0x0C }, + { PI_TFC_F2, 0xBC }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x30 }, + { PI_TWR_F2, 0x1A }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x16D6 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45C }, + { PI_TXSNR_F2, 0x123 }, + { PI_ZQRESET_F2, 0x0026 }, + { PI_SEQ_WAIT_16_F2, 0x0000BC }, + { PI_SEQ_WAIT_21_F2, 0x0005DD }, + { PI_SEQ_WAIT_23_F2, 0x00001B }, + { PI_SEQ_WAIT_24_F2, 0x00004D }, + { PI_SEQ_WAIT_25_F2, 0x000098 }, + { PI_SEQ_WAIT_30_F2, 0x00003A }, + { PI_TINIT_F2, 0x024A16 }, + { PI_TINIT1_F2, 0x024A16 }, + { PI_TINIT3_F2, 0x16E4D8 }, + { PI_TINIT4_F2, 0x000026 }, + { PI_TINIT5_F2, 0x0005DD } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_640 = { + PHY_DATA_DC_CAL_CLK_SEL, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_mbpsdiv_640 = { + PHY_CLK_DC_CAL_CLK_SEL, 0x04 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_640 = { + PHY_CAL_CLK_SELECT_0, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = { + PHY_RX_PCLK_CLK_SEL, 0x3 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = { + PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = { + { PHY_PLL_CTRL, 0x1542 }, + { PHY_PLL_CTRL_8X, 0x3342 } +}; + +/* Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set */ +static const u32 PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_0_CS0_F0, PI_DARRAY3_0_CS0_F1, PI_DARRAY3_0_CS0_F2 }, + { PI_DARRAY3_0_CS1_F0, PI_DARRAY3_0_CS1_F1, PI_DARRAY3_0_CS1_F2 } +}; + +/* Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set */ +static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_1_CS0_F0, PI_DARRAY3_1_CS0_F1, PI_DARRAY3_1_CS0_F2 }, + { PI_DARRAY3_1_CS1_F0, PI_DARRAY3_1_CS1_F1, PI_DARRAY3_1_CS1_F2 } +}; + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0x0 +#define DBSC_DBSYSCONF1 0x0 +#define DBSC_DBSYSCONF1A 0x4 +#define DBSC_DBSYSCONF2 0x4 +#define DBSC_DBPHYCONF0 0x8 +#define DBSC_DBSYSCONF2A 0x8 +#define DBSC_DBMEMKIND 0x20 +#define DBSC_DBMEMKINDA 0x20 +#define DBSC_DBMEMCONF(ch, cs) (0x30 + (0x2000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBMEMCONFA(ch, cs) (0x30 + (0x4000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBSYSCNT0 0x100 +#define DBSC_DBSYSCNT0A 0x100 +#define DBSC_DBACEN 0x200 +#define DBSC_DBRFEN 0x204 +#define DBSC_DBCMD 0x208 +#define DBSC_DBWAIT 0x210 +#define DBSC_DBBL 0x400 +#define DBSC_DBBLA 0x400 +#define DBSC_DBRFCNF1 0x414 +#define DBSC_DBRFCNF2 0x418 +#define DBSC_DBCALCNF 0x424 +#define DBSC_DBDBICNT 0x518 +#define DBSC_DBDFIPMSTRCNF 0x520 +#define DBSC_DBDFICUPDCNF 0x540 +#define DBSC_DBBCAMDIS 0x9FC +#define DBSC_DBSCHRW1 0x1024 +#define DBSC_DBSCHTR0 0x1030 +#define DBSC_DBTR(x) (0x300 + (0x4 * (x))) +#define DBSC_DBRNK(x) (0x430 + (0x4 * (x))) +#define DBSC_DBDFISTAT(ch) (0x600 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBDFICNT(ch) (0x604 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDCNT2(ch) (0x618 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDLK(ch) (0x620 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGA(ch) (0x624 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGD(ch) (0x628 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGM(ch) (0x62C + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT0(ch) (0x630 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT1(ch) (0x634 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBSCHFCTST0 0x1040 +#define DBSC_DBSCHFCTST1 0x1044 + +/* CPG PLL3 registers */ +#define CPG_CPGWPR 0x0 +#define CPG_FRQCRD0 0x80C +#define CPG_PLLECR 0x820 +#define CPG_PLL3CR0 0x83C +#define CPG_PLL3CR1 0x8C0 +#define CPG_FSRCHKCLRR4 0x590 +#define CPG_FSRCHKSETR4 0x510 +#define CPG_FSRCHKRA4 0x410 +#define CPG_SRCR4 0x2C10 +#define CPG_SRSTCLR4 0x2C90 + +#define CPG_FRQCRD_KICK_BIT BIT(31) +#define CPG_PLL3CR0_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) + +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +struct renesas_dbsc5_board_config { + /* Channels in use */ + u8 bdcfg_phyvalid; + /* Read vref (SoC) training range */ + u32 bdcfg_vref_r; + /* Write vref (MR14, MR15) training range */ + u16 bdcfg_vref_w; + /* CA vref (MR12) training range */ + u16 bdcfg_vref_ca; + /* RFM required check */ + bool bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + u8 bdcfg_cs_swap; + } ch[4]; +}; + +struct renesas_dbsc5_dram_priv { + void __iomem *regs; + void __iomem *cpg_regs; + + /* The board parameter structure of the board */ + const struct renesas_dbsc5_board_config *dbsc5_board_config; + + /* The board clock frequency */ + u32 brd_clk; + u32 brd_clkdiv; + u32 brd_clkdiva; + + /* The Mbps of Bus */ + u32 bus_clk; + u32 bus_clkdiv; + + /* The Mbps of DDR */ + u32 ddr_mbps; + u32 ddr_mbpsdiv; + + /* DDR memory multiplier setting value */ + u32 ddr_mul; + u32 ddr_mul_nf; + u32 ddr_mul_low; + u32 ddr_mul_reg; + + /* Value indicating the enabled channel */ + u32 ddr_phyvalid; + + /* The tccd value of DDR */ + u32 ddr_tccd; + + /* Memory capacity in each channel and each CS */ + u8 ddr_density[DRAM_CH_CNT][CS_CNT]; + /* Channels used for each memory rank */ + u32 ch_have_this_cs[CS_CNT]; + /* The maximum memory capacity */ + u32 max_density; + + /* Index of jedec spec1 setting table you use */ + u32 js1_ind; + /* Array of jedec spec2 setting table */ + u32 js2[JS2_CNT]; + /* Read latency */ + u32 RL; + /* Write latency */ + u32 WL; + + /* Array for DDR PI Slice settings */ + u32 DDR_PI_REGSET[DDR_PI_REGSET_NUM_V4H]; + /* Array for DDRPHY Slice settings */ + u32 DDR_PHY_SLICE_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS VALUE Slice settings */ + u32 DDR_PHY_ADR_V_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS CONTROL Slice settings */ + u32 DDR_PHY_ADR_G_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; +}; + +static const struct renesas_dbsc5_board_config renesas_v4h_dbsc5_board_config = { + /* RENESAS V4H White Hawk (64Gbit 1rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26147085, 0x12306845 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02341065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x71048365 }, + .bdcfg_dm_swap = { 0x00, 0x02 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264071, 0x41207536 }, + .bdcfg_dm_swap = { 0x03, 0x08 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x62801745 }, + .bdcfg_dm_swap = { 0x00, 0x03 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +/** + * r_vch_nxt() - Macro for channel selection loop + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 r_vch_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + int posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + if (priv->ddr_phyvalid & BIT(posn)) + break; + + return posn; +} + +/* Select only valid channels in all channels from CH0. */ +#define r_foreach_vch(dev, ch) \ +for ((ch) = r_vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = r_vch_nxt((dev), (ch) + 1)) + +/* All channels are selected. */ +#define r_foreach_ech(ch) \ +for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/** + * dbsc5_clk_cpg_write_32() - Write clock control register + * + * Write the complement value of setting value to the CPG_CPGWPR register + * for releaseing the protect. Write setting value to destination address. + */ +static void dbsc5_clk_cpg_write_32(struct udevice *dev, void __iomem *a, u32 v) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + writel(~v, priv->cpg_regs + CPG_CPGWPR); + writel(v, a); +} + +enum dbsc5_clk_pll3_mode { + PLL3_LOW_FREQUENCY_MODE = 0, + PLL3_HIGH_FREQUENCY_MODE, + PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER +}; + +/** + * dbsc5_clk_pll3_control() - Set PLL3 + * @dev: DBSC5 device + * @mode: PLL3 frequency mode + * + * Determine the set value according to the frequency mode of the argument. + * Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one. + * Reflect settings + */ +static void dbsc5_clk_pll3_control(struct udevice *dev, u32 mode) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 data_div, data_mul, data_nf, ssmode, val; + int ret; + + /* + * PLL3VCO = EXTAL * priv->ddr_mul * 1/2 + * clk_ctlr_sync = PLL3VCO * pll3_div + * priv->ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 + */ + + switch (mode) { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + data_mul = (priv->ddr_mul_low / 2) - 1; /* PLL3VCO = 1600MHz */ + data_div = 0x9; /* div = 32 */ + data_nf = 0x0; + ssmode = 0x0; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + data_mul = (priv->ddr_mul / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = priv->ddr_mul_nf; + ssmode = 0x4; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + data_mul = (priv->ddr_mul_reg / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = 0x0; + ssmode = 0x4; + break; + default: + printf("%s Mode %d not supported\n", __func__, mode); + hang(); + } + + data_mul = (data_mul << 20) | (ssmode << 16); + data_nf = data_nf << 21; + + if (((readl(priv->cpg_regs + CPG_PLL3CR0) & 0x3FFFFF7F) != data_mul) || + (readl(priv->cpg_regs + CPG_PLL3CR1) != data_nf)) { + /* PLL3CR0 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, data_mul); + /* PLL3CR1 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR1, data_nf); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, + readl(priv->cpg_regs + CPG_PLL3CR0) | + CPG_PLL3CR0_KICK_BIT); + + ret = readl_poll_timeout(priv->cpg_regs + CPG_PLLECR, val, + (val & CPG_PLLECR_PLL3ST_BIT), + 1000000); + if (ret < 0) { + printf("%s CPG_PLLECR bit CPG_PLLECR_PLL3ST_BIT timeout\n", __func__); + hang(); + } + } + + /* PLL3 DIV set(Target value) */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT div set timeout\n", __func__); + hang(); + } + + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + (readl(priv->cpg_regs + CPG_FRQCRD0) & 0xFFFFFFF0) | + data_div); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + readl(priv->cpg_regs + CPG_FRQCRD0) | + CPG_FRQCRD_KICK_BIT); + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_clk_wait_freqchgreq() - Training handshake functions + * + * Check the value of the argument req_assert. If req_assert is 1, wait until + * FREQCHGREQ of all channels is 1 before time expires. If req_assert is 0, + * wait until FREQCHGREQ of all channels is 0 before time expires. Return the + * result of whether time has expired or not as a return value. + */ +static u32 dbsc5_clk_wait_freqchgreq(struct udevice *dev, u32 req_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 count = 0xFFFFFF; + u32 ch, reg; + + do { + reg = !!req_assert; + r_foreach_vch(dev, ch) + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); + count = count - 1; + } while (((reg & 0x1) != !!req_assert) && (count != 0)); + + return count == 0x0; +} + +/** + * dbsc5_clk_set_freqchgack() - Training handshake functions + * @dev: DBSC5 device + * @ack_assert: Select DBSC_DBPDCNT2 content + * + * Check the value of the argument ackassert. If the value of ackassert + * is greater than or equal to 0, write 0xCF01 to DBSC_DBPDCNT2. + * If the value of ackassert is 0, write 0x0 to DBSC_DBPDCNT2. + */ +static void dbsc5_clk_set_freqchgack(struct udevice *dev, u32 ack_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const u32 reg = ack_assert ? 0xcf01 : 0x0; + u32 ch; + + r_foreach_vch(dev, ch) + writel(reg, regs_dbsc_d + DBSC_DBPDCNT2(ch)); +} + +/** + * dbsc5_clk_wait_dbpdstat1() - Wait for status register update + * @dev: DBSC5 device + * @status: Expected status + * + * Read value the DBSC_DBPDSTAT1(ch) register. Wait until the contents + * of the status register are the same as status. + */ +static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 i, ch, reg; + + for (i = 0; i < 2; i++) { + do { + reg = status; + r_foreach_vch(dev, ch) + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch)); + } while (reg != status); + } +} + +/** + * dbsc5_clk_pll3_freq() - Set up the pll3 frequency + * @dev: DBSC5 device + * + * Wait for frequency change request. DBSC_DBPDSTAT0 value determines whether + * dbsc5_clk_pll3_control is called in low frequency mode or high frequency + * mode. Call dbsc5_clk_set_freqchgack(1) function. Check update completion until + * timeout. Call dbsc5_clk_set_freqchgack(0) function. If timed out, return with + * error log Wait for status register update. + */ +static int dbsc5_clk_pll3_freq(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 fsel, timeout; + + dbsc5_clk_wait_freqchgreq(dev, 1); + + fsel = (readl(regs_dbsc_d + DBSC_DBPDSTAT0(0)) & 0x300) >> 8; + dbsc5_clk_pll3_control(dev, fsel ? PLL3_HIGH_FREQUENCY_MODE : + PLL3_LOW_FREQUENCY_MODE); + + dbsc5_clk_set_freqchgack(dev, 1); + timeout = dbsc5_clk_wait_freqchgreq(dev, 0); + dbsc5_clk_set_freqchgack(dev, 0); + + if (timeout) { + printf("Time out\n"); + return -ETIMEDOUT; + } + + dbsc5_clk_wait_dbpdstat1(dev, 0x7); + + return 0; +} + +/** + * dbsc5_reg_write() - Write DBSC register + * @addr: Destination address + * @data: Setting value to be written + * + * Write 32bit value @data to register at @addr . + */ +static void dbsc5_reg_write(void __iomem *addr, u32 data) +{ + writel(data, addr); + + if (((uintptr_t)addr & 0x000A0000) == 0x000A0000) + writel(data, addr + 0x4000); + else + writel(data, addr + 0x8000); +} + +/** + * dbsc5_reg_write() - DRAM Command Write Access + * @dev: DBSC5 device + * @cmd DRAM command. + * + * First, execute the dummy read to DBSC_DBCMD. + * Confirm that no DBSC command operation is in progress 0. + * Write the contents of the command to be sent to DRAM. + */ +static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + /* dummy read */ + readl(regs_dbsc_d + DBSC_DBCMD); + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT bit 0 timeout\n", __func__); + hang(); + } + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__); + hang(); + } + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd); +} + +/** + * dbsc5_reg_ddrphy_read() - Read setting from DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * + * Write matching values to DBPDRGA register and read value out of DBSC_DBPDRGD. + * Wait until the write process completed in each step. + */ +static u32 dbsc5_reg_ddrphy_read(struct udevice *dev, u32 ch, u32 regadd) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd | BIT(14), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15) | BIT(14))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + val = readl(regs_dbsc_d + DBSC_DBPDRGA(ch)); + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) again timeout\n", __func__); + hang(); + } + + return readl(regs_dbsc_d + DBSC_DBPDRGD(ch)); +} + +/** + * dbsc5_reg_ddrphy_write(dev, ) - Write setting to DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * + * Write matching values to DBPDRGA, DBPDRGD, DBPDRGA, DBPDRGA registers. + * Wait until the write process completed in each step. + */ +static void dbsc5_reg_ddrphy_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + writel(regdata, regs_dbsc_d + DBSC_DBPDRGD(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGD timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); +} + +/* + * dbsc5_reg_ddrphy_write_all() - Write setting from DDR PHY register for all channels + * @dev: DBSC5 device + * @regadd: Destination address + * @regdata: Value to be written + * + * Wrapper around dbsc5_reg_ddrphy_write() for all channels. + */ +static void dbsc5_reg_ddrphy_write_all(struct udevice *dev, u32 regadd, u32 regdata) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); +} + +/** + * dbsc5_reg_ddrphy_masked_write() - Write setting to DDR PHY register with mask + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * @msk: Register mask + * + * Wrapper around dbsc5_reg_ddrphy_write() with DBPDRGM set. + */ +static void dbsc5_reg_ddrphy_masked_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata, u32 msk) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(msk, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == msk), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM timeout\n", __func__); + hang(); + } + + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); + + writel(0, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == 0), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM != 0 timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_ddr_setval_slice() - Write setting to DDR PHY hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Calculate the bit field in which to write the setting value + * from encoded register and bitfield @regdef parameter. Call + * dbsc5_reg_ddrphy_masked_write() to write the value to hardware. + */ +static void dbsc5_ddr_setval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef, u32 val) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + const u32 dms = ~((!!(msk & BIT(24)) << 3) | (!!(msk & BIT(16)) << 2) | + (!!(msk & BIT(8)) << 1) | !!(msk & BIT(0))) & 0xf; + + dbsc5_reg_ddrphy_masked_write(dev, ch, adr, val << lsb, dms); +} + +/* + * dbsc5_ddr_setval() - Write setting from DDR PHY hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval(struct udevice *dev, u32 ch, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_slice(dev, ch, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_slice() - Write setting from DDR PHY hardware for all channels and one slice + * @dev: DBSC5 device + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_slice(struct udevice *dev, u32 slice, u32 regdef, u32 val) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval_slice(dev, ch, slice, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch() - Write setting from DDR PHY hardware for all channels and slice 0 + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch(struct udevice *dev, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_all_ch_slice(dev, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_all_slice() - Write setting from DDR PHY hardware for all channels and all slices + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_all_slice(struct udevice *dev, u32 regdef, u32 val) +{ + u32 slice; + + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_all_ch_slice(dev, slice, regdef, val); +} + +/** + * dbsc5_ddr_getval_slice() - Read setting from DDR PHY/PI hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * + * Calculate the address and the bit-field from "regdef" value. + * Call dbsc5_reg_ddrphy_read() to read value from the target address. + */ +static u32 dbsc5_ddr_getval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (dbsc5_reg_ddrphy_read(dev, ch, adr) >> lsb) & msk; +} + +/** + * dbsc5_ddr_getval() - Read setting from DDR PHY/PI hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * + * Wrapper around dbsc5_ddr_getval_slice() for slice 0. + */ +static u32 dbsc5_ddr_getval(struct udevice *dev, u32 ch, u32 regdef) +{ + return dbsc5_ddr_getval_slice(dev, ch, 0, regdef); +} + +/** + * dbsc5_table_patch_set() - Modify DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @adrmsk_pi: Use wider address mask for PI register + * @patch: List of modifications to the settings table + * @patchlen: Length of the list of modifications to the settings table + * + * Calculate the target index of settings table, calculate the bit-field + * to write the setting value, and write the setting value to the target + * bit-field in the index. + */ +static void dbsc5_table_patch_set(u32 *tbl, const bool adrmsk_pi, + const struct dbsc5_table_patch *patch, + int patchlen) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + u32 adr, len, lsb, msk; + int i; + + for (i = 0; i < patchlen; i++) { + adr = DDR_REGDEF_ADR(patch[i].reg); + len = DDR_REGDEF_LEN(patch[i].reg); + lsb = DDR_REGDEF_LSB(patch[i].reg); + msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + + tbl[adr & adrmsk] &= ~msk; + tbl[adr & adrmsk] |= (patch[i].val << lsb) & msk; + } +} + +/** + * dbsc5_ddrtbl_getval() - Read setting from DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @regdef: Encoded PHY/PI register and bitfield + * @adrmsk_pi: Use wider address mask for PI register + * + * Calculate the target index of *tbl and the bit-field to read the + * setting value and read and return the setting value from the target + * bit-field in the index. + */ +static u32 dbsc5_ddrtbl_getval(const u32 *tbl, u32 regdef, bool adrmsk_pi) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + const u32 adr = DDR_REGDEF_ADR(regdef); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (tbl[adr & adrmsk] >> lsb) & msk; +} + +/** + * dbsc5_f_scale() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ps Optimal setting value in pico second + * @cyc Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) +{ + const u32 mul = frac ? 8 : 800000; + const u32 tmp = DIV_ROUND_UP(ps, 10UL) * priv->ddr_mbps; + const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * priv->ddr_mbpsdiv); + + return (f_scale_div > cyc) ? f_scale_div : cyc; +} + +/** + * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 + * @priv: Driver private data + * + * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. + * Only the following array elements are calculated using different formulas from those + * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. + */ +static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv) +{ + const int derate = 0; + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + priv->js2[i] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][i].ps, + jedec_spec2[derate][i].cyc); + } + + priv->js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tZQCALns].ps * 1000UL, 0); + priv->js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tDQ72DQns].ps * 1000UL, 0); + priv->js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tCAENTns].ps * 1000UL, 0); + priv->js2[JS2_tRCpb] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPpb]; + priv->js2[JS2_tRCab] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPab]; + priv->js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_ab[priv->max_density] * 1000UL, 0); + + priv->js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; + priv->js2[JS2_tXSR] = priv->js2[JS2_tRFCab] + + dbsc5_f_scale(priv, false, 7500, 2); + priv->js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; + priv->js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tPDN_DSM].ps * 10UL, 0); + priv->js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXSR_DSM].ps * 10UL, 0); + priv->js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXDSM_XP].ps * 10UL, 0); + priv->js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); +} + +/** + * dbsc5_ddrtbl_calc() - Calculate JS1/JS2 + * @priv: Driver private data + * + * Determine jedec_spec1 configuration table based on priv->ddr_mbps + * and priv->ddr_mbpsdiv. Calculate the value of the jedec_spec2 + * configuration table from priv->ddr_mbps and priv->ddr_mbpsdiv. + */ +static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv) +{ + int i; + + /* Search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) + if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3) + break; + + priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI); + + priv->RL = js1[priv->js1_ind].RLset1; + priv->WL = js1[priv->js1_ind].WLsetA; + + /* Calculate jedec_spec2 */ + dbsc5_f_scale_js2(priv); +}; + +/** + * dbsc5_ddrtbl_load() Load table data into DDR registers + * @dev: DBSC5 device + * + * Copy the base configuration table to a local array. Change PI register table + * settings to match priv->ddr_mbps and priv->ddr_mbpsdiv. + * + * If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" + * setting in the configuration table. + * + * If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" + * setting in the configuration table. + * + * If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" + * setting in the configuration table. + * + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 5120, + * change the contents of the PHY register setting table. + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 4576, + * change the contents of the PHY register setting table. + * + * Reflect the contents of the configuration table in the register. + */ +static void dbsc5_ddrtbl_load(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbps = { + PHY_CAL_INTERVAL_COUNT_0, 10000 * priv->ddr_mbps / priv->ddr_mbpsdiv / 8 / 256, + }; + + const struct dbsc5_table_patch dbsc5_table_patch_pi_js[] = { + { PI_WRLAT_F2, priv->WL }, + { PI_TWCKENL_WR_ADJ_F2, (js1[priv->js1_ind].WCKENLW * 4) + 4 }, + { PI_TWCKENL_RD_ADJ_F2, (js1[priv->js1_ind].WCKENLR * 4) + 4 }, + { PI_TWCKPRE_STATIC_F2, (js1[priv->js1_ind].WCKPRESTA * 4) }, + { PI_TWCKPRE_TOGGLE_RD_F2, (js1[priv->js1_ind].WCKPRETGLR) * 4 }, + { PI_CASLAT_F2, priv->RL }, + { PI_TWCKENL_FS_ADJ_F2, (js1[priv->js1_ind].WCKENLF * 4) + 4 }, + { PI_TRFC_F2, priv->js2[JS2_tRFCab] }, + { PI_WRLVL_WCKOFF_F2, (priv->js2[JS2_tWLWCKOFF]) + 3 }, + { PI_WRLAT_ADJ_F2, (priv->WL * 4) + 2 }, + { PI_TCAENT_F2, priv->js2[JS2_tCAENTns] }, + { PI_TVREF_LONG_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TVREF_SHORT_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TRCD_F2, priv->js2[JS2_tRCD] }, + { PI_TRP_F2, priv->js2[JS2_tRPab] }, + { PI_TRTP_F2, js1[priv->js1_ind].nRBTP }, + { PI_TRAS_MIN_F2, priv->js2[JS2_tRAS] }, + { PI_TMRD_F2, (priv->js2[JS2_tMRD]) + 1 }, + { PI_TSR_F2, priv->js2[JS2_tSR] }, + { PI_TZQCAL_F2, priv->js2[JS2_tZQCALns] }, + { PI_TZQLAT_F2, priv->js2[JS2_tZQLAT] }, + { PI_TDQ72DQ_F2, priv->js2[JS2_tDQ72DQns] }, + { PI_MC_TRFC_F2, priv->js2[JS2_tRFCab] }, + }; + + const u32 vref_r = priv->dbsc5_board_config->bdcfg_vref_r; + const struct dbsc5_table_patch dbsc5_table_patch_slice_vref_r[] = { + { PHY_VREF_INITIAL_START_POINT, vref_r & 0xFF }, + { PHY_VREF_INITIAL_STOP_POINT, (vref_r & 0xFF00) >> 8 }, + { PHY_VREF_INITIAL_STEPSIZE, (vref_r & 0xFF0000) >> 16 } + }; + + const u32 vref_w = priv->dbsc5_board_config->bdcfg_vref_w; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_w[] = { + { PI_WDQLVL_VREF_INITIAL_START_POINT_F0, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F1, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F2, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (vref_w & 0xff00) >> 8 } + }; + + const u32 vref_ca = priv->dbsc5_board_config->bdcfg_vref_ca; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_ca[] = { + { PI_CALVL_VREF_INITIAL_START_POINT_F0, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F1, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F2, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (vref_ca & 0xff00) >> 8 } + }; + + int i, cs, slice; + u32 adr; + + /* Prepare register tables */ + memcpy(priv->DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_V4H, sizeof(DDR_PHY_SLICE_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_V4H, sizeof(DDR_PHY_ADR_V_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_V4H, sizeof(DDR_PHY_ADR_G_REGSET_V4H)); + memcpy(priv->DDR_PI_REGSET, DDR_PI_REGSET_V4H, sizeof(DDR_PI_REGSET_V4H)); + + /* Adjust PI parameters */ + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbps, 1); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_js, + ARRAY_SIZE(dbsc5_table_patch_pi_js)); + + if (priv->ddr_mbps < (3201 * priv->ddr_mbpsdiv)) { + /* 2751-3200 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3200, + ARRAY_SIZE(dbsc5_table_patch_slice_3200)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3200, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3200)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3200, + ARRAY_SIZE(dbsc5_table_patch_pi_3200)); + } else if (priv->ddr_mbps < (3734 * priv->ddr_mbpsdiv)) { + /* 3201-3733 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3733, + ARRAY_SIZE(dbsc5_table_patch_slice_3733)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3733, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3733)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3733, + ARRAY_SIZE(dbsc5_table_patch_pi_3733)); + } else if (priv->ddr_mbps < (4268 * priv->ddr_mbpsdiv)) { + /* 3734-4267 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4266, + ARRAY_SIZE(dbsc5_table_patch_slice_4266)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4266, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4266)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4266, + ARRAY_SIZE(dbsc5_table_patch_pi_4266)); + } else if (priv->ddr_mbps < (4801 * priv->ddr_mbpsdiv)) { + /* 4269-4800 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4800, + ARRAY_SIZE(dbsc5_table_patch_slice_4800)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4800, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4800)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4800, + ARRAY_SIZE(dbsc5_table_patch_pi_4800)); + } else if (priv->ddr_mbps < (5501 * priv->ddr_mbpsdiv)) { + /* 4801 - 5500 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_5500, + ARRAY_SIZE(dbsc5_table_patch_slice_5500)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_5500, + ARRAY_SIZE(dbsc5_table_patch_adr_v_5500)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_5500, + ARRAY_SIZE(dbsc5_table_patch_pi_5500)); + } else if (priv->ddr_mbps < (6001 * priv->ddr_mbpsdiv)) { + /* 5501 - 6000 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_6000, + ARRAY_SIZE(dbsc5_table_patch_slice_6000)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_6000, + ARRAY_SIZE(dbsc5_table_patch_adr_v_6000)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_6000, + ARRAY_SIZE(dbsc5_table_patch_pi_6000)); + } + + for (cs = 0; cs < CS_CNT; cs++) { + struct dbsc5_table_patch dbsc5_table_patch_pi_mr12[] = { + { PI_DARRAY3_0_CSx_Fx[cs][2], js1[priv->js1_ind].MR1 }, + { PI_DARRAY3_1_CSx_Fx[cs][2], js1[priv->js1_ind].MR2 }, + }; + + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_mr12, + ARRAY_SIZE(dbsc5_table_patch_pi_mr12)); + } + + /* Read Vref (SoC side) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_r) { + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_vref_r, + ARRAY_SIZE(dbsc5_table_patch_slice_vref_r)); + } + + /* Write Vref (MR14, MR15) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_w) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_w, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_w)); + } + + /* CA Vref (MR12) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_ca) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_ca, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_ca)); + } + + /* Low Freq setting */ + if (priv->ddr_mbps < (8 * 640 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + &dbsc5_table_patch_adr_v_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_640, 1); + } + + if (priv->ddr_mbps < (8 * 572 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_572, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_572, 1); + } + + if (priv->ddr_mbps < (8 * 401 * priv->ddr_mbpsdiv)) { + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + dbsc5_table_patch_adr_g_mbpsdiv_400, + ARRAY_SIZE(dbsc5_table_patch_adr_g_mbpsdiv_400)); + } + + /* SET DATA SLICE TABLE */ + for (slice = 0; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS_V4H + (DDR_PHY_SLICE_REGSET_SIZE_V4H * slice); + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, adr + i, priv->DDR_PHY_SLICE_REGSET[i]); + } + + /* SET ADR SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_V_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_V_REGSET[i]); + + /* SET ADRCTRL SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_G_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_G_REGSET[i]); + + /* SET PI REGISTERS */ + for (i = 0; i < DDR_PI_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PI_REGSET_OFS_V4H + i, priv->DDR_PI_REGSET[i]); +} + +/** + * dbsc5_ddr_config() - Configure DDR registers + * @dev: DBSC5 device + * + * Set up wiring for DQ and DM pins and VREF_DRIVING. Set the CA pin wiring + * and ADR_CALVL_SWIZZLE settings. Make wiring settings for the CS pin. When + * memory rank is 1, set RANK setting to 1 to disable CS training. Configure + * the DATA_BYTE_SWAP setting. + */ +static void dbsc5_ddr_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ca_swap, cs_swap, dqs_swap; + u32 ch, slice; + + r_foreach_vch(dev, ch) { + /* Board settings (DQ, DM, VREF_DRIVING) */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE0, + priv->dbsc5_board_config->ch[ch].bdcfg_dq_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE1, + priv->dbsc5_board_config->ch[ch].bdcfg_dm_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, + !((dqs_swap >> (4 * slice)) & 1)); + } + dbsc5_ddr_setval(dev, ch, PHY_DATA_BYTE_ORDER_SEL, + priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap | 0x76543200); + + /* Board settings (CA, ADDR_MUX) */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + + /* ADDR_MUX */ + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_0, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_1, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_2, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_3, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_4, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_5, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_6, ca_swap & 0xf); + ca_swap >>= 4; + + /* ADR_CALVL_SWIZZLE */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_SWIZZLE0, ca_swap & 0x0fffffff); + + /* Board settings (CS) */ + /* CKE_MUX */ + /* SoC CKE -> DRAM CS */ + cs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_cs_swap; + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_0, (cs_swap & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_1, ((cs_swap >> 4) & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT2_2, (cs_swap & 0xf) + 1); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((cs_swap >> 4) & 0xf) + 1); + + /* Mask CS_MAP if RANK1 is not found */ + if (!(priv->ch_have_this_cs[1] & BIT(ch))) { + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_RANK_CTRL, 0x0); + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_PER_CS_TRAINING_EN, 0x0); + } + } + + r_foreach_vch(dev, ch) { + /* DATA_BYTE_SWAP */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_EN, 0x1); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE0, dqs_swap & 0xf); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE1, (dqs_swap >> 4) & 0xf); + + if (!(priv->ch_have_this_cs[1] & BIT(ch))) + dbsc5_ddr_setval(dev, ch, PI_CS_MAP, 0x1); + } +} + +/** + * dbsc5_dbsc_regset_pre() - Configure primary DDR registers + * @dev: DBSC5 device + * + * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. + * Write SDRAM configuration contents to registers. + */ +static void dbsc5_dbsc_regset_pre(struct udevice *dev) +{ +#define DBMEMCONF_REG(d3, row, bg, bank, col, dw) \ + (((d3) << 30) | ((row) << 24) | ((bg) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) /* 16bit */ \ + DBMEMCONF_REG(((density) % 2), ((((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1)), 2, 2, 10, 1) + + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 density; + u32 ch, cs; + + /* Primary settings */ + /* LPDDR5, BL=16, DFI interface */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBMEMKIND, 0xC); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBMEMKINDA, 0xC); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBBL, 0x2); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBLA, 0x2); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBPHYCONF0, 0x1); + + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF0, 0x1); + + /* FREQRATIO=2 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF1, 0x20000); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF1A, 0x0); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF2, 0x1); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF2A, 0x241); + + r_foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if (priv->ddr_density[ch][cs] == 0xFF) { + writel(0x00, regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(0x00, regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } else { + density = priv->ddr_density[ch][cs]; + writel(DBMEMCONF_REGD(density), + regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(DBMEMCONF_REGD(density), + regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } + } + } +} + +/** + * dbsc5_dbsc_regset() - Set DBSC timing parameters + * @dev: DBSC5 device + * + * Set the timing registers of the DBSC. + * Configure Scheduler settings. + */ +static void dbsc5_dbsc_regset(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 tmp[4]; + + /* DBTR0.CL : RL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(0), priv->RL); + + /* DBTR1.CWL : WL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(1), priv->WL); + + /* DBTR2.AL = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(2), 0x0); + + /* DBTR3.TRCD: tRCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(3), priv->js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(4), (priv->js2[JS2_tRPab] << 16) | + priv->js2[JS2_tRPpb]); + + /* DBTR5.TRC : tRCpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(5), priv->js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(6), priv->js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(7), ((priv->js2[JS2_tRRD] - 1) << 16) | + (priv->js2[JS2_tRRD] - 1)); + + /* DBTR8.TFAW : tFAW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(8), priv->js2[JS2_tFAW] - 1); + + /* DBTR9.TRDPR: nRBTP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); + + /* DBTR10.TWR : nWR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(10), js1[priv->js1_ind].nWR); + + /* + * DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + + * RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature + */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11), + priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - + js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]); + + /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12), + ((priv->WL + 2 + priv->js2[JS2_tWTR_S]) << 16) | + (priv->WL + 4 + priv->js2[JS2_tWTR_L])); + + /* DBTR13.TRFCAB : tRFCab */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(13), priv->js2[JS2_tRFCab]); + + /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(14), (priv->js2[JS2_tCSCAL] << 24) | + (priv->js2[JS2_tXP] << 16) | + priv->js2[JS2_tXP]); + + /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(15), (0x02 << 24) | + (priv->js2[JS2_tSR] << 16) | + priv->js2[JS2_tSR]); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (priv->WL * 4) - 1 + 5; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (priv->WL * 4) - 2 - 2 + 5; + /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (priv->RL * 4) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, false) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, false) + + 39; + /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (priv->RL * 4) + 4 - + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, false); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(16), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(17), (priv->js2[JS2_tMRR] << 24) | + (priv->js2[JS2_tMRW] << 16)); + + /* DBTR18. RODTL, RODTA = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(18), 0x0); + + /* DBTR19. TZQCL, TZQCS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(19), 0x0); + + /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(20), ((priv->js2[JS2_tXSR]) << 16) | + priv->js2[JS2_tXSR]); + + /* DBTR21.TCCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(21), (priv->ddr_tccd << 16) | + (priv->ddr_tccd * 2)); + + /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(22), (priv->js2[JS2_tZQCALns] << 16) | priv->js2[JS2_tZQLAT]); + + /* DBTR23. RRSPC = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(23), 0x0); + + /* DBTR24 */ + /* WRCSLAT(tphy_wrcslat) */ + tmp[0] = (priv->WL * 4) - 2; + /* WRCSGAP(tphy_wrcsgap) */ + tmp[1] = 0x0C; + /* RDCSLAT(tphy_rdcslat) */ + tmp[2] = priv->RL * 4; + /* RDCSGAP(tphy_rdcsgap) */ + tmp[3] = 0x0C; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR25. TWDQLVLDIS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(25), 0x0); + + /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(26), 0x0); + + /* DBTR27.TPDN : tPDN */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(27), priv->js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(28), priv->js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(29), priv->js2[JS2_tXDSM_XP]); + + /* DBTR30.TCMDPD : tCMDPD = 3 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(30), 0x3); + + /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(31), (priv->js2[JS2_tWCK2DQO_HF] << 4) | + priv->js2[JS2_tWCK2DQI_HF]); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[priv->js1_ind].WCKENLR * 4) + 4 - 1; + /* twckenw */ + tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) + 4 - 1; + /* twckenlf */ + tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) + 4; + /* twckpresta */ + tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR33 */ + /* TWCKTGL */ + tmp[0] = 4; + /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ + tmp[1] = ((priv->RL + 4) * 4) + 3; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); + + /* DBTR34 */ + /* TWCKSUS = 4 */ + tmp[0] = 4; + /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ + tmp[1] = 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); + + /* DBTR35 */ + /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = priv->RL + 4 + 0 + 1; + /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = priv->WL + 4 + 0 + 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); + + /* DBTR36 */ + /* TWSSUSWRX : CAS(WCKSUS)WRX */ + tmp[0] = 3; + /* TWSOFFWRX : CAS(WS_OFF)WRX */ + tmp[1] = 3; + /* TWSFSWRX : CAS(WS_FS)WRX */ + tmp[2] = 2; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR37 */ + /* tOSCO */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(37), priv->js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* RNKRR = 12 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(2), 0xCC); + + /* DBRNK3 */ + /* RNKRW = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(3), 0x66); + + /* DBRNK4 */ + /* RNKWR = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(4), 0x66); + + /* DBRNK5 */ + /* RNKWW = 14 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(5), 0xEE); + + /* Timing registers for Scheduler */ + /* SCFCTST0 */ + /* SCPREACT */ + tmp[0] = priv->js2[JS2_tRPpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTRDWR */ + tmp[1] = (priv->WL + 2 + 1 + js1[priv->js1_ind].nWR + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDACRT */ + tmp[2] = ((js1[priv->js1_ind].nRBTP + 2) + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTACT */ + tmp[3] = priv->js2[JS2_tRCpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCASYNCOFS */ + tmp[0] = 12; + /* SCACTRDWR */ + tmp[1] = priv->js2[JS2_tRCD] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCWRRD */ + tmp[2] = (readl(regs_dbsc_d + DBSC_DBTR(12)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDWR */ + tmp[3] = (readl(regs_dbsc_d + DBSC_DBTR(11)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* SCTRFCAB */ + tmp[0] = (priv->js2[JS2_tRFCab] + priv->js2[JS2_tZQLAT]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* SCDT0 */ + tmp[0] = (4 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT1 */ + tmp[1] = (8 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT2 */ + tmp[2] = (12 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT3 */ + tmp[3] = (16 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* QOS and CAM */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBCAMDIS, 0x1); +} + +/** + * dbsc5_dbsc_regset_post() - Set DBSC registers + * @dev: DBSC5 device + * + * If memory rank is 2, CS_TRAINING_EN is set to the other side. + * Configure DBI read/write settings. Execute DRAM refresh settings. + * Set WTmode of DFI PHY to OFF. Set up PHY Periodic Write DQ training. + * Set WTmode of DFI PHY to ON. Calibration settings for PHY PAD. + * Set SDRAM calibration. Make DFI Control Update Setting settings. + * In the case of WARM_BOOT, cancel the self-refresh setting. + * Enable SDRAM auto refresh. Set up PHY Periodic Write DQ training. + * Enable access to SDRAM. + */ +static void dbsc5_dbsc_regset_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + /* Average periodic refresh interval/Average Refresh Interval [ns] */ + const u32 dbsc_refint = 1920; + /* 0: Average interval is REFINT, 1: Average interval is 1/2 REFINT */ + const u32 dbsc_refints = 0; + /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ + const u32 periodic_training_interval = 20000; + u32 phymster_req_interval; + u32 ch, slice; + u32 clk_count; + u32 refcycle; + u32 ctrl_clk; + u32 reg; + + if ((renesas_get_cpu_rev_integer() < 3) && priv->ch_have_this_cs[1]) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_PER_CS_TRAINING_EN, + 0x0); + } + } + } + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDBICNT, 0x3); + + /* set REFCYCLE */ + refcycle = dbsc_refint * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; + /* refpmax=8 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF1, (refcycle & 0xFFFF) | BIT(19)); + /* refpmin=1 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF2, dbsc_refints | BIT(16)); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x0); + + /* Periodic-WriteDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_VREF_EN, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_WDQLVL_ENABLE, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_PERIODIC, 0x1); + + /* Periodic-ReadDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDLVL_DLY_STEP, 0x4); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_PERIODIC, 0x1); + + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x11); + + /* periodic SoC zqcal enable */ + reg = dbsc5_ddrtbl_getval(priv->DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0, false); + dbsc5_ddr_setval_all_ch(dev, PHY_CAL_MODE_0, reg | BIT(1)); + + /* Periodic dram zqcal enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCALCNF, 0x1000010); + + /* Periodic phy ctrl update enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFICUPDCNF, 0x504C0001); + + /* Set Auto Refresh */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFEN, 0x1); + + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = periodic_training_interval - 3000; + clk_count = 1024 - (dbsc5_ddrtbl_getval(priv->DDR_PI_REGSET, PI_LONG_COUNT_MASK, true) * 32); + ctrl_clk = priv->ddr_mbps / priv->ddr_mbpsdiv / 8; + reg = phymster_req_interval * ctrl_clk / clk_count; + + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_INTERVAL, reg); + + /* DRAM access enable */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBACEN, 0x1); +} + +/** + * dbsc5_pi_training() - Training by PI + * @dev: DBSC5 device + * + * Enable WCK signal training and read gate training. Start PI training. + * After DFI initialization for all channels is once turned off, turned + * on all chennels of it. Power down the DRAM device once and then release + * the power down mode. Perform training in low frequency mode and training + * in high frequency mode. Wait for the DFI training completion status + * bit to stand until the time limit. Turn off DFI initialization for all + * channels. Turn off WTMODE of DFI PHY. Check if CA/CS Training has failed. + * Check if Wrlvl training is in error. If an error can be confirmed from + * the check result, the result is returned as a return value. Clear the + * status register for PI training. + */ +static u32 dbsc5_pi_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const int retry_max = 0x10000; + u32 ca_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + bool frqchg_req; + u32 ch, reg; + int retry; + int ret; + + /* Init start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_9, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_10, 0x0); + + /* PI_START */ + dbsc5_ddr_setval_all_ch(dev, PI_START, 0x1); + + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + r_foreach_vch(dev, ch) + writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* Dummy PDE */ + dbsc5_send_dbcmd2(dev, 0x8840000); + + /* PDX */ + dbsc5_send_dbcmd2(dev, 0x8840001); + + /* Wait init_complete */ + for (retry = 0; retry < retry_max; retry++) { + frqchg_req = false; + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + if (!((~phytrainingok & priv->ddr_phyvalid) & BIT(ch))) + continue; + + if (!(readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)) & BIT(0))) + continue; + + frqchg_req = true; + break; + } + + if (frqchg_req) { + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + break; + } else { + r_foreach_vch(dev, ch) { + if (readl(regs_dbsc_d + DBSC_DBDFISTAT(ch)) & BIT(0)) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + } + + /* + * dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* DFI_PHYMSTR_ACK */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x1); + + /* Error check */ + r_foreach_vch(dev, ch) { + /* CA/CS Training Error Check */ + /* PI_CALVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(4); + /* Error on decrement/increment pass */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS1) & (0x3 << 30); + /* Start outside of initial search range */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS2) & (0x3 << 24); + /* CSlvl error */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_CSLVL_OBS1) & (0xF << 28); + if (reg) { + ca_training_ng |= BIT(ch); + printf("%s pi_training_error:1\n", __func__); + } + + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s pi_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | ca_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_write_leveling_adjust() - Write Leveling Cycle Adjust + * @dev: DBSC5 device + * + * Get delay value from the result write leveling of slice 0 and 1. + * Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask + * signals based on delay values. + */ +static void dbsc5_write_leveling_adjust(struct udevice *dev) +{ + u32 result_hard0, result_hard1; + u32 avg, avg_frac, avg_cycle; + u32 ch; + + r_foreach_vch(dev, ch) { + /* SLICE0 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 > result_hard1) + avg += 0x400; + avg /= 2; + + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 >= result_hard1) + avg += 0x400; + avg /= 2; + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, SC_PHY_WCK_CALC, 0x1); +} + +/** + * dbsc5_wl_gt_training() - Re-run Write Leveling & Read Gate Training + * @dev: DBSC5 device + * + * Set CA leveling OFF, read gate leveling ON, write gate leveling ON, + * PI dram wck training ON. Perform PI_DFS configuration. Start PI + * frequency training in manual mode. Perform training in high-frequency + * mode. Check for Write leveling Error and Gate leveling Error. If an + * error is identified, the resulting value is inverted and returned. + * Clear the PI status register. + */ +static u32 dbsc5_wl_gt_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + + dbsc5_ddr_setval_all_ch(dev, PI_DFS_ENTRY_SEQ_0, 0x181F0000); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:1\n", __func__); + } + + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_pi_int_ack_0_assert() - Training handshake functions + * @dev: DBSC5 device + * @bit: Status bit to poll + * + * Wait for the status bit specified in the argument to become 1 until the + * time limit. After checking status bits on all channels, clear the target + * status bits and returns the result of the check as the return value. + */ +static u32 dbsc5_pi_int_ack_0_assert(struct udevice *dev, u32 bit) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 ch, phytrainingok = 0; + int retry; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(bit)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, BIT(bit)); + + return phytrainingok; +} + +/** + * dbsc5_write_dca() - Write DCA Training + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static void dbsc5_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_CAL_START, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_DATA_DC_CAL_START) | + dbsc5_ddr_getval_slice(dev, ch, 1, PHY_DATA_DC_CAL_START); + if (!reg) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } +} + +/** + * dbsc5_dramdca_training() - DRAM DCA Training and Calculations + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static u32 dbsc5_dramdca_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 mr30_conv[16] = { + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, + 0x0, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF + }; + u32 dca_result_l_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_l_1[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_1[DRAM_CH_CNT][CS_CNT]; + u32 ch, phytrainingok, reg; + u32 tempu, templ; + + /* Run DRAM DCA Training for Flip-0 */ + dbsc5_ddr_setval_all_ch(dev, PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-0 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Run DRAM DCA Training for Flip-1 */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x0); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-1 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Calculate and set DRAMDCA value */ + r_foreach_vch(dev, ch) { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS0_F2, reg); + if (!(rank & 0x2)) + continue; + + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS1_F2, reg); + } + + /* Set DRAMDCA value in MR30 */ + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_0, 0x1A11E14); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_1, 0x1F0000); + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, rank); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_START, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 19); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x2); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x1101FC); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x211A00); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x51500); + + return phytrainingok; +} + +/** + * dbsc5_write_leveling() - Re-run Write Leveling + * @dev: DBSC5 device + * + * CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA + * training is set to OFF. Set the memory rank for the Write leveling target + * and start leveling. Wait until leveling is complete. + * + * Check for Write leveling errors. If an error is confirmed to have occurred, + * the result is returned as a return value. Clear the PI status bit. + */ +static u32 dbsc5_write_leveling(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(29)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s write_leveling_error:1\n", __func__); + } + } + + if (wr_training_ng) + return ~wr_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_manual_write_dca() - Manual Write DCA Training + * @dev: DBSC5 device + * + * Write DCA training according to memory rank. + */ +static void dbsc5_manual_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1; + u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 slv_dly_center_cyc; + u32 slv_dly_center_dly; + u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_mid; + const int retry_max = 0x10000; + const u8 ratio_min_div = 0xA; + const u8 ratio_max_div = 0x2; + const u8 ratio_min = 0x6; + const u8 ratio_max = 0x3; + u32 ch, cs, slice, tmp; + u32 complete = 0; + int i, retry; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_min[ch][slice] = 0x7F; + phy_dcc_code_max[ch][slice] = 0x0; + } + } + + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + slv_dly_center[ch][cs][slice] = + dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180; + slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F; + slv_dly_min_tmp[ch][cs][slice] = + slv_dly_center_cyc | + (slv_dly_center_dly * ratio_min / ratio_min_div); + slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc; + if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div)) + slv_dly_max_tmp[ch][cs][slice] |= 0x7F; + else + slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div; + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (rank == 0x2) { + if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice]) + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice]; + else + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; + + if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice]) + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; + else + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice]; + } else { + slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice]; + slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice]; + } + } + } + + for (i = 0; i <= 0x7F; i++) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) { + complete |= BIT(ch) << (8 * slice); + } else { + /* CS0/1 same setting, Need masked write */ + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + slv_dly_min[ch][slice] + i); + dbsc5_ddr_setval_slice(dev, ch, slice, SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + + if (complete == (priv->ddr_phyvalid | (priv->ddr_phyvalid << 8))) + break; + + /* Execute write dca */ + r_foreach_vch(dev, ch) + for (slice = 0; slice < SLICE_CNT; slice++) + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DATA_DC_CAL_START, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) { + for (retry = 0; retry < retry_max; retry++) { + tmp = dbsc5_ddr_getval_slice(dev, ch, slice, + PHY_DATA_DC_CAL_START); + if (!tmp) + break; + } + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if ((slv_dly_min[ch][slice] + i) > slv_dly_max[ch][slice]) + continue; + + tmp = (dbsc5_ddr_getval_slice(dev, ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x1) + tmp = 0x0; + else if ((tmp >> 6) == 0x2) + tmp = 0x3F; + + if (tmp < phy_dcc_code_min[ch][slice]) + phy_dcc_code_min[ch][slice] = tmp; + + if (phy_dcc_code_max[ch][slice] < tmp) + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + slv_dly_center[ch][cs][slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, + SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + + phy_dcc_code_max[ch][slice]) / 2; + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_DATA_DC_DQS_CLK_ADJUST, + phy_dcc_code_mid); + } + } +} + +/** + * dbsc5_read_gate_training() - Re-run read gate training by PI + * @dev: DBSC5 device + * + * Write leveling set to OFF, read gate leveling set to ON. Set memory rank + * for leveling target, turn on read gate leveling. Wait for leveling to be + * completed until the time limit. Check for errors during gate leveling. + * + * If an error is confirmed to have occurred, the result is returned as a + * return value. Clear the PI status register. + */ +static u32 dbsc5_read_gate_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(24)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2)); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s read_gate_training_error\n", __func__); + } + } + + if (gt_training_ng) + return ~gt_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_vref_training() - Read Data Training with VREF Training + * @dev: DBSC5 device + * + * Set reading leveling to ON and Vref leveling of reading to OFF. + * Set Vref reading training to OFF. Get start value, end value and + * number of steps for Vref training. Determine the optimal VREFSEL + * value while increasing the Vref training setpoint by the starting + * value+step value. + */ +static u32 dbsc5_read_vref_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + u32 best_dvw_min_byte0, best_dvw_min_byte1; + u32 dvw_min_byte0_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte1_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte0[DRAM_CH_CNT] = { 0 }; + u32 dvw_min_byte1[DRAM_CH_CNT] = { 0 }; + u32 best_lower_vref, best_upper_vref; + u32 best_vref_byte0, best_vref_byte1; + u32 vref_start, vref_stop, vref_step; + u32 best_vref_byte0_index = 0; + u32 best_vref_byte1_index = 0; + const int retry_max = 0x10000; + u32 win_byte0, win_byte1; + u32 phytrainingok = 0; + u32 vref_stop_index; + u32 temple, tempte; + u32 best_thrshld; + u32 vref_outlier; + u32 outlier_cnt; + u32 curr_rank; + int i, retry; + u32 obs_sel; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F0, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_VREF_TRAINING_CTRL, 0x0); + + /* ch0 vref_point */ + vref_start = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_START_POINT); + vref_stop = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STOP_POINT); + vref_step = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80) + return 0; + + for (i = 0; i <= vref_stop_index; i++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + } + + for (curr_rank = 0; curr_rank < rank; curr_rank++) { + /* All ch Read Training Start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, BIT(curr_rank)); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + phytrainingok = 0; + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(25)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Read Training End */ + dbsc5_ddr_setval_all_ch(dev, PI_INT_ACK_0, BIT(25)); + + r_foreach_vch(dev, ch) { + /* minimum Data Valid Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFF; + dvw_min_byte1[ch] = 0xFFFFFFFF; + for (obs_sel = 0x0; obs_sel < 0x19; obs_sel++) { + if (!((obs_sel < 0x11) || (obs_sel == 0x18))) + continue; + + dbsc5_ddr_setval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + dbsc5_ddr_setval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + + temple = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte0 = tempte - temple; + else + win_byte0 = 0; + + temple = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte1 = tempte - temple; + else + win_byte1 = 0; + + if (dvw_min_byte0[ch] > win_byte0) + dvw_min_byte0[ch] = win_byte0; + + if (dvw_min_byte1[ch] > win_byte1) + dvw_min_byte1[ch] = win_byte1; + } + } + } + + r_foreach_vch(dev, ch) { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + } + + r_foreach_vch(dev, ch) { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0]; + + for (i = 0; i <= vref_stop_index; i++) { + if (best_dvw_min_byte0 >= dvw_min_byte0_table[ch][i]) + continue; + + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + + /* Search best_lower VREF byte0 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte0 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0]; + for (i = 0; i <= vref_stop_index; i++) { + if (best_dvw_min_byte1 >= dvw_min_byte1_table[ch][i]) + continue; + + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + + /* Search best_lower VREF byte1 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte1 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2; + + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte0); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte1); + } + + return phytrainingok; +} + +/** + * dbsc5_read_write_training() - Read Data & RDDQ Training with best VREF & Write DQ VREF Training + * @dev: DBSC5 device + * + * Set read DQS/RDQS slave delay setting to 0. Write leveling set to OFF, + * read gate leveling set to OFF. Turn on read and write leveling. Start + * frequency training. Training in high-frequency mode. Wait until training + * is complete. Check for errors in write dq leveling and read leveling. + + * If an error is confirmed to have occurred, return the inverted result + * value. Clear the PI status register. + */ +static u32 dbsc5_read_write_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 wdq_training_ng = 0; + u32 rd_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ0_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ1_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ2_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ3_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ4_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ5_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ6_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ7_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDM_SLAVE_DELAY, 0x0); + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_write_training_error:1\n", __func__); + } + + /* Wdqlvl Error Check */ + /* PI_WDQLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(5); + /* SLICE0 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + /* SLICE1 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + if (reg) { + wdq_training_ng |= BIT(ch); + printf("%s read_write_training_error:2\n", __func__); + } + } + + complete_ng = wdq_training_ng | rd_training_ng; + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_training() - Correct RDDQ Training result & Re-Run Read Data Training + * @dev: DBSC5 device + * + * Set the Read DQ correction value and its upper limit from the board + * settings. Check DDR memory ranks. Add the offset value to the current + * Read DQ value and write it to the register. Write the setting value + * to PI_RDLVL_TRAIN_SEQ_x. Start the Read training. PI_INT_ACK assert. + * Execute the Rdlvl Error Check. Confirm that training has been successfully + * completed. Return the result of the confirmation as the return value. + */ +static u32 dbsc5_read_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 rddq_delay_offset_ps = 0x19; + const u32 rddq_delay_max_ps = 0x67; + const u32 rddq_delay_addr[] = { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + const u32 rddq_delay_offset = rddq_delay_offset_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + const u32 rddq_delay_max = rddq_delay_max_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + u32 rd_training_ng = 0; + u32 ch, reg, slice; + u32 phytrainingok; + int i; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i < 9; i++) { + reg = dbsc5_ddr_getval_slice(dev, ch, slice, + rddq_delay_addr[i]) + + rddq_delay_offset; + if (reg > rddq_delay_max) + reg = rddq_delay_max; + dbsc5_ddr_setval_slice(dev, ch, slice, rddq_delay_addr[i], reg); + } + } + } + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_1, 0x89080); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_2, 0x811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_3, 0x40811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_4, 0x2000000); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_5, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + + /* Read training go */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 25); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_training_error\n", __func__); + } + } + + if (rd_training_ng) + return ~rd_training_ng; + + return phytrainingok; +} + +/** + * dbsc5_ddr_register_set() - DDR mode register setting + * @dev: DBSC5 device + * + * Set the mode register 28 of the SDRAM. + * ZQ Mode: Command-Based ZQ Calibration + * ZQ interval: Background Cal Interval < 64ms + */ +static void dbsc5_ddr_register_set(struct udevice *dev) +{ + dbsc5_send_dbcmd2(dev, 0xE841C24); +} + +/** + * dbsc5_ddr_register_read() - DDR mode register read + * @dev: DBSC5 device + * + * Set the mode register 27 and 57 of the SDRAM. + */ +static void dbsc5_ddr_register_read(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + if (!priv->dbsc5_board_config->bdcfg_rfm_chk) + return; + + /* MR27 rank0 */ + dbsc5_send_dbcmd2(dev, 0xF801B00); + /* MR57 rank0 */ + dbsc5_send_dbcmd2(dev, 0xF803900); + + if (!priv->ch_have_this_cs[1]) + return; + + /* MR27 rank1 */ + dbsc5_send_dbcmd2(dev, 0xF811B00); + /* MR57 rank1 */ + dbsc5_send_dbcmd2(dev, 0xF813900); +} + +/** + * dbsc5_init_ddr() - Initialize DDR + * @dev: DBSC5 device + * + * Status monitor and perform reset and software reset for DDR. + * Disable DDRPHY software reset. Unprotect the DDRPHY register. + * Perform pre-setting of DBSC registers. Configure the ddrphy + * registers. Process ddr backup. Set DBSC registers. + * + * Initialize DFI and perform PI training. Setup DDR mode registers + * pre-traning. Adjust number of write leveling cycles. Perform PI + * training in manual mode. Perform DRAM DCA training. Perform write + * leveling. Execute phydca training. Execute read gate training. + * + * Perform Vref training on read gate. Read DQ Write DQ Execute. + * Frequency selection change (F1->F2). Disable the FREQ_SEL_MULTICAST & + * PER_CS_TRAINING_MULTICAST. Start setting DDR mode registers. Set DBSC + * registers after training is completed. Set write protection for PHY + * registers. + */ +static u32 dbsc5_init_ddr(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 phytrainingok; + u32 ch, val; + int ret; + + /* PLL3 initialization setting */ + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + /* Reset Status Monitor set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKSETR4, 0x600); + /* ddrphy soft reset assert */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRCR4, readl(priv->cpg_regs + CPG_SRCR4) | 0x600); + /* Wait reset FB */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FSRCHKRA4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_FSRCHKRA4 Wait reset FB timeout\n", __func__); + hang(); + } + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + + /* Initialize PLL3 setting */ + dbsc5_clk_pll3_control(dev, PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); + + /* DDRPHY soft reset negate */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRSTCLR4, 0x600); + ret = readl_poll_timeout(priv->cpg_regs + CPG_SRCR4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_SRCR4 DDRPHY soft reset negate timeout\n", __func__); + hang(); + } + + /* Unlock PHY */ + /* Unlock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0xA55A, regs_dbsc_d + DBSC_DBPDLK(ch)); + + /* DBSC register pre-setting */ + dbsc5_dbsc_regset_pre(dev); + + /* Load DDRPHY registers */ + dbsc5_ddrtbl_calc(priv); + dbsc5_ddrtbl_load(dev); + + /* Configure ddrphy registers */ + dbsc5_ddr_config(dev); + + /* DDR backupmode end */ + + /* DBSC register set */ + dbsc5_dbsc_regset(dev); + + /* Frequency selection change (F1->F2) */ + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1); + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0); + + /* dfi_init_start (start ddrphy) & execute pi_training */ + phytrainingok = dbsc5_pi_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:1\n", __func__); + return phytrainingok; + } + + /* Write leveling cycle adjust */ + dbsc5_write_leveling_adjust(dev); + + /* Execute write leveling & read gate training */ + phytrainingok = dbsc5_wl_gt_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:2\n", __func__); + return phytrainingok; + } + + /* Execute write dca training */ + dbsc5_write_dca(dev); + + /* Execute dram dca training */ + phytrainingok = dbsc5_dramdca_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:3\n", __func__); + return phytrainingok; + } + + /* Execute write leveling */ + phytrainingok = dbsc5_write_leveling(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:4\n", __func__); + return phytrainingok; + } + + /* Execute manual write dca training */ + dbsc5_manual_write_dca(dev); + + /* Execute read gate training */ + phytrainingok = dbsc5_read_gate_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:5\n", __func__); + return phytrainingok; + } + + /* Execute read vref training */ + phytrainingok = dbsc5_read_vref_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:6\n", __func__); + return phytrainingok; + } + + /* Execute read dq & write dq training with best vref */ + phytrainingok = dbsc5_read_write_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:7\n", __func__); + return phytrainingok; + } + + /* correct rddq training result & Execute read dq training */ + phytrainingok = dbsc5_read_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:8\n", __func__); + return phytrainingok; + } + + /* PER_CS_TRAINING_MULTICAST SET (disable) */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + + /* setup DDR mode registers */ + /* MRS */ + dbsc5_ddr_register_set(dev); + + /* MRR */ + dbsc5_ddr_register_read(dev); + + /* training complete, setup DBSC */ + dbsc5_dbsc_regset_post(dev); + + /* Lock PHY */ + /* Lock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0x0, regs_dbsc_d + DBSC_DBPDLK(ch)); + + return phytrainingok; +} + +/** + * dbsc5_get_board_data() - Obtain board specific DRAM configuration + * + * Return board specific DRAM configuration structure pointer. + */ +__weak const struct renesas_dbsc5_board_config *dbsc5_get_board_data(void) +{ + return &renesas_v4h_dbsc5_board_config; +} + +/** + * renesas_dbsc5_dram_probe() - DDR Initialize entry + * @dev: DBSC5 device + * + * Remove write protection on DBSC register. Read DDR configuration + * information from driver data. Calculate board clock frequency and + * operating frequency from DDR configuration information. Call the + * main function of DDR initialization. Perform DBSC write protection + * after initialization is complete. + */ +static int renesas_dbsc5_dram_probe(struct udevice *dev) +{ +#define RST_MODEMR0 0x0 +#define RST_MODEMR1 0x4 + struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev); + ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node); + ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node); + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + phys_addr_t rregs = ofnode_get_addr(rnode); + const u32 modemr0 = readl(rregs + RST_MODEMR0); + const u32 modemr1 = readl(rregs + RST_MODEMR1); + u32 breg, reg, md, sscg; + u32 ch, cs; + + /* Get board data */ + priv->dbsc5_board_config = dbsc5_get_board_data(); + priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); + priv->max_density = 0; + priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode); + + for (cs = 0; cs < CS_CNT; cs++) + priv->ch_have_this_cs[cs] = 0; + + r_foreach_ech(ch) + for (cs = 0; cs < CS_CNT; cs++) + priv->ddr_density[ch][cs] = 0xFF; + + r_foreach_vch(dev, ch) { + for (cs = 0; cs < CS_CNT; cs++) { + priv->ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + + if (priv->ddr_density[ch][cs] == 0xFF) + continue; + + if (priv->ddr_density[ch][cs] > priv->max_density) + priv->max_density = priv->ddr_density[ch][cs]; + + priv->ch_have_this_cs[cs] |= BIT(ch); + } + } + + /* Decode board clock frequency from MD[14:13] pins */ + priv->brd_clkdiv = 3; + + breg = (modemr0 >> 13) & 0x3; + if (breg == 0) { + priv->brd_clk = 50; /* 16.66 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 1) { + priv->brd_clk = 60; /* 20 MHz */ + priv->bus_clk = priv->brd_clk * 0x14; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 3) { + priv->brd_clk = 100; /* 33.33 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv * 2; + } else { + printf("MD[14:13] setting 0x%x not supported!", breg); + hang(); + } + + priv->brd_clkdiva = !!(modemr0 & BIT(14)); /* MD14 */ + + /* Decode DDR operating frequency from MD[37:36,19,17] pins */ + md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17); + sscg = (modemr1 >> 4) & 0x03; + if (sscg == 2) { + printf("MD[37:36] setting 0x%x not supported!", sscg); + hang(); + } + + if (md == 0) { + if (sscg == 0) { + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + } else { + priv->ddr_mbps = 19000; + priv->ddr_mbpsdiv = 3; + } + } else if (md == 1) { + priv->ddr_mbps = 6000; + priv->ddr_mbpsdiv = 1; + } else if (md == 1) { + priv->ddr_mbps = 5500; + priv->ddr_mbpsdiv = 1; + } else if (md == 1) { + priv->ddr_mbps = 4800; + priv->ddr_mbpsdiv = 1; + } + + priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, + priv->brd_clk, priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + priv->ddr_mul_low = CLK_DIV(6400, 2, priv->brd_clk, + priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + priv->ddr_mul_reg = priv->ddr_mul_low; + if (sscg != 0) + priv->ddr_mul_reg -= 2; + + priv->ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1)) / + (priv->ddr_mbpsdiv * priv->brd_clk * 2)) - (8 * (priv->ddr_mul / 2) * 2); + + /* Adjust tccd */ + priv->ddr_tccd = 2; + + /* Initialize DDR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x1234); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x1234); + + reg = dbsc5_init_ddr(dev); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x0); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x0); + + return reg != priv->ddr_phyvalid; +} + +/** + * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data + * @dev: DBSC5 device + * + * Extract DBSC5 address from DT and store it in driver data. + */ +static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +/** + * renesas_dbsc5_dram_get_info() - Return RAM size + * @dev: DBSC5 device + * @info: Output RAM info + * + * Return size of the RAM managed by this RAM driver. + */ +static int renesas_dbsc5_dram_get_info(struct udevice *dev, + struct ram_info *info) +{ + info->base = 0x40000000; + info->size = 0; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_dram_ops = { + .get_info = renesas_dbsc5_dram_get_info, +}; + +U_BOOT_DRIVER(renesas_dbsc5_dram) = { + .name = "dbsc5_dram", + .id = UCLASS_RAM, + .of_to_plat = renesas_dbsc5_dram_of_to_plat, + .ops = &renesas_dbsc5_dram_ops, + .probe = renesas_dbsc5_dram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/qos.c b/drivers/ram/renesas/dbsc5/qos.c new file mode 100644 index 00000000000..56a60b987af --- /dev/null +++ b/drivers/ram/renesas/dbsc5/qos.c @@ -0,0 +1,636 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <hang.h> +#include <linux/sizes.h> +#include <ram.h> +#include "dbsc5.h" + +/* AXMM */ +#define AXMM_ADSPLCR0 0x4008 +#define AXMM_ADSPLCR1 0x400C +#define AXMM_ADSPLCR2 0x4010 +#define AXMM_ADSPLCR3 0x4014 +#define AXMM_MMCR 0x4300 +#define AXMM_TR0CR0 0x51000 +#define AXMM_TR1CR0 0x51004 +#define AXMM_TR2CR0 0x51008 +#define AXMM_TR3CR 0x5100C +#define AXMM_TR3CR0 0x5100C +#define AXMM_TR0CR1 0x51100 +#define AXMM_TR1CR1 0x51104 +#define AXMM_TR2CR1 0x51108 +#define AXMM_TR3CR1 0x5110C +#define AXMM_TR0CR2 0x51200 +#define AXMM_TR1CR2 0x51204 +#define AXMM_TR2CR2 0x51208 +#define AXMM_TR3CR2 0x5120C + +#define ACTEXT_RT0_R 0xFFC50800 +#define ACTEXT_RT0_W 0xFFC51800 +#define ACTEXT_IR0_R 0xFF890800 +#define ACTEXT_IR0_W 0xFF891800 +#define ACTEXT_IR1_R 0xFF892800 +#define ACTEXT_IR1_W 0xFF893800 +#define SI0_RW_MAX 0xF1201110 +#define SI1_RW_MAX 0xF1202110 + +/* DBSC */ +#define DBSC_A_CH_OFFSET 0x8000 +#define DBSC_D_CH_OFFSET 0x4000 + +#define DBSC_SYSCNT0 0x0100 +#define DBSC_SYSCNT1 0x0104 +#define DBSC_FCPRSCTRL 0x0110 +#define DBSC_DBBUS0CNF2 0x0808 +#define DBSC_DBCAM0CNF1 0x0904 +#define DBSC_DBCAM0CNF2 0x0908 +#define DBSC_DBCAM0CNF3 0x090C +#define DBSC_DBCAMDIS 0x09FC +#define DBSC_DBSCHCNT0 0x1000 +#define DBSC_DBSCHSZ0 0x1010 +#define DBSC_DBSCHRW0 0x1020 +#define DBSC_SCFCTST2 0x1048 +#define DBSC_DBSCHQOS_0_0 0x1100 +#define DBSC_DBSCHQOS_0_1 0x1104 +#define DBSC_DBSCHQOS_0_2 0x1108 +#define DBSC_DBSCHQOS_0_3 0x110C +#define DBSC_DBSCHQOS_4_0 0x1140 +#define DBSC_DBSCHQOS_4_1 0x1144 +#define DBSC_DBSCHQOS_4_2 0x1148 +#define DBSC_DBSCHQOS_4_3 0x114C +#define DBSC_DBSCHQOS_9_0 0x1190 +#define DBSC_DBSCHQOS_9_1 0x1194 +#define DBSC_DBSCHQOS_9_2 0x1198 +#define DBSC_DBSCHQOS_9_3 0x119C +#define DBSC_DBSCHQOS_12_0 0x11C0 +#define DBSC_DBSCHQOS_12_1 0x11C4 +#define DBSC_DBSCHQOS_12_2 0x11C8 +#define DBSC_DBSCHQOS_12_3 0x11CC +#define DBSC_DBSCHQOS_13_0 0x11D0 +#define DBSC_DBSCHQOS_13_1 0x11D4 +#define DBSC_DBSCHQOS_13_2 0x11D8 +#define DBSC_DBSCHQOS_13_3 0x11DC +#define DBSC_DBSCHQOS_14_0 0x11E0 +#define DBSC_DBSCHQOS_14_1 0x11E4 +#define DBSC_DBSCHQOS_14_2 0x11E8 +#define DBSC_DBSCHQOS_14_3 0x11EC +#define DBSC_DBSCHQOS_15_0 0x11F0 +#define DBSC_DBSCHQOS_15_1 0x11F4 +#define DBSC_DBSCHQOS_15_2 0x11F8 +#define DBSC_DBSCHQOS_15_3 0x11FC + +/* CCI */ +#define CCIQOS00 0xC020 +#define CCIQOS01 0xC024 +#define CCIQOS10 0xD000 +#define CCIQOS11 0xD004 + +/* QOS */ +#define QOS_FIX_QOS_BANK0 0x0 +#define QOS_FIX_QOS_BANK1 0x1000 +#define QOS_BE_QOS_BANK0 0x2000 +#define QOS_BE_QOS_BANK1 0x3000 +#define QOS_SL_INIT 0x8000 +#define QOS_REF_ARS 0x8004 +#define QOS_STATQC 0x8008 +#define QOS_REF_ENBL 0x8044 +#define QOS_BWG 0x804C +#define QOS_RAS 0x10000 +#define QOS_FSS 0x10048 +#define QOS_RAEN 0x10018 +#define QOS_DANN_LOW 0x10030 +#define QOS_DANN_HIGH 0x10034 +#define QOS_DANT 0x10038 +#define QOS_EMS_LOW 0x10040 +#define QOS_EMS_HIGH 0x10044 +#define QOS_INSFC 0x10050 +#define QOS_EARLYR 0x10060 +#define QOS_RACNT0 0x10080 +#define QOS_STATGEN0 0x10088 + +#define QOSWT_FIX_QOS_BANK0 0x800 +#define QOSWT_FIX_QOS_BANK1 0x1800 +#define QOSWT_BE_QOS_BANK0 0x2800 +#define QOSWT_BE_QOS_BANK1 0x3800 +#define QOSWT_WTEN 0x8030 +#define QOSWT_WTREF 0x8034 +#define QOSWT_WTSET0 0x8038 +#define QOSWT_WTSET1 0x803C + +static const struct { + u64 fix; + u64 be; +} g_qosbw_tbl[] = { + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04010000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00200030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00200030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x0000000000000000 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFF0, 0x0000000000000000 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C08140000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x001000F0004FFC01 }, + { 0x000C04010000FFFF, 0x001000F0004FFC01 }, + { 0x000C04010000FFFF, 0x002000F0004FFC01 }, + { 0x000C04010000FFFF, 0x002000F0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C04200000FFFF, 0x00100030004FFC01 }, + { 0x000C04100000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C144F0000FFFF, 0x00100030004FFC01 }, + { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, + { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x000C149E0000FFFF, 0x00100030004FFC01 }, + { 0x000C149E0000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x00140C050000FFFF, 0x00100030004FFC01 }, + { 0x0014450E0000FFFF, 0x00100030004FFC01 }, + { 0x001424870000FFFF, 0x00100030004FFC01 }, + { 0x0014289E0000FFFF, 0x00000000000FFC00 }, + { 0x0014289E0000FFFF, 0x00000000000FFC00 }, + { 0x0014149E0000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x001004080000FFFF, 0x0000000000000000 }, + { 0x000C00000000FFFF, 0x001000F0004FFC01 }, + { 0x000C00000000FFFF, 0x001000F0004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x001404080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000C04080000FFFF, 0x00100030004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000000000000FFFF, 0x0000000000000000 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x001001D0004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x000C04010000FFFF, 0x00100030004FFC01 }, + { 0x001404010000FFFF, 0x00100030004FFC01 } +}; + +static const struct { + u64 fix; + u64 be; +} g_qoswt_tbl[] = { + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x000C04050000FFFF, 0x0000000000000000 }, + { 0x000C080C0000FFFF, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x000C04050000C001, 0x0000000000000000 }, + { 0x000C080C0000C001, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x001424870000C001, 0x0000000000000000 }, + { 0x001424870000C001, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x001424870000FFFF, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 }, + { 0x0000000000000000, 0x0000000000000000 } +}; + +struct renesas_dbsc5_qos_priv { + void __iomem *regs; +}; + +static int dbsc5_qos_dbsc_setting(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a, *regs_dbsc_d; + unsigned int ch, nch; + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) + nch = 2; + else if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) + nch = 1; + else + return -EINVAL; + + for (ch = 0; ch < nch; ch++) { + regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET + ch * DBSC_A_CH_OFFSET; + regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET + ch * DBSC_D_CH_OFFSET; + + /* DBSC CAM, Scheduling Setting */ + writel(0x1234, regs_dbsc_d + DBSC_SYSCNT0); + writel(0x1234, regs_dbsc_a + DBSC_SYSCNT0); + writel(0x48218, regs_dbsc_a + DBSC_DBCAM0CNF1); + writel(0x1C4, regs_dbsc_a + DBSC_DBCAM0CNF2); + writel(0x3, regs_dbsc_a + DBSC_DBCAM0CNF3); + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && + (renesas_get_cpu_rev_integer() < 2 || + (renesas_get_cpu_rev_integer() == 2 && + renesas_get_cpu_rev_fraction() <= 1))) { + /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ + writel(0x11, regs_dbsc_a + DBSC_DBCAMDIS); + } else { + writel(0x10, regs_dbsc_a + DBSC_DBCAMDIS); + } + + writel(0xF0037, regs_dbsc_a + DBSC_DBSCHCNT0); + writel(0x1, regs_dbsc_a + DBSC_DBSCHSZ0); + writel(0xF7311111, regs_dbsc_a + DBSC_DBSCHRW0); + writel(0x111F1FFF, regs_dbsc_a + DBSC_SCFCTST2); + + /* OTLINT-5579: V4H DBSC WA3 */ + writel(0x7, regs_dbsc_a + DBSC_DBBUS0CNF2); + + /* DBSC QoS Setting */ + writel(0xFFFF, regs_dbsc_a + DBSC_DBSCHQOS_0_0); + writel(0x480, regs_dbsc_a + DBSC_DBSCHQOS_0_1); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_0_2); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_0_3); + writel(0x400, regs_dbsc_a + DBSC_DBSCHQOS_4_0); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_4_1); + writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_4_2); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_4_3); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_9_0); + writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_9_1); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_9_2); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_9_3); + writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_12_0); + writel(0x30, regs_dbsc_a + DBSC_DBSCHQOS_12_1); + writel(0x20, regs_dbsc_a + DBSC_DBSCHQOS_12_2); + writel(0x10, regs_dbsc_a + DBSC_DBSCHQOS_12_3); + writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_13_0); + writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_13_1); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_13_2); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_13_3); + writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_14_0); + writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_14_1); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_14_2); + writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_14_3); + writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_15_0); + writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_15_1); + writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_15_2); + writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_15_3); + + /* Target register is only DBSC0 side. */ + if (ch == 0) + writel(0x1, regs_dbsc_a + DBSC_FCPRSCTRL); + + writel(0x1, regs_dbsc_a + DBSC_SYSCNT1); + writel(0x0, regs_dbsc_d + DBSC_SYSCNT0); + writel(0x0, regs_dbsc_a + DBSC_SYSCNT0); + } + + return 0; +} + +static int dbsc5_qos_settings_init(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + void __iomem *regs_axmm = priv->regs + DBSC5_AXMM_OFFSET; + void __iomem *regs_cci = priv->regs + DBSC5_CCI_OFFSET; + void __iomem *regs_qos = priv->regs + DBSC5_QOS_OFFSET; + int i; + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { + /* Address Split 2ch */ + writel(0x0, regs_axmm + AXMM_ADSPLCR0); + writel(0xFF1B0C, regs_axmm + AXMM_ADSPLCR1); + writel(0x0, regs_axmm + AXMM_ADSPLCR2); + writel(0x0, regs_axmm + AXMM_ADSPLCR3); + + writel(0x8000000, regs_cci + CCIQOS00); + writel(0x8000000, regs_cci + CCIQOS01); + + if (renesas_get_cpu_rev_integer() >= 2) { + writel(0x1, regs_cci + CCIQOS10); + writel(0x1, regs_cci + CCIQOS11); + } else { + writel(0x0, regs_cci + CCIQOS10); + writel(0x0, regs_cci + CCIQOS11); + } + + /* Resource Alloc setting */ + writel(0x48, regs_qos + QOS_RAS); + } else if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { + /* Resource Alloc setting */ + writel(0x30, regs_qos + QOS_RAS); + } else { + return -EINVAL; + } + + writel(0x2020201, regs_qos + QOS_DANN_LOW); + writel(0x4040200, regs_qos + QOS_DANN_HIGH); + writel(0x181008, regs_qos + QOS_DANT); + writel(0x0, regs_qos + QOS_EMS_LOW); + writel(0x0, regs_qos + QOS_EMS_HIGH); + writel(0xA, regs_qos + QOS_FSS); + writel(0x30F0001, regs_qos + QOS_INSFC); + writel(0x0, regs_qos + QOS_EARLYR); + writel(0x50003, regs_qos + QOS_RACNT0); + writel(0x0, regs_qos + QOS_STATGEN0); + + /* QoS MSTAT setting */ + writel(0x70120, regs_qos + QOS_SL_INIT); + writel(0x11B0000, regs_qos + QOS_REF_ARS); + writel(0x12, regs_qos + QOS_REF_ENBL); + writel(0x4, regs_qos + QOS_BWG); + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && + (renesas_get_cpu_rev_integer() < 2 || + (renesas_get_cpu_rev_integer() == 2 && + renesas_get_cpu_rev_fraction() <= 1))) { + /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ + writel(0x0, regs_axmm + AXMM_MMCR); + } else { + writel(0x10000, regs_axmm + AXMM_MMCR); + } + + writel(0x3, ACTEXT_RT0_R); + writel(0x3, ACTEXT_RT0_W); + + /* + * This may be necessary, but this IP is powered off at this point: + * writel(0x3, ACTEXT_IR0_R); + * writel(0x3, ACTEXT_IR0_W); + * writel(0x3, ACTEXT_IR1_R); + * writel(0x3, ACTEXT_IR1_W); + */ + + if (IS_ENABLED(CONFIG_R8A779G0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { + writel(0x10000, regs_axmm + AXMM_TR3CR); + + if (renesas_get_cpu_rev_integer() >= 2) { + /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ + writel(0x38, SI0_RW_MAX); + writel(0x38, SI1_RW_MAX); + } + } + + if (IS_ENABLED(CONFIG_R8A779H0) && + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { + writel(0x0, regs_axmm + AXMM_TR0CR0); + writel(0x0, regs_axmm + AXMM_TR1CR0); + writel(0x0, regs_axmm + AXMM_TR2CR0); + writel(0x0, regs_axmm + AXMM_TR3CR0); + writel(0x70707070, regs_axmm + AXMM_TR0CR1); + writel(0x70707070, regs_axmm + AXMM_TR1CR1); + writel(0x70707070, regs_axmm + AXMM_TR2CR1); + writel(0x70707070, regs_axmm + AXMM_TR3CR1); + writel(0x70707070, regs_axmm + AXMM_TR0CR2); + writel(0x70707070, regs_axmm + AXMM_TR1CR2); + writel(0x70707070, regs_axmm + AXMM_TR2CR2); + writel(0x70707070, regs_axmm + AXMM_TR3CR2); + } + + for (i = 0U; i < ARRAY_SIZE(g_qosbw_tbl); i++) { + writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK0 + (i * 8)); + writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK1 + (i * 8)); + writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK0 + (i * 8)); + writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK1 + (i * 8)); + } + + for (i = 0U; i < ARRAY_SIZE(g_qoswt_tbl); i++) { + writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK0 + (i * 8)); + writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK1 + (i * 8)); + writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK0 + (i * 8)); + writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK1 + (i * 8)); + } + + /* QoS SRAM setting */ + writel(0x1, regs_qos + QOS_RAEN); + writel(0x2080208, regs_qos + QOSWT_WTREF); + writel(0xD90050F, regs_qos + QOSWT_WTSET0); + writel(0xD90050F, regs_qos + QOSWT_WTSET1); + writel(0x1, regs_qos + QOSWT_WTEN); + writel(0x101, regs_qos + QOS_STATQC); + + return 0; +} + +static int renesas_dbsc5_qos_probe(struct udevice *dev) +{ + int ret; + + /* Setting the register of DBSC4 for QoS initialize */ + ret = dbsc5_qos_dbsc_setting(dev); + if (ret) + return ret; + + return dbsc5_qos_settings_init(dev); +} + +static int renesas_dbsc5_qos_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(renesas_dbsc5_qos) = { + .name = "dbsc5_qos", + .id = UCLASS_NOP, + .of_to_plat = renesas_dbsc5_qos_of_to_plat, + .probe = renesas_dbsc5_qos_probe, + .priv_auto = sizeof(struct renesas_dbsc5_qos_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/rtvram.c b/drivers/ram/renesas/dbsc5/rtvram.c new file mode 100644 index 00000000000..6c149284bc6 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/rtvram.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <ram.h> +#include <linux/sizes.h> + +/* RT-VRAM register base address */ +#define RTVRAM_VBUF_CFG 0x6504 +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1 << 8) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6 << 0) +#define RTVRAM_EXT_MODE 0x8500 +#define RTVRAM_EXT_MODE_EXT BIT(0) +#define RTVRAM_VBUF_BADDR 0xC580 + +#define RTVRAM_VBUF_NUM 7 + +#define SDRAM_40BIT_ADDR_TOP 0x0400000000ULL +#define RTVRAM_VBUF_AREA_SIZE SZ_4M + +struct renesas_dbsc5_rtvram_priv { + void __iomem *regs; +}; + +static int renesas_dbsc5_rtvram_probe(struct udevice *dev) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + u64 addr; + int i; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for (i = 0; i < RTVRAM_VBUF_NUM; i++) { + addr = (SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * i)) >> 16; + writel(lower_32_bits(addr), priv->regs + (RTVRAM_VBUF_BADDR + (4 * i))); + } + + /* Cache Mode: 8-way, VBF size: 28M */ + setbits_le32(priv->regs + RTVRAM_VBUF_CFG, + RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); + + /* Change from Compatible Mode to Extended Mode */ + writel(RTVRAM_EXT_MODE_EXT, priv->regs + RTVRAM_EXT_MODE); + + dsb(); + + return 0; +} + +static int renesas_dbsc5_rtvram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static int renesas_dbsc5_rtvram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct renesas_dbsc5_rtvram_priv *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->regs; + info->size = 28 * SZ_1M; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_rtvram_ops = { + .get_info = renesas_dbsc5_rtvram_get_info, +}; + +static const struct udevice_id renesas_dbsc5_rtvram_ids[] = { + { .compatible = "renesas,r8a779g0-rtvram" }, + { .compatible = "renesas,r8a779h0-rtvram" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5_rtvram) = { + .name = "rtvram", + .id = UCLASS_RAM, + .of_match = renesas_dbsc5_rtvram_ids, + .of_to_plat = renesas_dbsc5_rtvram_of_to_plat, + .ops = &renesas_dbsc5_rtvram_ops, + .probe = renesas_dbsc5_rtvram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_rtvram_priv), +}; diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a49802c1323..2790b168b19 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -22,6 +22,14 @@ config K3_SYSTEM_CONTROLLER help Say 'y' here to add support for TI' K3 System Controller. +config REMOTEPROC_RENESAS_APMU + bool "Support for Renesas R-Car Gen4 APMU start of CR52 processor" + select REMOTEPROC + depends on ARCH_RENESAS && RCAR_GEN4 && DM && OF_CONTROL + help + Say 'y' here to add support for Renesas R-Car Gen4 Cortex-A52 + processor via the remoteproc framework. + config REMOTEPROC_SANDBOX bool "Support for Test processor for Sandbox" select REMOTEPROC diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 801b0965e4f..3a092b7660e 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o # Remote proc drivers - Please keep this list alphabetically sorted. obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o +obj-$(CONFIG_REMOTEPROC_RENESAS_APMU) += renesas_apmu.o obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o diff --git a/drivers/remoteproc/renesas_apmu.c b/drivers/remoteproc/renesas_apmu.c new file mode 100644 index 00000000000..32d138e6487 --- /dev/null +++ b/drivers/remoteproc/renesas_apmu.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <errno.h> +#include <hang.h> +#include <linux/iopoll.h> +#include <linux/sizes.h> +#include <malloc.h> +#include <remoteproc.h> + +/* R-Car V4H/V4M contain 3 clusters / 3 cores */ +#define RCAR4_CR52_CORES 3 + +/* Reset Control Register for Cortex-R52 #n */ +#define APMU_CRRSTCTRL(n) (0x304 + ((n) * 0x40)) +#define APMU_CRRSTCTRL_CR52RST BIT(0) + +/* Base Address Register for Cortex-R52 #n */ +#define APMU_CRBARP(n) (0x33c + ((n) * 0x40)) +#define APMU_CRBARP_CR_VLD_BARP BIT(0) +#define APMU_CRBARP_CR_BAREN_VALID BIT(4) +#define APMU_CRBARP_CR_RBAR_MASK 0xfffc0000 +#define APMU_CRBARP_CR_RBAR_ALIGN 0x40000 + +/** + * struct renesas_apmu_rproc_privdata - remote processor private data + * @regs: controller registers + * @core_id: CPU core id + * @trampoline: jump trampoline code + */ +struct renesas_apmu_rproc_privdata { + void __iomem *regs; + ulong core_id; + u32 *trampoline; +}; + +/* + * CRBARP address is aligned to 0x40000 / 256 kiB , this trampoline + * allows arbitrary address alignment at instruction granularity. + */ +static const u32 renesas_apmu_rproc_trampoline[4] = { + 0xe59f0004, /* ldr r0, [pc, #4] */ + 0xe1a0f000, /* mov pc, r0 */ + 0xeafffffe, /* 1: b 1b */ + 0xabcd1234 /* jump target (rewritten on load) */ +}; + +/** + * renesas_apmu_rproc_load() - Load the remote processor + * @dev: corresponding remote processor device + * @addr: Address in memory where image is stored + * @size: Size in bytes of the image + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + u32 trampolineaddr = (u32)(uintptr_t)(priv->trampoline); + + priv->trampoline[3] = addr; + flush_dcache_range(trampolineaddr, + trampolineaddr + + sizeof(renesas_apmu_rproc_trampoline)); + + /* CR52 boot address set */ + writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP, + priv->regs + APMU_CRBARP(priv->core_id)); + writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP | APMU_CRBARP_CR_BAREN_VALID, + priv->regs + APMU_CRBARP(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_start() - Start the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_start(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* Clear APMU_CRRSTCTRL_CR52RST, the only bit in this register */ + writel(0, priv->regs + APMU_CRRSTCTRL(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_stop() - Stop the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_stop(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* Set APMU_CRRSTCTRL_CR52RST, the only bit in this register */ + writel(APMU_CRRSTCTRL_CR52RST, + priv->regs + APMU_CRRSTCTRL(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_reset() - Reset the remote processor + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_reset(struct udevice *dev) +{ + renesas_apmu_rproc_stop(dev); + renesas_apmu_rproc_start(dev); + return 0; +} + +/** + * renesas_apmu_rproc_is_running() - Is the remote processor running + * @dev: corresponding remote processor device + * + * Return: 0 if the remote processor is running, 1 otherwise + */ +static int renesas_apmu_rproc_is_running(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + return readl(priv->regs + APMU_CRRSTCTRL(priv->core_id)) & + APMU_CRRSTCTRL_CR52RST; +} + +/** + * renesas_apmu_rproc_init() - Initialize the remote processor CRBAR registers + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_init(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + /* If the core is running already, do nothing. */ + if (renesas_apmu_rproc_is_running(dev)) + return 0; + + /* Clear and invalidate CRBARP content */ + writel(0, priv->regs + APMU_CRBARP(priv->core_id)); + + return 0; +} + +/** + * renesas_apmu_rproc_device_to_virt() - Convert device address to virtual address + * @dev: corresponding remote processor device + * @da: device address + * @size: Size of the memory region @da is pointing to + * + * Return: converted virtual address + */ +static void *renesas_apmu_rproc_device_to_virt(struct udevice *dev, ulong da, + ulong size) +{ + /* + * The Cortex R52 and A76 share the same address space, + * this operation is a no-op. + */ + return (void *)da; +} + +static const struct dm_rproc_ops renesas_apmu_rproc_ops = { + .init = renesas_apmu_rproc_init, + .load = renesas_apmu_rproc_load, + .start = renesas_apmu_rproc_start, + .stop = renesas_apmu_rproc_stop, + .reset = renesas_apmu_rproc_reset, + .is_running = renesas_apmu_rproc_is_running, + .device_to_virt = renesas_apmu_rproc_device_to_virt, +}; + +/** + * renesas_apmu_rproc_of_to_plat() - Convert OF data to platform data + * @dev: corresponding remote processor device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_of_to_plat(struct udevice *dev) +{ + struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev); + + priv->core_id = dev_get_driver_data(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + priv->trampoline = memalign(APMU_CRBARP_CR_RBAR_ALIGN, + sizeof(renesas_apmu_rproc_trampoline)); + if (!priv->trampoline) + return -ENOMEM; + + memcpy(priv->trampoline, renesas_apmu_rproc_trampoline, + sizeof(renesas_apmu_rproc_trampoline)); + + return 0; +} + +U_BOOT_DRIVER(renesas_apmu_cr52) = { + .name = "rcar-apmu-cr52", + .id = UCLASS_REMOTEPROC, + .ops = &renesas_apmu_rproc_ops, + .of_to_plat = renesas_apmu_rproc_of_to_plat, + .priv_auto = sizeof(struct renesas_apmu_rproc_privdata), +}; + +/** + * renesas_apmu_rproc_bind() - Bind rproc driver to each core control + * @dev: corresponding remote processor parent device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_apmu_rproc_bind(struct udevice *parent) +{ + const ulong cr52cores = RCAR4_CR52_CORES; + ofnode pnode = dev_ofnode(parent); + struct udevice *cdev; + struct driver *cdrv; + char name[32]; + ulong i; + int ret; + + cdrv = lists_driver_lookup_name("rcar-apmu-cr52"); + if (!cdrv) + return -ENOENT; + + for (i = 0; i < cr52cores; i++) { + snprintf(name, sizeof(name), "rcar-apmu-cr52.%ld", i); + ret = device_bind_with_driver_data(parent, cdrv, strdup(name), + i, pnode, &cdev); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id renesas_apmu_rproc_ids[] = { + { .compatible = "renesas,r8a779g0-cr52" }, + { .compatible = "renesas,r8a779h0-cr52" }, + { } +}; + +U_BOOT_DRIVER(renesas_apmu_rproc) = { + .name = "rcar-apmu-rproc", + .of_match = renesas_apmu_rproc_ids, + .id = UCLASS_NOP, + .bind = renesas_apmu_rproc_bind, +}; diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c index 658c153d3ed..f790d3b60f9 100644 --- a/drivers/rng/msm_rng.c +++ b/drivers/rng/msm_rng.c @@ -34,6 +34,7 @@ struct msm_rng_priv { phys_addr_t base; struct clk clk; + bool skip_init; }; static int msm_rng_read(struct udevice *dev, void *data, size_t len) @@ -100,10 +101,15 @@ static int msm_rng_probe(struct udevice *dev) int ret; + priv->skip_init = (bool)dev_get_driver_data(dev); + priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; + if (priv->skip_init) + return 0; + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) return ret; @@ -119,6 +125,9 @@ static int msm_rng_remove(struct udevice *dev) { struct msm_rng_priv *priv = dev_get_priv(dev); + if (priv->skip_init) + return 0; + return msm_rng_enable(priv, 0); } @@ -127,7 +136,9 @@ static const struct dm_rng_ops msm_rng_ops = { }; static const struct udevice_id msm_rng_match[] = { - { .compatible = "qcom,prng", }, + { .compatible = "qcom,prng", .data = (ulong)false }, + { .compatible = "qcom,prng-ee", .data = (ulong)true }, + { .compatible = "qcom,trng", .data = (ulong)true }, {}, }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 9c2d1398247..6467f20422b 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -294,7 +294,7 @@ config RTC_DAVINCI config RTC_ZYNQMP bool "Enable ZynqMP RTC driver" - depends on ARCH_ZYNQMP + depends on DM_RTC && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) help Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 7e21c4ae2bb..fc87d34cca3 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,5 +1,6 @@ config SCSI bool "Support SCSI controllers with driver model" + select BLK help This enables support for SCSI (Small Computer System Interface), a parallel interface widely used with storage peripherals such as diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b27ad9a77e..c4f4a8d78df 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -920,7 +920,7 @@ config SCIF_CONSOLE depends on SH || ARCH_RENESAS help Select this to enable Renesas SCIF UART. To operate serial ports - on systems with RCar or SH SoCs, say Y to this option. If unsure, + on systems with R-Car or SH SoCs, say Y to this option. If unsure, say N. choice diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fd5cb3694f6..96ea033082b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -420,7 +420,7 @@ config RENESAS_RPC_SPI imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash - on Renesas RCar Gen3 SoCs. This uses driver model and requires a + on Renesas R-Car Gen3 SoCs. This uses driver model and requires a device tree binding to operate. config ROCKCHIP_SFC diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h deleted file mode 100644 index 9663cca5e66..00000000000 --- a/drivers/spi/atmel_spi.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Register definitions for the Atmel AT32/AT91 SPI Controller - */ - -/* Register offsets */ -#include <linux/bitops.h> -#define ATMEL_SPI_CR 0x0000 -#define ATMEL_SPI_MR 0x0004 -#define ATMEL_SPI_RDR 0x0008 -#define ATMEL_SPI_TDR 0x000c -#define ATMEL_SPI_SR 0x0010 -#define ATMEL_SPI_IER 0x0014 -#define ATMEL_SPI_IDR 0x0018 -#define ATMEL_SPI_IMR 0x001c -#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) -#define ATMEL_SPI_VERSION 0x00fc - -/* Bits in CR */ -#define ATMEL_SPI_CR_SPIEN BIT(0) -#define ATMEL_SPI_CR_SPIDIS BIT(1) -#define ATMEL_SPI_CR_SWRST BIT(7) -#define ATMEL_SPI_CR_LASTXFER BIT(24) - -/* Bits in MR */ -#define ATMEL_SPI_MR_MSTR BIT(0) -#define ATMEL_SPI_MR_PS BIT(1) -#define ATMEL_SPI_MR_PCSDEC BIT(2) -#define ATMEL_SPI_MR_FDIV BIT(3) -#define ATMEL_SPI_MR_MODFDIS BIT(4) -#define ATMEL_SPI_MR_WDRBT BIT(5) -#define ATMEL_SPI_MR_LLB BIT(7) -#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) -#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) - -/* Bits in RDR */ -#define ATMEL_SPI_RDR_RD(x) (x) -#define ATMEL_SPI_RDR_PCS(x) ((x) << 16) - -/* Bits in TDR */ -#define ATMEL_SPI_TDR_TD(x) (x) -#define ATMEL_SPI_TDR_PCS(x) ((x) << 16) -#define ATMEL_SPI_TDR_LASTXFER BIT(24) - -/* Bits in SR/IER/IDR/IMR */ -#define ATMEL_SPI_SR_RDRF BIT(0) -#define ATMEL_SPI_SR_TDRE BIT(1) -#define ATMEL_SPI_SR_MODF BIT(2) -#define ATMEL_SPI_SR_OVRES BIT(3) -#define ATMEL_SPI_SR_ENDRX BIT(4) -#define ATMEL_SPI_SR_ENDTX BIT(5) -#define ATMEL_SPI_SR_RXBUFF BIT(6) -#define ATMEL_SPI_SR_TXBUFE BIT(7) -#define ATMEL_SPI_SR_NSSR BIT(8) -#define ATMEL_SPI_SR_TXEMPTY BIT(9) -#define ATMEL_SPI_SR_SPIENS BIT(16) - -/* Bits in CSRx */ -#define ATMEL_SPI_CSRx_CPOL BIT(0) -#define ATMEL_SPI_CSRx_NCPHA BIT(1) -#define ATMEL_SPI_CSRx_CSAAT BIT(3) -#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) -#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) -#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) -#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) -#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) - -/* Bits in VERSION */ -#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff) -#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) - -/* Constants for CSRx:BITS */ -#define ATMEL_SPI_BITS_8 0 -#define ATMEL_SPI_BITS_9 1 -#define ATMEL_SPI_BITS_10 2 -#define ATMEL_SPI_BITS_11 3 -#define ATMEL_SPI_BITS_12 4 -#define ATMEL_SPI_BITS_13 5 -#define ATMEL_SPI_BITS_14 6 -#define ATMEL_SPI_BITS_15 7 -#define ATMEL_SPI_BITS_16 8 - -/* Register access macros */ -#define spi_readl(as, reg) \ - readl(as->regs + ATMEL_SPI_##reg) -#define spi_writel(as, reg, value) \ - writel(value, as->regs + ATMEL_SPI_##reg) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 93ab2b5635f..f2f69cf9f12 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -151,9 +151,9 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv, /* Return 1 if idle, otherwise return 0 (busy). */ static unsigned int cadence_qspi_wait_idle(void *reg_base) { - unsigned int start, count = 0; + unsigned long start, count = 0; /* timeout in unit of ms */ - unsigned int timeout = 5000; + unsigned long timeout = 5000; start = get_timer(0); for ( ; get_timer(start) < timeout ; ) { @@ -170,7 +170,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } /* Timeout, still in busy mode. */ - printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); + printf("QSPI: QSPI is still busy after poll for %lu ms.\n", timeout); return 0; } diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 9ab39a188b2..2c9b0ada87b 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -115,6 +115,9 @@ struct mxc_spi_slave { #if defined(MXC_ECSPI) u32 cfg_reg; #endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif int gpio; int ss_pol; unsigned int max_hz; @@ -214,7 +217,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) #ifdef MXC_ECSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { +#if CONFIG_IS_ENABLED(CLK) + u32 clk_src = clk_get_rate(&mxcs->clk); +#else u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); +#endif s32 reg_ctrl, reg_config; u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; u32 pre_div = 0, post_div = 0; @@ -599,14 +606,13 @@ static int mxc_spi_probe(struct udevice *bus) return -ENODEV; #if CONFIG_IS_ENABLED(CLK) - struct clk clk; - ret = clk_get_by_index(bus, 0, &clk); + ret = clk_get_by_index(bus, 0, &mxcs->clk); if (ret) return ret; - clk_enable(&clk); + clk_enable(&mxcs->clk); - mxcs->max_hz = clk_get_rate(&clk); + mxcs->max_hz = clk_get_rate(&mxcs->clk); #else int node = dev_of_offset(bus); const void *blob = gd->fdt_blob; diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index f1e6f9f4e01..7103d786c7e 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 RPC QSPI driver + * Renesas R-Car Gen3 RPC QSPI driver * * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 4251bf28cd3..2a095d0c58e 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -255,7 +255,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) GQSPI_GFIFO_CS_LOWER | GQSPI_GFIFO_CS_UPPER; else - debug("Wrong Bus selection:0x%x\n", priv->bus); + log_debug("Wrong Bus selection:0x%x\n", priv->bus); } else { if (priv->u_page) gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | diff --git a/drivers/sysinfo/sandbox.c b/drivers/sysinfo/sandbox.c index d39720958f0..af54fe87596 100644 --- a/drivers/sysinfo/sandbox.c +++ b/drivers/sysinfo/sandbox.c @@ -13,6 +13,7 @@ struct sysinfo_sandbox_priv { bool called_detect; int test_i1; int test_i2; + u32 test_data[2]; }; char vacation_spots[][64] = {"R'lyeh", "Dreamlands", "Plateau of Leng", @@ -24,6 +25,8 @@ int sysinfo_sandbox_detect(struct udevice *dev) priv->called_detect = true; priv->test_i2 = 100; + priv->test_data[0] = 0xabcdabcd; + priv->test_data[1] = 0xdeadbeef; return 0; } @@ -79,6 +82,21 @@ int sysinfo_sandbox_get_str(struct udevice *dev, int id, size_t size, char *val) return -ENOENT; } +int sysinfo_sandbox_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_sandbox_priv *priv = dev_get_priv(dev); + + switch (id) { + case DATA_TEST: + *buf = priv->test_data; + *size = sizeof(priv->test_data); + return 0; + } + + return -ENOENT; +} + static const struct udevice_id sysinfo_sandbox_ids[] = { { .compatible = "sandbox,sysinfo-sandbox" }, { /* sentinel */ } @@ -89,6 +107,7 @@ static const struct sysinfo_ops sysinfo_sandbox_ops = { .get_bool = sysinfo_sandbox_get_bool, .get_int = sysinfo_sandbox_get_int, .get_str = sysinfo_sandbox_get_str, + .get_data = sysinfo_sandbox_get_data, }; int sysinfo_sandbox_probe(struct udevice *dev) diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h index a7cbac0ce18..47b7f5ef9fe 100644 --- a/drivers/sysinfo/sandbox.h +++ b/drivers/sysinfo/sandbox.h @@ -9,4 +9,5 @@ enum { INT_TEST1, INT_TEST2, STR_VACATIONSPOT, + DATA_TEST, }; diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index a7ac8e3f072..99104274f72 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -5,14 +5,240 @@ */ #include <dm.h> +#include <smbios_plat.h> #include <sysinfo.h> +/* platform information storage */ +struct processor_info processor_info; +struct cache_info cache_info[SYSINFO_CACHE_LVL_MAX]; +struct sysinfo_plat sysinfo_smbios_p = { + /* Processor Information */ + .processor = &processor_info, + /* Cache Information */ + .cache = &cache_info[0], +}; + +/* structure for smbios private data storage */ +struct sysinfo_plat_priv { + struct processor_info *t4; + struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; + u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; + u8 cache_level; +}; + +static void smbios_cache_info_dump(struct smbios_type7 *cache_info) +{ + log_debug("SMBIOS Type 7 (Cache Information):\n"); + log_debug("Cache Configuration: 0x%04x\n", cache_info->config.data); + log_debug("Maximum Cache Size: %u KB\n", cache_info->max_size.data); + log_debug("Installed Size: %u KB\n", cache_info->inst_size.data); + log_debug("Supported SRAM Type: 0x%04x\n", + cache_info->supp_sram_type.data); + log_debug("Current SRAM Type: 0x%04x\n", + cache_info->curr_sram_type.data); + log_debug("Cache Speed: %u\n", cache_info->speed); + log_debug("Error Correction Type: %u\n", cache_info->err_corr_type); + log_debug("System Cache Type: %u\n", cache_info->sys_cache_type); + log_debug("Associativity: %u\n", cache_info->associativity); + log_debug("Maximum Cache Size 2: %u KB\n", cache_info->max_size2.data); + log_debug("Installed Cache Size 2: %u KB\n", + cache_info->inst_size2.data); +} + +/* weak function for the platforms not yet supported */ +__weak int sysinfo_get_cache_info(u8 level, struct cache_info *cache_info) +{ + return -ENOSYS; +} + +__weak int sysinfo_get_processor_info(struct processor_info *pinfo) +{ + return -ENOSYS; +} + +void sysinfo_cache_info_default(struct cache_info *ci) +{ + memset(ci, 0, sizeof(*ci)); + ci->config.data = SMBIOS_CACHE_LOCATE_UNKNOWN | SMBIOS_CACHE_OP_UND; + ci->supp_sram_type.fields.unknown = 1; + ci->curr_sram_type.fields.unknown = 1; + ci->speed = SMBIOS_CACHE_SPEED_UNKNOWN; + ci->err_corr_type = SMBIOS_CACHE_ERRCORR_UNKNOWN; + ci->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN; +} + +static int sysinfo_plat_detect(struct udevice *dev) +{ + return 0; +} + +static int sysinfo_plat_get_str(struct udevice *dev, int id, + size_t size, char *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + const char *str = NULL; + + switch (id) { + case SYSID_SM_PROCESSOR_MANUFACT: + str = priv->t4->manufacturer; + break; + default: + break; + } + + if (!str) + return -ENOSYS; + + strlcpy(val, str, size); + + return 0; +} + +static int sysinfo_plat_get_int(struct udevice *dev, int id, int *val) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + u8 i; + + if (id >= SYSID_SM_CACHE_INFO_START && + id <= SYSID_SM_CACHE_INFO_END) { + /* For smbios type 7 */ + for (i = 0; i < priv->cache_level; i++) { + switch (id - i) { + case SYSID_SM_CACHE_MAX_SIZE: + *val = priv->t7[i].max_size.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE: + *val = priv->t7[i].inst_size.data; + return 0; + case SYSID_SM_CACHE_SCACHE_TYPE: + *val = priv->t7[i].sys_cache_type; + return 0; + case SYSID_SM_CACHE_ASSOC: + *val = priv->t7[i].associativity; + return 0; + case SYSID_SM_CACHE_MAX_SIZE2: + *val = priv->t7[i].max_size2.data; + return 0; + case SYSID_SM_CACHE_INST_SIZE2: + *val = priv->t7[i].inst_size2.data; + return 0; + default: + break; + } + } + return -ENOSYS; + } + + switch (id) { + case SYSID_SM_PROCESSOR_CORE_CNT: + *val = priv->t4->core_count; + break; + case SYSID_SM_PROCESSOR_CORE_EN: + *val = priv->t4->core_enabled; + break; + case SYSID_SM_PROCESSOR_CHARA: + *val = priv->t4->characteristics; + break; + case SYSID_SM_CACHE_LEVEL: + if (!priv->cache_level) /* No cache detected */ + return -ENOSYS; + *val = priv->cache_level - 1; + break; + default: + return -ENOSYS; + } + + return 0; +} + +static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, + size_t *size) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_SM_PROCESSOR_ID: + *buf = priv->t4->id; + *size = sizeof(priv->t4->id); + break; + case SYSID_SM_CACHE_HANDLE: + *buf = &priv->cache_handles[0]; + *size = sizeof(priv->cache_handles); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static int sysinfo_plat_probe(struct udevice *dev) +{ + struct sysinfo_plat_priv *priv = dev_get_priv(dev); + struct sysinfo_plat *plat = &sysinfo_smbios_p; + u8 level; + + if (!sysinfo_get_processor_info(plat->processor)) + priv->t4 = plat->processor; + + for (level = 0; level < SYSINFO_CACHE_LVL_MAX; level++) { + struct cache_info *pcache = plat->cache + level; + + if (sysinfo_get_cache_info(level, pcache)) + break; /* no more levels */ + + /* + * Fill in the SMBIOS type 7 structure, + * skip the header members (type, length, handle), + * and the ones in DT smbios node. + */ + priv->t7[level].sys_cache_type = pcache->cache_type; + priv->t7[level].associativity = pcache->associativity; + + if (pcache->max_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].max_size.data = 0xFFFF; + priv->t7[level].max_size2.fields.size = + pcache->max_size / 64; + priv->t7[level].max_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].max_size.fields.size = pcache->max_size; + priv->t7[level].max_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].max_size2.data = 0; + } + if (pcache->inst_size > SMBIOS_CACHE_SIZE_EXT_KB) { + priv->t7[level].inst_size.data = 0xFFFF; + priv->t7[level].inst_size2.fields.size = + pcache->inst_size / 64; + priv->t7[level].inst_size2.fields.granu = + SMBIOS_CACHE_GRANU_64K; + } else { + priv->t7[level].inst_size.fields.size = + pcache->inst_size; + priv->t7[level].inst_size.fields.granu = + SMBIOS_CACHE_GRANU_1K; + priv->t7[level].inst_size2.data = 0; + } + smbios_cache_info_dump(&priv->t7[level]); + } + if (!level) /* no cache detected */ + return -ENOSYS; + + priv->cache_level = level; + + return 0; +} + static const struct udevice_id sysinfo_smbios_ids[] = { { .compatible = "u-boot,sysinfo-smbios" }, { /* sentinel */ } }; static const struct sysinfo_ops sysinfo_smbios_ops = { + .detect = sysinfo_plat_detect, + .get_str = sysinfo_plat_get_str, + .get_int = sysinfo_plat_get_int, + .get_data = sysinfo_plat_get_data, }; U_BOOT_DRIVER(sysinfo_smbios) = { @@ -20,4 +246,6 @@ U_BOOT_DRIVER(sysinfo_smbios) = { .id = UCLASS_SYSINFO, .of_match = sysinfo_smbios_ids, .ops = &sysinfo_smbios_ops, + .priv_auto = sizeof(struct sysinfo_plat_priv), + .probe = sysinfo_plat_probe, }; diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index d77d1e3ee44..3c0cd51273e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -99,6 +99,26 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val) return ops->get_str(dev, id, size, val); } +int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_priv *priv; + struct sysinfo_ops *ops; + + if (!dev) + return -ENOSYS; + + priv = dev_get_uclass_priv(dev); + ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_data) + return -ENOSYS; + + return ops->get_data(dev, id, data, size); +} + UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c index 9da74479aaa..f92009e4ccc 100644 --- a/drivers/timer/mpc83xx_timer.c +++ b/drivers/timer/mpc83xx_timer.c @@ -206,7 +206,7 @@ static u64 mpc83xx_timer_get_count(struct udevice *dev) tbl = mftb(); } while (tbu != mftbu()); - return (tbu * 0x10000ULL) + tbl; + return (uint64_t)tbu << 32 | tbl; } static int mpc83xx_timer_probe(struct udevice *dev) diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 960b6a906ac..99c6649e417 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,5 +1,6 @@ menuconfig USB bool "USB support" + select BLK ---help--- Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 010084ef7f3..c815764c2bc 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -115,10 +115,10 @@ config USB_GADGET_DWC2_OTG USB_GADGET to be enabled. config USB_RENESAS_USBHS - bool "Renesas RCar USB2.0 HS controller (gadget mode)" + bool "Renesas R-Car USB2.0 HS controller (gadget mode)" select USB_GADGET_DUALSPEED help - The Renesas Rcar USB 2.0 high-speed gadget controller + The Renesas R-Car USB 2.0 high-speed gadget controller integrated into Salvator and Kingfisher boards. Select this option if you want the driver to operate in Peripheral mode. This option requires USB_GADGET to be enabled. diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bb5893d56db..a656265890e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -103,12 +103,12 @@ config USB_XHCI_PCI Enables support for the PCI-based xHCI controller. config USB_XHCI_RCAR - bool "Renesas RCar USB 3.0 support" + bool "Renesas R-Car USB 3.0 support" default y depends on ARCH_RENESAS help Choose this option to add support for USB 3.0 driver on Renesas - RCar Gen3 SoCs. + R-Car Gen3 SoCs. config USB_XHCI_STI bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" @@ -217,14 +217,14 @@ config USB_EHCI_MX6 Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 - bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 || IMX8M || IMX93 + bool "Support for i.MX7/i.MX8M/i.MX9 on-chip EHCI USB controller" + depends on ARCH_MX7 || IMX8M || IMX93 || IMX95 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7 - select PHY if IMX8M || IMX93 - select NOP_PHY if IMX8M || IMX93 + select PHY if IMX8M || IMX93 || IMX95 + select NOP_PHY if IMX8M || IMX93 || IMX95 default y ---help--- - Enables support for the on-chip EHCI controller on i.MX7 SoCs. + Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS bool "Support for i.MX23/i.MX28 EHCI USB controller" diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index d8f521befe1..1392d29bc13 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -287,9 +287,9 @@ static int ehci_usb_probe(struct udevice *dev) debug("%s: No vbus supply\n", dev->name); if (!ret && priv->vbus_supply) { - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret) { puts("Error enabling VBUS supply\n"); return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a93fa5d5455..a8748cef7ad 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -479,9 +479,9 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { int ret; - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); return ret; diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h index 8db88f0dcfa..7c909b4697a 100644 --- a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h @@ -1,5 +1,5 @@ /* - * Renesas RCar xHCI controller firmware version 3 + * Renesas R-Car xHCI controller firmware version 3 * * Copyright (c) 2014, Renesas Electronics Corporation * All rights reserved. diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 38c5928faed..b72807053c4 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> * - * Renesas RCar USB HOST xHCI Controller + * Renesas R-Car USB HOST xHCI Controller */ #include <clk.h> diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 76abfeac443..52af23c3c83 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -11,6 +11,7 @@ #include <dm.h> #include <errno.h> #include <generic-phy.h> +#include <reset.h> #include <stdlib.h> #include <video.h> #include <wait_bit.h> @@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk resets; struct clk clk; int ret; int mode = RGBA8888; + ret = reset_get_bulk(dev, &resets); + if (!ret) + reset_deassert_bulk(&resets); + ret = clk_get_by_name(dev, "dp_apb_clk", &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index 1de68867d52..512ac376f18 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -64,6 +64,7 @@ config VIRTIO_NET config VIRTIO_BLK bool "virtio block driver" depends on VIRTIO + select BLK help This is the virtual block driver for virtio. It can be used with QEMU based targets. diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 99168d0cad0..7b387266b99 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -131,18 +131,19 @@ static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) u32 timer_margin; int ret; - if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY) + timer_margin = timeout_ms * priv->clk_hz / 1000; + timer_margin >>= WDT_PRELOAD_SHIFT; + if (timer_margin > WDT_PRELOAD_MAX) + timer_margin = WDT_PRELOAD_MAX; + + if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY && + readl(priv->regs + RTIDWDPRLD) != timer_margin) return -EBUSY; ret = rti_wdt_load_fw(dev); if (ret < 0) return ret; - timer_margin = timeout_ms * priv->clk_hz / 1000; - timer_margin >>= WDT_PRELOAD_SHIFT; - if (timer_margin > WDT_PRELOAD_MAX) - timer_margin = WDT_PRELOAD_MAX; - writel(timer_margin, priv->regs + RTIDWDPRLD); writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL); writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL); @@ -186,14 +187,6 @@ static int rti_wdt_probe(struct udevice *dev) priv->clk_hz = clk_get_rate(&clk); - /* - * If watchdog is running at 32k clock, it is not accurate. - * Adjust frequency down in this case so that it does not expire - * earlier than expected. - */ - if (priv->clk_hz < 32768) - priv->clk_hz = priv->clk_hz * 9 / 10; - return 0; } |