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-rw-r--r--dts/upstream/Bindings/display/mediatek/mediatek,od.yaml22
1 files changed, 22 insertions, 0 deletions
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,od.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,od.yaml
index 831c653caff..71534febd49 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,od.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,od.yaml
@@ -38,6 +38,28 @@ properties:
items:
- description: OD Clock
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description:
+ Input and output ports can have multiple endpoints, each of those
+ connects to either the primary, secondary, etc, display pipeline.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: OD input port, usually from an AAL block
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ OD output to the input of the next desired component in the
+ display pipeline, for example one of the available RDMA or
+ other blocks.
+
+ required:
+ - port@0
+ - port@1
+
required:
- compatible
- reg