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-rw-r--r--dts/upstream/src/arm64/qcom/sa8775p.dtsi706
1 files changed, 607 insertions, 99 deletions
diff --git a/dts/upstream/src/arm64/qcom/sa8775p.dtsi b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
index e8dbc8d820a..9da62d7c4d2 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -8,6 +9,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -37,21 +39,21 @@
#address-cells = <2>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
- L3_0: l3-cache {
+ next-level-cache = <&l3_0>;
+ l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -59,72 +61,72 @@
};
};
- CPU1: cpu@100 {
+ cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_1: l2-cache {
+ l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU2: cpu@200 {
+ cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- next-level-cache = <&L2_2>;
+ next-level-cache = <&l2_2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_2: l2-cache {
+ l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU3: cpu@300 {
+ cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
- next-level-cache = <&L2_3>;
+ next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_3: l2-cache {
+ l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_0>;
+ next-level-cache = <&l3_0>;
};
};
- CPU4: cpu@10000 {
+ cpu4: cpu@10000 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10000>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- next-level-cache = <&L2_4>;
+ next-level-cache = <&l2_4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_4: l2-cache {
+ l2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_1>;
- L3_1: l3-cache {
+ next-level-cache = <&l3_1>;
+ l3_1: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -133,91 +135,91 @@
};
};
- CPU5: cpu@10100 {
+ cpu5: cpu@10100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10100>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- next-level-cache = <&L2_5>;
+ next-level-cache = <&l2_5>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_5: l2-cache {
+ l2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_1>;
+ next-level-cache = <&l3_1>;
};
};
- CPU6: cpu@10200 {
+ cpu6: cpu@10200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10200>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- next-level-cache = <&L2_6>;
+ next-level-cache = <&l2_6>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_6: l2-cache {
+ l2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_1>;
+ next-level-cache = <&l3_1>;
};
};
- CPU7: cpu@10300 {
+ cpu7: cpu@10300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10300>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
- next-level-cache = <&L2_7>;
+ next-level-cache = <&l2_7>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
- L2_7: l2-cache {
+ l2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
- next-level-cache = <&L3_1>;
+ next-level-cache = <&l3_1>;
};
};
cpu-map {
cluster0 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
core2 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core3 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
};
cluster1 {
core0 {
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
};
core1 {
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
};
core2 {
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
};
core3 {
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
};
};
};
@@ -225,7 +227,7 @@
idle-states {
entry-method = "psci";
- GOLD_CPU_SLEEP_0: cpu-sleep-0 {
+ gold_cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-power-collapse";
arm,psci-suspend-param = <0x40000003>;
@@ -235,7 +237,7 @@
local-timer-stop;
};
- GOLD_RAIL_CPU_SLEEP_0: cpu-sleep-1 {
+ gold_rail_cpu_sleep_0: cpu-sleep-1 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
@@ -247,7 +249,7 @@
};
domain-idle-states {
- CLUSTER_SLEEP_GOLD: cluster-sleep-0 {
+ cluster_sleep_gold: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
@@ -255,7 +257,7 @@
min-residency-us = <6118>;
};
- CLUSTER_SLEEP_APSS_RSC_PC: cluster-sleep-1 {
+ cluster_sleep_apss_rsc_pc: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x42000144>;
entry-latency-us = <3263>;
@@ -281,6 +283,7 @@
firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
memory-region = <&tz_ffi_mem>;
};
};
@@ -393,77 +396,77 @@
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: power-domain-cpu0 {
+ cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_0_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_0_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD1: power-domain-cpu1 {
+ cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_0_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_0_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD2: power-domain-cpu2 {
+ cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_0_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_0_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD3: power-domain-cpu3 {
+ cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_0_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_0_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD4: power-domain-cpu4 {
+ cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_1_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_1_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD5: power-domain-cpu5 {
+ cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_1_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_1_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD6: power-domain-cpu6 {
+ cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_1_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_1_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CPU_PD7: power-domain-cpu7 {
+ cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_1_PD>;
- domain-idle-states = <&GOLD_CPU_SLEEP_0>,
- <&GOLD_RAIL_CPU_SLEEP_0>;
+ power-domains = <&cluster_1_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>,
+ <&gold_rail_cpu_sleep_0>;
};
- CLUSTER_0_PD: power-domain-cluster0 {
+ cluster_0_pd: power-domain-cluster0 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_2_PD>;
- domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
+ power-domains = <&cluster_2_pd>;
+ domain-idle-states = <&cluster_sleep_gold>;
};
- CLUSTER_1_PD: power-domain-cluster1 {
+ cluster_1_pd: power-domain-cluster1 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_2_PD>;
- domain-idle-states = <&CLUSTER_SLEEP_GOLD>;
+ power-domains = <&cluster_2_pd>;
+ domain-idle-states = <&cluster_sleep_gold>;
};
- CLUSTER_2_PD: power-domain-cluster2 {
+ cluster_2_pd: power-domain-cluster2 {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_SLEEP_APSS_RSC_PC>;
+ domain-idle-states = <&cluster_sleep_apss_rsc_pc>;
};
};
@@ -851,6 +854,28 @@
#mbox-cells = <2>;
};
+ gpi_dma2: qcom,gpi-dma@800000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+ #dma-cells = <3>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0xfff>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -881,6 +906,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -902,6 +931,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart14: serial@880000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -923,6 +971,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -944,6 +996,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart15: serial@884000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -965,6 +1036,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -984,11 +1059,30 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ uart16: serial@888000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c17: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x88c000 0x0 0x4000>;
@@ -1007,6 +1101,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1028,6 +1126,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1062,6 +1164,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1085,6 +1191,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart18: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1106,6 +1231,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1127,6 +1256,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart19: serial@894000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00894000 0x0 0x4000>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1148,6 +1296,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1169,8 +1321,50 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
+
+ uart20: serial@898000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00898000 0x0 0x4000>;
+ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
+ };
+
+ gpi_dma0: qcom,gpi-dma@900000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00900000 0x0 0x60000>;
+ #dma-cells = <3>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0xfff>;
+ iommus = <&apps_smmu 0x416 0x0>;
+ status = "disabled";
};
qupv3_id_0: geniqup@9c0000 {
@@ -1203,6 +1397,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1224,6 +1422,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x980000 0x0 0x4000>;
+ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1245,6 +1462,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1266,6 +1487,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1287,6 +1527,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1308,6 +1552,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1329,6 +1592,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1350,6 +1617,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1371,6 +1657,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1392,6 +1682,25 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
@@ -1413,6 +1722,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1434,6 +1747,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1453,6 +1770,28 @@
};
};
+ gpi_dma1: qcom,gpi-dma@a00000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+ #dma-cells = <3>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x456 0x0>;
+ dma-channels = <12>;
+ dma-channel-mask = <0xfff>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -1483,6 +1822,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1504,6 +1847,26 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart7: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -1525,6 +1888,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1546,6 +1913,26 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart8: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -1567,6 +1954,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1588,6 +1979,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1624,6 +2019,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1645,6 +2044,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1682,6 +2085,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1703,6 +2110,26 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart11: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
@@ -1724,6 +2151,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1745,6 +2176,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1781,10 +2216,29 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
+
};
};
+ gpi_dma3: qcom,gpi-dma@b00000 {
+ compatible = "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00b00000 0x0 0x58000>;
+ #dma-cells = <3>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x056 0x0>;
+ dma-channels = <4>;
+ dma-channel-mask = <0xf>;
+ status = "disabled";
+ };
+
qupv3_id_3: geniqup@bc0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0xbc0000 0x0 0x6000>;
@@ -1815,6 +2269,10 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma3 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
status = "disabled";
};
@@ -1836,6 +2294,26 @@
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
+ dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma3 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+ status = "disabled";
+ };
+
+ uart21: serial@b80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00b80000 0x0 0x4000>;
+ interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
+ interconnect-names = "qup-core", "qup-config";
+ interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>;
+ power-domains = <&rpmhpd SA8775P_CX>;
+ operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
};
@@ -1845,7 +2323,7 @@
reg = <0 0x010d2000 0 0x1000>;
};
- ufs_mem_hc: ufs@1d84000 {
+ ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@@ -1908,10 +2386,32 @@
ice: crypto@1d88000 {
compatible = "qcom,sa8775p-inline-crypto-engine",
"qcom,inline-crypto-engine";
- reg = <0x0 0x01d88000 0x0 0x8000>;
+ reg = <0x0 0x01d88000 0x0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x28000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ iommus = <&apps_smmu 0x480 0x00>,
+ <&apps_smmu 0x481 0x00>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sa8775p-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x480 0x00>,
+ <&apps_smmu 0x481 0x00>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "memory";
+ };
+
stm: stm@4002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x4002000 0x0 0x1000>,
@@ -1940,6 +2440,7 @@
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
+ status = "disabled";
out-ports {
port {
@@ -2382,7 +2883,7 @@
etm@6040000 {
compatible = "arm,primecell";
reg = <0x0 0x6040000 0x0 0x1000>;
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2402,7 +2903,7 @@
etm@6140000 {
compatible = "arm,primecell";
reg = <0x0 0x6140000 0x0 0x1000>;
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2422,7 +2923,7 @@
etm@6240000 {
compatible = "arm,primecell";
reg = <0x0 0x6240000 0x0 0x1000>;
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2442,7 +2943,7 @@
etm@6340000 {
compatible = "arm,primecell";
reg = <0x0 0x6340000 0x0 0x1000>;
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2462,7 +2963,7 @@
etm@6440000 {
compatible = "arm,primecell";
reg = <0x0 0x6440000 0x0 0x1000>;
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2482,7 +2983,7 @@
etm@6540000 {
compatible = "arm,primecell";
reg = <0x0 0x6540000 0x0 0x1000>;
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2502,7 +3003,7 @@
etm@6640000 {
compatible = "arm,primecell";
reg = <0x0 0x6640000 0x0 0x1000>;
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2522,7 +3023,7 @@
etm@6740000 {
compatible = "arm,primecell";
reg = <0x0 0x6740000 0x0 0x1000>;
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -3072,6 +3573,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sa8775p-tcsr", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sa8775p-gpucc";
reg = <0x0 0x03d90000 0x0 0xa000>;
@@ -5570,7 +6076,7 @@
status = "disabled";
- pcie@0 {
+ pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -5587,7 +6093,7 @@
<0x0 0x40000000 0x0 0xf20>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x4000>,
- <0x0 0x40200000 0x0 0x100000>,
+ <0x0 0x40200000 0x0 0x1fe00000>,
<0x0 0x01c03000 0x0 0x1000>,
<0x0 0x40005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
@@ -5624,6 +6130,7 @@
phy-names = "pciephy";
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
num-lanes = <2>;
+ linux,pci-domain = <0>;
status = "disabled";
};
@@ -5744,7 +6251,7 @@
<0x0 0x60000000 0x0 0xf20>,
<0x0 0x60000f20 0x0 0xa8>,
<0x0 0x60001000 0x0 0x4000>,
- <0x0 0x60200000 0x0 0x100000>,
+ <0x0 0x60200000 0x0 0x1fe00000>,
<0x0 0x01c13000 0x0 0x1000>,
<0x0 0x60005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
@@ -5781,6 +6288,7 @@
phy-names = "pciephy";
max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
num-lanes = <4>;
+ linux,pci-domain = <1>;
status = "disabled";
};