diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8548CDS.h | 1 | ||||
| -rw-r--r-- | include/configs/P1010RDB.h | 3 | ||||
| -rw-r--r-- | include/configs/P2041RDB.h | 2 | ||||
| -rw-r--r-- | include/configs/T102xRDB.h | 1 | ||||
| -rw-r--r-- | include/configs/T104xRDB.h | 2 | ||||
| -rw-r--r-- | include/configs/T208xQDS.h | 1 | ||||
| -rw-r--r-- | include/configs/T208xRDB.h | 1 | ||||
| -rw-r--r-- | include/configs/T4240RDB.h | 2 | ||||
| -rw-r--r-- | include/configs/corenet_ds.h | 2 | ||||
| -rw-r--r-- | include/configs/kmcent2.h | 2 | ||||
| -rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 2 | ||||
| -rw-r--r-- | include/configs/qemu-ppce500.h | 2 | ||||
| -rw-r--r-- | include/configs/socrates.h | 1 |
13 files changed, 0 insertions, 22 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d8ffa2e28a9..5fba5bb198d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -34,7 +34,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_CCSRBAR 0xe0000000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ad78dba865b..53c719807d6 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -108,9 +108,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ - -#define CONFIG_ENABLE_36BIT_PHYS - /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index df16319de4a..8e5d18f6cca 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -58,8 +58,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bd458ff35e9..3f32354038e 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,7 +15,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 505bae931e6..bda25248621 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -83,8 +83,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2db2b07fb4b..0c13550ef23 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -22,7 +22,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 07e1108f0f0..5fb768ab92f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,7 +17,6 @@ /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 526d40fa034..6f5b7594299 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -56,8 +56,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f563a5f3816..034cd00381e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -62,8 +62,6 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 4de5736d8ce..798688a220b 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -152,8 +152,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - /* POST memory regions test */ #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 2a24236c111..1be548e20d2 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -111,8 +111,6 @@ */ #define CONFIG_L2_CACHE -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index c3fef0de173..006593acfdd 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -11,8 +11,6 @@ #define CONFIG_SYS_RAMBOOT -#define CONFIG_ENABLE_36BIT_PHYS - /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3309779118a..73f82fc00ac 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ /* * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_ENABLE_36BIT_PHYS 1 /* * sysclk for MPC85xx |