aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Convert CONFIG_SYS_UNIFY_CACHE to KconfigTom Rini2022-07-079-8/+8
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_UNIFY_CACHE Signed-off-by: Tom Rini <trini@konsulko.com>
* layerscape: Remove some unused CONFIG symbolsTom Rini2022-07-076-18/+1
| | | | | | | | All of these symbols are not referenced anywhere else in the code, so remove them. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* usb: Remove some unused CONFIG settingsTom Rini2022-07-079-41/+0
| | | | | | | | On platforms that use CONFIG_USB_OHCI_NEW we do not need to set CONFIG_SYS_USB_OHCI_REGS_BASE nor CONFIG_SYS_USB_OHCI_SLOT_NAME. Drop these from platforms that we can. Signed-off-by: Tom Rini <trini@konsulko.com>
* usb: ohci-hcd: Remove some unused legacy codeTom Rini2022-07-073-126/+0
| | | | | | | | | At this point, the only user of ohci-hcd that also uses PCI is using DM, so we can drop CONFIG_PCI_OHCI* usage. No platforms set either of CONFIG_SYS_USB_OHCI_BOARD_INIT or CONFIG_SYS_USB_OHCI_CPU_INIT so those hooks can be removed as well. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_USB_OHCI_NEW et al to KconfigTom Rini2022-07-07107-214/+173
| | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_OHCI_SWAP_REG_ACCESS CONFIG_SYS_USB_OHCI_CPU_INIT CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS CONFIG_SYS_USB_OHCI_SLOT_NAME CONFIG_USB_ATMEL CONFIG_USB_ATMEL_CLK_SEL_PLLB CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_OHCI_LPC32XX CONFIG_USB_OHCI_NEW Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: Ensure all SPL symbols in Kconfig have some SPL dependencyTom Rini2022-07-0727-36/+50
| | | | | | | | | | | Tighten up symbol dependencies in a number of places. Ensure that a SPL specific option has at least a direct dependency on SPL. In places where it's clear that we depend on something more specific, use that dependency instead. This means in a very small number of places we can drop redundant dependencies. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_USB_XHCI_EXYNOS et al to KconfigTom Rini2022-07-076-18/+16
| | | | | | | | This converts the following to Kconfig: CONFIG_USB_XHCI_EXYNOS CONFIG_USB_EHCI_EXYNOS Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch '2022-07-06-platform-updates' into nextTom Rini2022-07-0640-215/+920
|\ | | | | | | - Assorted updates for Toradex, TI, Aspeed and Nuvoton platforms
| * misc: nuvoton: Add host interface configuration driverJim Liu2022-07-063-0/+117
| | | | | | | | | | | | add nuvoton BMC npcm750 host configuration driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
| * CI: Add Aspeed AST2600Joel Stanley2022-07-062-0/+9
| | | | | | | | | | | | | | | | | | The AST2600 has a Qemu model that allows testing. Create a SPI NOR image containing the combined SPL and u-boot FIT image. Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * aspeed/spl: Remove OVERLAY from linker scriptJoel Stanley2022-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic arm linker script contains this section: .bss __rel_dyn_start (OVERLAY) : { ... } The (OVERLAY) syntax in the description causes the .bss section to be included in the NOR area of the image: $ objdump -t -j .bss spl/u-boot-spl SYMBOL TABLE: 0000c61c l d .bss 00000000 .bss 0000c640 l O .bss 00000040 __value.0 0000c68c g O .bss 00000000 __bss_end 0000c61c g O .bss 00000000 __bss_start 0000c680 g O .bss 0000000c stdio_devices This is what the custom linker script tries to avoid, as the NOR area is read-only. Remove the OVERLAY syntax to fix the BSS location: $ objdump -t -j .bss spl/u-boot-spl SYMBOL TABLE: 83000000 l d .bss 00000000 .bss 83000000 l O .bss 00000040 __value.0 0000c61c g O .bss 00000000 __image_copy_end 8300004c g O .bss 00000000 __bss_end 83000000 g O .bss 00000000 __bss_start 83000040 g O .bss 0000000c stdio_devices This restores the state of the linker script before the patch that fixed the linker lists issue. Fixes: f6810b749f2e ("aspeed/ast2600: Fix SPL linker script") Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ast2600: Configure u-boot-with-spl.bin targetJoel Stanley2022-07-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The normal way of loading u-boot is as a FIT, so configure u-boot.img as the SPL playload. The u-boot-with-spl.bin target will add padding according to CONFIG_SPL_MAX_SIZE which defaults to 64KB on the AST2600. With this the following simple steps can be used to build and boot a system: make u-boot-with-spl.bin truncate -s 64M u-boot-with-spl.bin qemu-system-arm -nographic -M ast2600-evb \ -drive file=u-boot-with-spl.bin,if=mtd,format=raw Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * spl: Set SPL_MAX_SIZE default for AST2600Joel Stanley2022-07-061-0/+1
| | | | | | | | | | | | | | The AST2600 bootrom has a max size of 64KB. This can be overridden if the system is running the SPL from SPI NOR and not using secure boot. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/ast2600: Disable hash hardware accelJoel Stanley2022-07-061-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HACE driver lacks support for all the hash types, causing boot to fail with the default FIT configuration which uses CRC32. Additionally the Qemu model or the u-boot driver is unable to correctly compute the SHA256 hash used in a FIT. Disable HACE by default while the above issues are worked out to enable boot testing in Qemu. Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/ast2600: Make position independentJoel Stanley2022-07-061-0/+1
| | | | | | | | | | | | | | | | Allows loading one u-boot from another. Useful for testing on hardware. Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/ast2600: Enable CRC32Joel Stanley2022-07-061-0/+1
| | | | | | | | | | | | | | | | Useful for testing images with the default hash type. Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/ast2600: Enable eMMC related boot optionsJoel Stanley2022-07-061-0/+12
| | | | | | | | | | | | | | Allow booting zImage from ext4 devices with DOS or UEFI partition layouts. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * mmc/aspeed: Enable controller clocksJoel Stanley2022-07-061-0/+15
| | | | | | | | | | | | Request and enable the controller level clocks. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * mmc/aspeed: Probe from controllerJoel Stanley2022-07-062-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Aspeed SDHCI controller is arranged with some shared control registers, followed by one or two sets of actual SDHCI registers. Adjust the driver to probe this controller device first. The driver then wants to iterate over the child nodes to probe the SDHCI proper: ofnode node; dev_for_each_subnode(node, parent) { struct udevice *dev; int ret; ret = device_bind_driver_to_node(parent, "aspeed_sdhci", ofnode_get_name(node), node, &dev); if (ret) return ret; } However if we did this the sdhci driver would probe twice; once "naturally" from the device tree and a second time due to this code. Instead of doing this we can rely on the probe order, where the controller will be set up before the sdhci devices. A better solution is preferred. Select MISC as the controller driver is implemented as a misc device. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * mmc/aspeed: Add debuging for clock probe failuresJoel Stanley2022-07-061-2/+7
| | | | | | | | Signed-off-by: Joel Stanley <joel@jms.id.au>
| * clk/ast2500: Add SD clockJoel Stanley2022-07-061-0/+23
| | | | | | | | | | | | In order to use the clock from the sdhci driver, add the SD clock. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * clk/ast2600: Adjust eMMC clock namesJoel Stanley2022-07-061-2/+2
| | | | | | | | | | | | | | Adjust clock to stay compatible with those used by the Linux kernel device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * clk/aspeed: Add debug message when clock failsJoel Stanley2022-07-062-2/+5
| | | | | | | | | | | | A common message across platforms that prints the clock number. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: ast2500: Update SDHCI nodesJoel Stanley2022-07-063-25/+32
| | | | | | | | | | | | | | Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: ast2600: Update SDHCI nodesJoel Stanley2022-07-062-46/+35
| | | | | | | | | | | | | | Match the description used by the Linux kernel, except use scu instead of syscon as the phandle. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/aspeed: Enable EEPROM optionsJoel Stanley2022-07-062-0/+5
| | | | | | | | | | | | | | To allow testing of the I2C driver, enable the eprom command and the misc driver. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * config/ast2600: Enable I2C driverJoel Stanley2022-07-061-0/+1
| | | | | | | | Signed-off-by: Joel Stanley <joel@jms.id.au>
| * i2c/aspeed: Add AST2600 compatibleJoel Stanley2022-07-061-0/+1
| | | | | | | | | | Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * i2c/aspeed: Fix reset controlJoel Stanley2022-07-061-7/+15
| | | | | | | | | | | | | | | | | | | | | | The reset control was written for the ast2500 and directly programs the clocking register. So we can share the code with other SoC generations use the reset device to deassert the I2C reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * reset/aspeed: Implement status callbackJoel Stanley2022-07-062-0/+36
| | | | | | | | | | | | | | | | The I2C driver shares a reset line between buses, so allow it to test the state of the reset line before resetting it. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * ARM: dts: ast2600-evb: Add I2C devicesJoel Stanley2022-07-061-0/+16
| | | | | | | | | | | | | | The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7, and a LM75 temp sensor on bus 8. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: ast2500-evb: Add I2C devicesJoel Stanley2022-07-061-0/+19
| | | | | | | | | | | | | | | | The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable those busses we can test the I2C driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * ARM: dts: ast2600-evb: Remove redundant pinctrlJoel Stanley2022-07-061-15/+0
| | | | | | | | | | | | | | Now that these are in the dtsi we don't need them in the EVB device tree. Signed-off-by: Joel Stanley <joel@jms.id.au>
| * ARM: dts: ast2600: Disable I2C nodes by defaultJoel Stanley2022-07-061-0/+7
| | | | | | | | | | | | | | Allow boards to enable the buses they use. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * ARM: dts: ast2600: Add I2C reset propertiesJoel Stanley2022-07-061-0/+16
| | | | | | | | | | | | | | | | The same as the upstream Linux device tree, each i2c bus has a property specifying the reset line. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
| * ARM: dts: ast2600: Add I2C pinctrlEddie James2022-07-061-0/+33
| | | | | | | | | | | | | | | | | | Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
| * soc: soc_ti_k3: identify j7200 SR2.0 SoCsBryan Brattlof2022-07-061-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Anytime a new revision of a chip is produced, Texas Instruments will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID register by one. Typically this will be decoded as SR1.0 -> SR2.0 ... however a few TI SoCs do not follow this convention. Rather than defining a revision string array for each SoC, use a default revision string array for all TI SoCs that continue to follow the typical 1.0 -> 2.0 revision scheme. Signed-off-by: Bryan Brattlof <bb@ti.com>
| * phy: nuvoton: add NPCM7xx phy control driverJim Liu2022-07-063-0/+223
| | | | | | | | | | | | add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
| * toradex: tdx-cfg-block: add new toradex oui rangePhilippe Schenker2022-07-063-8/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new Toradex MAC OUI (8c:06:cb), to the config block. With this change we extend the possible serial-numbers as follows: For serial-numbers 00000000-16777215 OUI 00:14:2d is taken For serial-numbers 16777216-33554431 OUI 8c:06:cb is taken Lower 24-bit of the serial number are used in the NIC part of the MAC address, the complete serial number can be calculated using the OUI. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * board: ti: common: board_detect: Do 1byte address checks first.Nishanth Menon2022-07-061-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do 1 byte address checks first prior to doing 2 byte address checks. When performing 2 byte addressing on 1 byte addressing eeprom, the second byte is taken in as a write operation and ends up erasing the eeprom region we want to preserve. While we could have theoretically handled this by ensuring the write protect of the eeproms are properly managed, this is not true in case where board are updated with 1 byte eeproms to handle supply status. Flipping the checks by checking for 1 byte addressing prior to 2 byte addressing check prevents this problem at the minor cost of additional overhead for boards with 2 byte addressing eeproms. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * board: ti: common: Handle the legacy eeprom address width properlyNishanth Menon2022-07-061-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to supply chain issues, we are starting to see a mixture of eeprom usage including the smaller 7-bit addressing eeproms such as 24c04 used for eeproms. These eeproms don't respond well to 2 byte addressing and fail the read operation. We do have a check to ensure that we are reading the alternate addressing size, however the valid failure prevents us from checking at 1 byte anymore. Rectify the same by falling through and depend on header data comparison to ensure that we have valid data. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * board: ti: common: Optimize boot when detecting consecutive bad recordsNishanth Menon2022-07-061-1/+4
| | | | | | | | | | | | | | | | | | | | The eeprom data area is much bigger than the data we intend to store, however, with bad programming, we might end up reading bad records over and over till we run out of eeprom space. instead just exit when 10 consecutive records are read. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * firmware: ti_sci_static_data: Make file board agnosticVignesh Raghavendra2022-07-061-38/+4
| | | | | | | | | | | | | | | | | | | | Static DMA channel data for R5 SPL is mostly board agnostic so use SOC configs instead of EVM specific config to ease adding new board support. Drop J7200 EVM specific settings as its same as J721e Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
| * configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfigGeorgi Vlaev2022-07-061-0/+1
| | | | | | | | | | | | | | | | Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * board: ti: am62x: Account for DDR size fixups if ECC is enabledGeorgi Vlaev2022-07-061-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * board: ti: am62x: Use fdt functions for ram and bank initGeorgi Vlaev2022-07-061-9/+2
| | | | | | | | | | | | | | | | | | | | Use the appropriate fdtdec_setup_mem_size_base() call in dram_init() and fdtdec_setup_bank_size() in dram_bank_init() to pull these values from DT, where they are already available, instead of hardcoding them. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: k3-am625-*: Mark memory with u-boot,dm-splGeorgi Vlaev2022-07-062-0/+5
| | | | | | | | | | | | | | | | Mark the memory node with u-boot,dm-spl so we can use it from early SPL on both R5 and A53. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: mach-k3: common: Use ddr_init in spl_enable_dcacheGeorgi Vlaev2022-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | The spl_enable_dcache() function calls dram_init_banksize() to get the total memory size. Normally the dram_init_banksize() setups the memory banks, while the total size is reported by ddr_init(). This worked so far for K3 since we set the gd->ram_size in dram_init_banksize() as well. Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * toradex: tdx-cfg-block: extend assembly versionPhilippe Schenker2022-07-062-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two decimal digits reserved to encode the module version and revision. This code so far implemented A-Z which used 0-25 of this range. This commit extends the range to make use of all 99 numbers. After capital letters the form with a hashtag and number (e.g. #26) is used. Examples: If the assembly version is between zero and 25 the numbering is as follows, as it also has been before this commit: 0: V0.0A 1: V0.0B ... 25: V0.0Z New numbering of assembly version: If the number is between 26 and 99 the new assembly version name is: 26: V0.0#26 27: V0.0#27 ... 99: V0.0#99 Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * toradex: tdx-cfg-block: use defines for string lengthPhilippe Schenker2022-07-061-4/+8
| | | | | | | | | | | | | | | | | | With those defines the length can be reused and is in one place extendable. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
generated by cgit (git 2.34.1) at 2025-02-27 12:23:58 +0000