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* arm64: zynqmp: Define all eeproms for SC on vck190Michal Simek2021-09-301-0/+15
| | | | | | | | There are multiple eeproms on vck190 that's why list all of them. FMC eeproms are present only when fmcs are plugged. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/96902661e3ab9e20b59d626e6129ccf6f3317c4d.1632488695.git.michal.simek@xilinx.com
* arm: zynq: Use s25fl256s1 compatible string on zedboardMichal Simek2021-09-301-1/+1
| | | | | | | Use compatible string which is listed in the Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/49bc6b056b0f6f69d4d90351dc875a66b7e37619.1631715748.git.michal.simek@xilinx.com
* arm64: zynqmp: Add device tree properties for nand flashAmit Kumar Mahapatra2021-09-301-0/+4
| | | | | | | | | Add ecc strength & ecc step size properties for nand flash devices, when operating in software-ecc mode. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/866f4b888129ff0213df9cdb51b5529b199fb7b7.1631713594.git.michal.simek@xilinx.com
* xilinx: zynqmp: Set modeboot env variable in eMMC bootmodeAshok Reddy Soma2021-09-301-0/+1
| | | | | | | | | Set environment variable modeboot to "emmcboot" in case of eMMC boot mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/c61231e4b8c6118862dfc82e923211637bf29991.1631688736.git.michal.simek@xilinx.com
* ARM: zynq: Enable capsule update for qspi and mmcMichal Simek2021-09-302-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate dfu_alt_info setup at runtime for capsule update. Enabling this feature will help with upgrading boards without remembering what is where. The similar change was done for ZynqMP by commit b86f43de0be0 ("xilinx: zynqmp: Add support for runtime dfu_alt_info setup"). Code needs to be enabled by CONFIG_SET_DFU_ALT_INFO. And also enable capsule on disk for RAW firmware images with efidebug command. Two indexes are supported for SPL flow. Images can be generated like: ./tools/mkeficapsule --raw spl/boot.bin --index 1 capsule1.bin ./tools/mkeficapsule --raw u-boot.img --index 2 capsule2.bin Then place them to SD card and load them: load mmc 0 10000000 capsule1.bin && efidebug capsule update -v 10000000 load mmc 0 10000000 capsule2.bin && efidebug capsule update -v 10000000 FSBL flow will also work where only index 1 capsule is used. There should be enough space for using boot.bin with bitstream too. Zynq also support multiple boot locations in SPI or MMC but it is not wired by this patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/bea5fc75a87a5971f118b46bab4aa7ca39a629c6.1630061610.git.michal.simek@xilinx.com
* Merge tag 'rpi-next-2021.10.2' of ↵WIP/29Sep2021Tom Rini2021-09-292-0/+7
|\ | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - fix usb stopt; usb start; bug - update Nicolas email address
| * arm: rpi: perform XHCI firmware upload only onceMarek Szyprowski2021-09-291-0/+6
| | | | | | | | | | | | | | | | | | | | XHCI firmware upload must be performed only once after initializing the PCI bridge. This fixes USB stack initialization after calling "usb stop; usb start" on Raspberry Pi 4B. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * mailmap: Update mail address for Nicolas Saenz julienneNicolas Saenz Julienne2021-09-291-0/+1
| | | | | | | | | | | | | | | | The @suse.de address doesn't exist anymore. Update it to something not dependent on my workplace. Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-09-291-2/+2
|\ \ | | | | | | | | | - Armada8k: Fix CP0 eMMC/SDIO support (Robert)
| * | arm: dts: armada8040: Fix CP0 eMMC/SDIO supportRobert Marko2021-09-291-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the migration to a single DTSI for the CP110-s specific pinctrl compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics. Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor. So, the mvebu-pinctrl driver check specifically for the "marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit. Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl" for CP0 and "marvell,8k-cps-pinctrl" for the CP1. This is obviously incorrect as the pinctrl driver does not know about these. So fix the regression by applying correct compatibles to the DTSI. Regression found and tested on the Puzzle M801 board. Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge branch '2021-09-28-regression-fixes'Tom Rini2021-09-2813-32/+52
|\ \ | |/ |/| | | | | | | | | | | | | | | - Reintroduce creating internally the "nor%d" style names, in order to fix some use U-Boot use-cases involving the "mtd" command. - Fix a regression over the default SPI bus mode shown by having the compiled default actually start being used. The correct default here is 0. - Fix ethernet on imx7d-sdb - Fix a regression with MTD NAND devices when OF_LIVE is enabled
| * imx: imx7d-sdb: fix ethernet, sync .dts with linuxRasmus Villemoes2021-09-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0 (aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync device tree with v5.5-rc1", but in the linux tree, these gpios have always been GPIO_ACTIVE_HIGH ever since this node was introduced around v4.13 (linux commit 184f39b5). I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work around the behaviour of the soft-spi driver back then, which effectively defaulted to spi-mode 3 and not 0. That was arguably a bug in the soft-spi driver, which then got fixed in 0e146993bb3 (spi: add support for all spi modes with soft spi), but that commit then broke ethernet on this board. Fix it by setting the gpios as active high, which as a bonus actually brings us in sync with the .dts in the linux source tree. Without this, one gets Net: Could not get PHY for FEC0: addr 0 No ethernet found. With this, ethernet (at least ping and tftp) works as expected from the U-Boot shell. Cc: Fabio Estevam <festevam@gmail.com> Cc: Joris Offouga <offougajoris@gmail.com> Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| * mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard2021-09-286-23/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0Marek Vasut2021-09-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before e2e95e5e254 ("spi: Update speed/mode on change") most systems silently defaulted to SF bus mode 0. Now the mode is always updated, which causes breakage. It seems most SF which are used as boot media operate in bus mode 0, so switch that as the default. This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked as those might need mode 3. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Cc: Andreas Biessmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Tom Rini <trini@konsulko.com> Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Cc: Vignesh Raghavendra <vigneshr@ti.com>
| * mtd: spi: nor: force mtd name to "nor%d"Patrick Delaunay2021-09-284-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini <trini@konsulko.com>
| * mtd: cfi_flash: use cfi_flash_num_flash_banks only when supportedPatrick Delaunay2021-09-281-1/+7
|/ | | | | | | | | | | | | | When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, CONFIG_SYS_MAX_FLASH_BANKS is replaced by cfi_flash_num_flash_banks, but this variable is defined in drivers/mtd/cfi_flash.c, which is compiled only when CONFIG_FLASH_CFI_DRIVER is activated, in U-Boot or in SPL when CONFIG_SPL_MTD_SUPPORT is activated. This patch deactivates this feature CONFIG_SYS_MAX_FLASH_BANKS_DETECT when flash cfi driver is not activated to avoid compilation issue in the next patch, when CONFIG_SYS_MAX_FLASH_BANKS is used in spi_nor_scan(). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* Prepare v2021.10-rc5v2021.10-rc5Tom Rini2021-09-271-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/27Sep2021Tom Rini2021-09-272-1/+9
|\ | | | | | | | | - turris_omnia: fix leaked mtd device (Marek) - phy: marvell: cp110: Fix SATA invert polarity (Denis)
| * phy: marvell: cp110: Support SATA invert polarityDenis Odintsov2021-09-271-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <shiva@mail.ru> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: turris_omnia: fix leaked mtd deviceMarek Behún2021-09-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After getting MTD device via get_mtd_device_nm(), we need to put it with put_mtd_device(), otherwise we get Removing MTD device #0 (mx25l6405d) with use count 1 before booting kernel. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Tested-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge tag 'efi-2021-10-rc5' of ↵WIP/26Sep2021Tom Rini2021-09-264-23/+35
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc5 Documentation: * add /config bindings to HTML documentation UEFI * Fix number_of_algorithms field in TCG EFI Protocol
| * efi_loader: Fix spec ID event creationRuchika Gupta2021-09-252-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TCG EFI Protocol Specification defines the number_of_algorithms field in spec ID event to be equal to the number of active algorithms supported by the TPM device. In current implementation, this field is populated with the count of all algorithms supported by the TPM which leads to incorrect spec ID event creation. Similarly, the algorithm array in spec ID event should be a variable length array with length being equal to the number_of_algorithms field. In current implementation this is defined as a fixed length array which has been fixed. Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> CC: Masahisa Kojima <masahisa.kojima@linaro.org> CC: Ilias Apalodimas <ilias.apalodimas@linaro.org> CC: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * doc: Add mention of the /config bindingSimon Glass2021-09-252-0/+11
|/ | | | | | | | | | The devicetree binding files are in their own directory and use a simple text format. Add a link for the binding for the /config node, since it is otherwise hard to find. Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge branch '2021-09-24-assorted-minor-updates'Tom Rini2021-09-2413-685/+42
|\ | | | | | | - Assorted bugfixes, MAINTAINER updates and dead code removal
| * arm: orion5x: edminiv2: change maintainerWIP/2021-09-24-assorted-minor-updatesSimon Guinot2021-09-241-1/+1
| | | | | | | | | | | | | | | | | | Since Albert Aribaud is not maintaining anymore the LaCie Ethernet Disk mini V2 board, then I am taking over. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * mtd: remove SPEAr flash driver st_smiPatrick Delaunay2021-09-245-668/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Taking over responsibility for GE boards from SebastianMartyn Welch2021-09-243-3/+3
| | | | | | | | | | | | | | | | I am taking over responsibility for the GE board from Sebastian Reichel. Updating the MAINTAINERS files to reflect this. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * MAINTAINERS: remove SPEAR entryPatrick Delaunay2021-09-241-7/+0
| | | | | | | | | | | | | | | | | | | | | | As the lastest spear directories are removed, delete the associated entry in the MAINTAINERS file: - arch/arm/cpu/arm926ejs/spear/ - arch/arm/include/asm/arch-spear/ Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * fs: avoid superfluous messagesHeinrich Schuchardt2021-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Output like the following is quite irritating: => bootefi hello Scanning disk mmc2.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc1.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc0.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Albeit a whole disk may be formatted with a filesystem in most cases a partition table is used and the whole disk (partition number 0) doesn't contain a filesytem. Some partitions may only contain a blob. Not seeing a filesytem on the whole disk or on any partition is only worth a debug message. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * scripts/mailmapper: enable running with Python 3Heinrich Schuchardt2021-09-241-5/+9
| | | | | | | | | | | | | | | | Our mailmapper script required Python 2 which is no longer maintained. A main difference when converting to Python 3 is that byte strings are not character strings. So add conversion and skip over conversion errors. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
| * test/py: tpm2: Skip tpm pytest based on env variableT Karthik Reddy2021-09-241-0/+28
|/ | | | | | | | | | | | Tpm test cases relies on tpm device setup. Provide an environment variable "env__tpm_device_test_skip = True" to skip the test case if tpm device is not present. Only needed will have to add variable to the py-test framework. Test runs successfully even this variable is absent. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* Merge git://source.denx.de/u-boot-socfpgaWIP/23Sep2021Tom Rini2021-09-235-20/+11
|\ | | | | | | Bugfixes for this one socfpga platform
| * ddr: altera: use KBUILD_BASENAME instead of __FILE__Marek Vasut2021-09-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Let DWMAC configure PHY reset GPIOMarek Vasut2021-09-221-7/+0
| | | | | | | | | | | | | | | | | | | | | | The DM DWMAC driver is perfectly capable of configuring the ethernet PHY reset GPIO, let the driver do it instead of doing it in the board file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Enable DW I2C driverMarek Vasut2021-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | The Designware I2C IP is used to communicate with I2C peripherals on SoCFPGA, and required to access I2C EEPROM on this board. Enable it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Fix UDC controller phandle in DTMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Un-disable WDT in DTMarek Vasut2021-09-221-4/+0
| | | | | | | | | | | | | | | | | | The WDT on this system should be enabled, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Set default SPI NOR mode and frequencyMarek Vasut2021-09-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR bus mode is 0 on this system, update it accordingly. Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on this system support that and it is a huge performance improvement. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital SMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | This was configured in downstream, so it is likely that most of the custom software used around the device depends on it. Make upstream compatible. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Increase environment sizeMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | Increase the environment size from 4k to 16k to prevent environment from becoming full. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Drop meaningless commentMarek Vasut2021-09-221-2/+0
| | | | | | | | | | | | | | | | | | The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | Merge branch 'master' of git://source.denx.de/u-boot-usbTom Rini2021-09-2315-58/+327
|\ \ | |/ |/| | | Late bunch of USB fixes (incl. the xhci usb 3.1 support)
| * usb: xhci-dwc3: Add support for USB 3.1 controllersMark Kettenis2021-09-221-1/+2
| | | | | | | | | | | | | | | | This adds support for the DWC_sub31 controllers such as those found on Apple's M1 SoC. This version of the controller seems to work fine with the existing driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
| * usb: ehci-mx6: use phy_type from device treeMatthias Schiffer2021-09-222-2/+24
| | | | | | | | | | | | | | | | | | | | | | Allow using different PHY interfaces for multiple USB controllers. When no value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay compatible with current board configurations. This also adds support for the HSIC mode of the i.MX7. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * usb: ehci-ci: remove redundant PORTSC flag definitionsMatthias Schiffer2021-09-221-11/+0
| | | | | | | | | | | | | | | | These definitions are unused, all boards that define portsc flags use the equivalent PORT_* definitions instead. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * include/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIALMatthias Schiffer2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL with the equivalent PORT_PTS_SERIAL. Only the zmx25 platform is affected. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * usb: add support for ULPI/SERIAL/HSIC PHY modesMatthias Schiffer2021-09-222-0/+6
| | | | | | | | | | | | | | | | Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * configs: Enable USB3 on Allwinner H6 boardsSamuel Holland2021-09-222-0/+10
| | | | | | | | | | | | | | | | Pine H64 and Orange Pi 3 both provide a USB3 type A port. Enable it in U-Boot. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * usb: xhci-dwc3: Add support for clocks/resetsSamuel Holland2021-09-221-0/+56
| | | | | | | | | | | | | | | | | | | | Some platforms, like the Allwinner H6, do not have a separate glue layer around the dwc3. Instead, they rely on the clocks/resets/phys referenced from the dwc3 DT node itself. Add support for enabling the clocks/resets referenced from the dwc3 DT node. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * usb: xhci-pci: Move reset logic out of XHCI coreSamuel Holland2021-09-224-43/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting an XHCI controller inside xhci_register undoes any register setup performed by the platform driver. And at least on the Allwinner H6, resetting the XHCI controller also resets the PHY, which prevents the controller from working. That means the controller must be taken out of reset before initializing the PHY, which must be done before calling xhci_register. The logic in the XHCI core was added to support the Raspberry Pi 4 (although this was not mentioned in the commit log!), which uses the xhci-pci platform driver. Move the reset logic to the platform driver, where it belongs, and where it cannot interfere with other platform drivers. This also fixes a failure to call reset_free if xhci_register failed. Fixes: 0b80371b350e ("usb: xhci: Add reset controller support") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit (git 2.34.1) at 2025-03-01 17:24:38 +0000