aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'v2025.01-rc3' into nextWIP/25Nov2024-nextTom Rini2024-11-2519-443/+322
|\ | | | | | | Prepare v2025.01-rc3
| * ast2600: spl: Use readl for reading mmioJoel Stanley2024-11-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | u-boot was crashing in qemu as the modeled hardware enforced overly strict memory reads. While this code will work on existing hardware, fix to avoid future issues. Fixes: 12770d0df0e8 ("ast2600: spl: Add boot mode detection") Link: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley <joel@jms.id.au>
| * Merge patch series "Fix device removal order for Apple dart iommu"WIP/24Nov2024Tom Rini2024-11-241-4/+3
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Janne Grunau <j@jannau.net> says: Starting with v2024.10 dev_iommu_dma_unmap calls during device removal trigger a NULL pointer dereference in the Apple dart iommu driver. The iommu device is removed before its user. The sparsely used DM_FLAG_VITAL flag is intended to describe this dependency. Add it to the driver. Adding this flag is unfortunately not enough since the boot routines except the arm one simply remove all drivers. Add and use a new function which calls dm_remove_devioce_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); to ensure this order dependency is head consistently. Link: https://lore.kernel.org/r/20241123-iommu_apple_dart_ordering-v2-0-cc2ade6dde97@jannau.net
| | * dm: Add dm_remove_devices_active() for ordered device removalJanne Grunau2024-11-241-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces dm_remove_devices_flags() calls in all boot implementations to ensure non vital devices are consistently removed first. All boot implementation except arch/arm/lib/bootm.c currently just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result in crashes when dependencies between devices exists. The driver model's design document describes DM_FLAG_VITAL as "indicates that the device is 'vital' to the operation of other devices". Device removal at boot should follow this. Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which does this. Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI boot. The xhci-pci (driver which depends on the IOMMU to work) removes its mapping on removal. This explodes when the IOMMU device was removed first. dm_remove_devices_flags() is kept since it is used for testing of device_remove() calls in dm. Signed-off-by: Janne Grunau <j@jannau.net>
| * | arm64: dts: imx8mn: Include 32kHz oscillator clock in SPL DTsMarek Vasut2024-11-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent"), drivers/clk/imx/clk-imx8mn.c clk_get_by_name(dev, "osc_24m", &osc_24m_clk) fails with error -22 EINVAL in SPL. This is because clk_get_by_name() in the end calls fdtdec_parse_phandle_with_args(), which iterates over all phandles in clock-controller@30380000 { clocks = <&osc_32k>, <&osc_24m>, ... } node 'clocks' property in an attempt to find the "osc_24m" clock, but fails to resolve the &osc_32k phandle and returns with -EINVAL. Include the osc_32k clock in SPL DTs as a low risk fix for v2025.01 release. This way, fdtdec_parse_phandle_with_args() can resolve both the osc_32k and following osc_24m phandle and successfully look up the osc_24m clock. Fixes: 50cdd3f74af3 ("clk: imx: clk-imx8mn Fix nand and spi clock parent") Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon
| * | Merge branch 'qcom-main' of ↵WIP/20Nov2024Tom Rini2024-11-205-1/+173
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-snapdragon CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/23474 - UFS support is enabled for SC7280 and SM8150 platforms. - Qualcomm dt-bindings headers are all dropped in favour of dts/upstream. - The SMMU driver now correctly handles stream ID 0 and is disabled in EL2. - Initial support for capsule updates (using the new dynamic UUIDs) is added for the RB3 Gen 2 board alongside a new SCSI backend for DFU. - CONFIG_PINCONF is enabled in qcom_defconfig. - The vqmmc supply is now enabled for sdcard support on boards that need it. - A quirk is added for reading GPIOs on the PM8550 PMIC
| | * | mach-snapdragon: implement capsule update supportCaleb Connolly2024-11-205-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcomm boards flash U-Boot a variety of partitions, implement support for determining which slot U-Boot is running from, finding the correct partition for that slot and configuring the appropriate DFU string. Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the UEFI partition, and ignore handling of slots. In the future we will additionally support booting U-Boot from other partitions (e.g. boot) and correct handling for A/B. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| | * | mach-snapdragon: configure loggingCaleb Connolly2024-11-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Set LOG_CATEGORY and pr_fmt. Also fix the time.h include. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| | * | ARM: mach-snapdragon: configure a larger default SYS_MALLOC_LEN for fastbootNeil Armstrong2024-11-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fastboot is very hungry when it flashes larges chunks, and 8MiB is way too small, allocate a much bigger size like other platforms using Fastboot. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # rb1 Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
| * | | Merge tag 'xilinx-for-v2025.01-rc3-v2' of ↵WIP/19Nov2024Tom Rini2024-11-194-4/+7
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze AMD/Xilinx changes for v2025.01-rc3: - microblaze: - Disable JFFS2 - fpga: - pass compatible flag to fpga_load() - zynqmp: - SOM RTC fix - SC(system controller) PMW polarity fix - Fix ram_top calculation with introducing XILINX_MINI - Fix RPU release command - versal: - Enable capsule update - Enable soft reset and Micron octal flashes - xilinx: - Align Kconfig regarding SPI_STACKED_PARALLEL - bootcount: - Add new zynqmp driver
| | * | | drivers: bootcount: Add ZynqMP specific bootcount supportVasileios Amoiridis2024-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add native support of the bootcount mechanism in the ZynqMP by utilising internal PMU registers. The Persistent Global Storage Registers of the Platform Management Unit can keep their value during reboot cycles unless there is a POR reset, making them appropriate for the bootcount mechanism. Signed-off-by: Vasileios Amoiridis <vasileios.amoiridis@cern.ch> Reviewed-by: Heiko Schocher <hs@denx.de> Link: https://lore.kernel.org/r/20241105132744.1572759-2-vassilisamir@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
| | * | | arm64: zynqmp: Fix r5 mode for cpu release commandPadmarao Begari2024-11-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu release command for r5 mode (lockstep/split) argument accepts only string. But the zynqmp tcminit command accepts string or number for r5 mode (lockstep/split or 0/1) argument. To fix the r5 mode argument, the common argument (lockstep/split or 0/1) is used across different u-boot commands. Use the strcmp() instead of strncmp() to make uniform the r5 mode (lockstep/split or 0/1) for the zynqmp tcminit and cpu release command. Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Link: https://lore.kernel.org/r/20241104122750.96251-1-padmarao.begari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
| | * | | arm64: zynqmp: Fix pwm-fan polaritySaeed Nowshadi2024-11-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In previous version of pwm driver, the polarity of pwm were implemented in reverse. In recent release, that issue in the driver is fixed, therefore, correctly set the polarity in the device tree. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3e8e38b77101335f86bca0f05b3988877bb12993.1729766551.git.michal.simek@amd.com
| | * | | arm64: zynqmp: Configure SoC RTC on SOMMichal Simek2024-11-121-0/+1
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use RTC available in HW on Kria SOM without using emulation that's why configure it properly and disable emulated one. Power on reset value of RTC Calibration register without battery backup is not matching with crystal frequency which leads to RTC time drift. That's why write CALIB_WRITE register with crystal frequency (0x7FFF). There is also an option to write zero so that Linux will set default value (0x7FFF) in driver probe but calibration 0 is not permited by DT schema. Co-developed-by: Srinivas Goud <srinivas.goud@amd.com> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
| * | | imx: Fix critical thermal thresholdFrancesco Dolcini2024-11-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the critical thermal threshold for i.MX processors, this was changed while moving the code from imx8m/imx9 directories into a shared place. There is no need to keep the critical threshold 5 degrees less than the SoC maximum temperature threshold, what is actually going to happen in practice is that we are going to power-off the board when the SoC is still within its working temperature range. In addition to that this is a change in the actual behavior, that is introducing a regression to users, and it was hidden within a software refactoring. Fixes: d0fe80890ab1 ("imx: Generalize fixup_thermal_trips") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
| * | | Merge patch series "Apply SoM overlays on phyCORE-AM6xx SoMs"Tom Rini2024-11-142-2/+106
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wadim Egorov <w.egorov@phytec.de> says: Our SoMs are available in multiple configurations, managed via device tree overlays. To determine the specific variant in use, we read the EEPROM and apply the appropriate overlays during boot to the device tree used by the OS. Apply overlays for phyCORE-AM62x and phyCORE-AM64x SoMs. Future K3 SoMs will be able to reuse this logic and overlays. Link: https://lore.kernel.org/r/20241030164815.1763506-1-w.egorov@phytec.de
| | * | arm: dts: k3-am642-phycore-som-binman: Add SoM overlaysWadim Egorov2024-11-141-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include SoM dt-overlays that handle variants of our SoMs into u-boot's FIT image. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
| | * | arm: dts: k3-am625-phycore-som-binman: Add SoM overlaysWadim Egorov2024-11-141-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include SoM dt-overlays that handle variants of our SoMs into u-boot's FIT image. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
| * | | ARM: dts: stm32: Sort DH STM32 DHCOM DTSIMarek Vasut2024-11-121-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort the DTSI alphabetically. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | ARM: dts: stm32: Drop duplicate pinmux on DH STM32 DHCOMMarek Vasut2024-11-121-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ethernet0_rmii_pins_a pinmux change has no effect on any DHSOM based hardware. The mco2_pins_a and mco2_sleep_pins_a are both part of stm32mp15-pinctrl.dtsi . Drop both pinmux changes. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | ARM: dts: stm32: Drop remnants of upstream DT switch on DH STM32 DHSOMMarek Vasut2024-11-123-376/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Remove unused local DT copies after the OF_UPSTREAM conversion. Fixes: cccb29fc1270 ("ARM: dts: stm32: Switch to using upstream DT on DH STM32 DHSOM") Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | | armv8: cpu: Implement allow_unaligned()Sam Protsenko2024-11-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usually ARMv8 platforms allow unaligned access for Normal memory. But some chips might not allow it by default, having SCTLR.A bit set to 1 before U-Boot execution. One such example is Exynos850 SoC. As allow_unaligned() is not implemented for ARMv8 at the moment, its __weak implementation is used, which does nothing. That might lead to unaligned access abort, for example when running EFI selftest. Fix that by implementing allow_unaligned() for ARMv8. The issue was found when running EFI selftest on E850-96 board (Exynos850 based): => bootefi selftest $fdtcontroladdr ... Executing 'HII database protocols' "Synchronous Abort" handler, esr 0x96000021, far 0xbaac0991 ... resetting ... Unaligned abort happens in u16_strnlen(), which is called from efi_hii_sibt_string_ucs2_block_next(): u16_strlen(blk->string_text) where 'blk' type is struct efi_hii_sibt_string_ucs2_block. Because this struct is packed, doing "->string_text" makes 'blk' address incremented by 1 byte, which makes it unaligned. Although allow_unaligned() was called in efi_init_early() before EFI selftest execution, it wasn't implemented for ARMv8 CPUs, so data abort happened. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
* | | armv8: Fix get_sctlr() return typeSam Protsenko2024-11-172-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCTLR_EL2 is a 64-bit register [1]. Return its value as long (64 bit) instead of int (32 bit) in get_sctlr() to make sure it's not trimmed. [1] https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/SCTLR-EL2--System-Control-Register--EL2-?lang=en Fixes: 0ae7653128c8 ("arm64: core support") Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | | Merge tag 'u-boot-amlogic-next-20241113' of ↵WIP/14Nov2024-nextTom Rini2024-11-141-518/+0
|\ \ \ | |/ / |/| | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - khadas-vim3{l}: fix userdata size for android config - drop A1 dtsi and other bindings includes in favor of Upstream ones
| * | arm: dts: meson: remove meson-a1.dtsiAlexey Romanov2024-11-131-518/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Amlogic A1, we have to use dtsi from dts/upstream folder. The only difference between this two files is the added cpu temperature node definition in upstream version and additional assigned-clock for USB. This patch is tested on a device with A113L SoC (AD401-like) and everything is okay. So, we can remove legacy arch/arm/dts/meson-a1.dtsi file. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Link: https://lore.kernel.org/r/20241112125836.3239832-2-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | | Merge tag 'u-boot-rockchip-20241111' of ↵Tom Rini2024-11-117-26/+98
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280 - Add board: rk3328: FriendlyElec NanoPi R2S Plus rk3568: Qnap TS433 rk3588: Cool Pi CM5 GenBook - Move rk3399_force_power_on_reset to TPL for puma board;
| * | | rockchip: rk3399: move sysreset-gpio logic to TPLQuentin Schulz2024-11-111-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is provided in the TPL Device Tree, this will trigger a system reset similar to what's currently been done in SPL whenever the RK3399 "warm" boots. Because there's currently only one user of sysreset-gpio logic, and TPL is enabled on that board, so let's migrate the logic and that board to do it in TPL. There are three reasons for moving this earlier: - faster boot time as we don't need to reach SPL to be able to reset the system on a condition we know is already met in TPL, - have less code to be impacted by the issue this system reset works around (that is, "unclean" SoC registers after a reboot), - less confusion around the reason for restarting. Indeed when done from SPL, the following log can be observed: """ U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) Channel 0: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB Channel 1: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB 256B stride Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100) Trying to boot from MMC2 U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) """ possibly hinting at an issue within the SPL when loading the fitImage from MMC2 instead of the normal course of events (a system reset). Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: tpl: allow to call board/SoC-specific code before DRAM initQuentin Schulz2024-11-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This defines a weak tpl_board_init function that can be used for running board/SoC-specific code before the DRAM init happens, similarly to spl_board_init() for SPL. Reviewed-by: Paul Kocialkowski <paulk@sys-base.io> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | rockchip: rk3399: merge CRU check within rk3399_force_power_on_resetQuentin Schulz2024-11-111-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare to support forcing power on reset from TPL which would have the exact same logic, just in an earlier stage, let's merge the CRU check that triggers the power on reset with the rest of the logic. Reviewed-by: Paul Kocialkowski <paulk@sys-base.io> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | board: rockchip: Add FriendlyElec NanoPi R2S PlusJonas Karlman2024-11-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FriendlyElec NanoPi R2S Plus is a single-board computer based on Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC, SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host. Features tested on a NanoPi R2S Plus 2309: - SD-card boot - eMMC boot - Ethernet - USB gadget - USB host Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | board: rockchip: Add support for rk3588 GenBookAndy Yan2024-11-112-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Cool Pi GenBook, it works as a carrier board connect with CM5 SOM. Specification: - Rockchip RK3588 - LPDDR5X 8/32 GB - eMMC 64 GB - HDMI Type A out x 1 - USB 3.0 Host x 1 - USB-C 3.0 with DisplayPort AltMode - PCIE M.2 E Key for RTL8852BE Wireless connection - PCIE M.2 M Key for NVME connection - eDP panel with 1920x1080 Tested by Armbian boot on USB disk. Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03 Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | | board: rockchip: add support for Qnap TS433 devicesHeiko Stuebner2024-11-112-0/+20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qnap TS433 is a 4-bay NAS based around the RK3568. Two SATA bays are connected to the RK3568's own SATA controllers while the other two are connected to a JMicron SATA controller living on the PCIe bus. It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | board: hoperun: Switch to use complete DTS files from upstream DTSLad Prabhakar2024-11-109-206/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For upstream Linux kernel we use below DTBs for HiHope boards: - r8a774a1-hihope-rzg2m-ex.dtb - r8a774e1-hihope-rzg2h-ex.dtb - r8a774b1-hihope-rzg2n-ex.dtb Update the CONFIG_OF_LIST to match the above. Now that we have switched upstream DTS, drop deleting the nodes and also rename the r8a774*-u-boot.dtsi files to r8a774*-ex-u-boot.dtsi to match the OF_LIST files so that the `bootph-all` property gets applied to required nodes in upstream DTS. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
* | | arm: renesas: Fix RZ/G2L GICR base addressPaul Barker2024-11-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When support for the Renesas RZ/G2L SoC was added, the GICR base address for CPU1 was accidentally used. We should instead supply the GICR base address for CPU0 so that interrupts are correctly configured for the CPU core that U-Boot is actually using. Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support") Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
* | | ARM: dts: Drop unused RZ/G2L devicetreesPaul Barker2024-11-108-2220/+0
| | | | | | | | | | | | | | | | | | | | | | | | We are now using the dts/upstream subtree for the RZ/G2L SoC family so we can drop unused devicetree files from arch/arm/dts. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* | | arm: mach-imx: imx8m: re-use SNVS init routineIan Ray2024-11-092-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working with HAB on the i.MX8MP we've encountered a case where a board that successfully authenticates u-boot when booting Linux subsequently fails to properly bring up the RTC. The RTC registers live in the low-power block of the Secure Non-Volatile Storage (SNVS) block. The root cause of the error has been traced to the HAB handing off the SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the Non-Privileged Software Access Enable bit is zero. Configure SNVS to allow unpriv access to SNVS LP for imx8m and imx8mp. This commit generalizes 723f8359c1 ("imx: mx7: snvs: Add an SNVS init routine") to also be used on i.MX8M SoCs, and was testeed on i.MX8MP. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
* | | arm: mach-imx: move snvs moduleIan Ray2024-11-094-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 723f8359c1 ("imx: mx7: snvs: Add an SNVS init routine") noted that the init_snvs() call likely applies to other i.MX processors, and this has been found to be true for i.MX8MP. Move snvs module for future re-use. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com>
* | | ARM: dts: imx: Switch to using upstream DT on DH i.MX6 DHCOMMarek Vasut2024-11-095-95/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable OF_UPSTREAM to use upstream DT and add nxp/imx/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ directory. Signed-off-by: Marek Vasut <marex@denx.de>
* | | imx9: Improve boot mode autodetectionBenjamin Szőke2024-11-091-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve "mmcautodetect=yes" boot mode autodetection to able to use it if CONFIG_ENV_IS_NOWHERE=y is used for i.MX9 SoCs and i.MX93 EVK board. If both CONFIG_ENV_IS_IN_MMC=y and CONFIG_ENV_IS_NOWHERE=y are in the defconfig, CONFIG_ENV_IS_IN_MMC=y will be overiden default CONFIG_ENV_IS_NOWHERE settings. Goal is in this patch to able to use the boot mode autodetection if defconfig use only CONFIG_ENV_IS_NOWHERE=y option (without CONFIG_ENV_IS_IN_MMC) for any i.MX9 SoC. Signed-off-by: Benjamin Szőke <egyszeregy@freemail.hu>
* | | imx: hab: Make imx_hab_is_enabled dependent on FIELD_RETURNPaul Geurts2024-11-096-4/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The decision on whether HAB is enabled is solely based on the SEC_CONFIG fuse. The HAB FIELD_RETURN feature is able to permanently disable HAB on a CPU, after which it is able to boot unsigned firmware. U-Boot however does not take into account the FIELD_RETURN mode, and refuses to boot unsigned software when the feature is enabled. Also take the FIELD_RETURN fuse into account when deciding whether HAB is enabled. When The FIELD_RETURN fuse is blown, HAB is not enabled. Tested on i.MX8M Mini, i.MX8M Plus, i.MX8M Nano and i.MX6ULL Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
* | | imx: hab: rename imx_sec_config_fuse_t to imx_fusePaul Geurts2024-11-096-8/+8
|/ / | | | | | | | | | | | | | | | | | | The imx_sec_config_fuse_t structure is not specific to the sec_config fuse, but can be used for all fuse words. Rename the structure to a more generic name to be reused for other fuses. Signed-off-by: Paul Geurts <paul.geurts@prodrive-technologies.com>
* | Merge patch series "U-boot: arm: Refine the booting on Total Compute"Tom Rini2024-11-041-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leo Yan <leo.yan@arm.com> says: This patch series is to refine the booting on Arm Total Compuate platform. It changes to use the info passed in DTB for initialization DRAM info, and dynamically initializes the booting envoironment variables. Another big change is to use an envoironment file for boot commands, based on it, the series extends to support multiple block devices (MMC and virtio). And the env file is extended for booting Debian. The last commit is to update memory mapping info based on the DRAM info passed via DT binding. Link: https://lore.kernel.org/r/20241025171821.624702-1-leo.yan@arm.com
| * | arm: total_compute: Initialize environment variablesBoyan Karatotev2024-11-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the environment variables 'fdt_addr_r' and 'kernel_addr_r' during the misc init phase. The static configurations are not needed, remove them. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
| * | arm: total_compute: depend on TF-A for hardware descriptionBoyan Karatotev2024-11-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Total Compute, TF-A passes the info via DT binding for the hardware description - includes the serial, memory, and arm_ffa nodes. This commit initializes the fdt base address based on the passed the register x1. The similar implementation has already been done for the raspberry pi, so borrow a lot of it. Co-developed-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
* | | arch: arm: dts: k3-j784s4-r5: Introduce k3-j784s4-r5.dtsiManorit Chawdhry2024-10-303-204/+108
| |/ |/| | | | | | | | | | | Create an SoC R5 dtsi file that could be used at board level R5 files. This would help in keeping the SoC level changes in sync across board files. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
* | Merge tag 'u-boot-imx-master-20241029' of ↵WIP/29Oct2024Tom Rini2024-10-293-1/+119
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23092 - Implement i.MX93 erratum fix on the dwc_eth_qos driver to fix RMII. - Add support for Emcraft Systems NavQ+. - Fix the size of IVT + CSF blob tacked on to u-boot.itb.
| * | board: emcraft: Add support for Emcraft Systems NavQ+Gilles Talis2024-10-292-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Emcraft Systems NavQ+ kit is a mobile robotics platform based on NXP i.MX8 MPlus SoC. The following interfaces and devices are enabled: - eMMC - Gigabit Ethernet (through eQOS interface) - SD-Card - UART console The device tree file is taken from upstream Linux Kernel through OF_UPSTREAM Signed-off-by: Gilles Talis <gilles.talis@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | arm64: imx: Fix 0Xnn to 0xnnMarek Vasut2024-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | Use lowercase 0x prefix for hexadecimal number to be consistent No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* | | Merge patch series "memory: ti-aemif: Add DM support"Tom Rini2024-10-291-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bastien Curutchet <bastien.curutchet@bootlin.com> says: Hi all, This patch series aims to add DM support for the AEMIF controller that can be found in the DaVinci SoCs. This controller has already a driver used by the Keystone SoCs so I add my work to it. As we can now easily import Linux device-trees, I try to stick the most I can to the Linux bindings of the AEMIF controller. To do so I add an 'intermediate' driver called 'ti-aemif-cs'. It's in charge of configuring timings for a given chip select of the AEMIF controller. Link: https://lore.kernel.org/r/20241021151330.1860929-1-bastien.curutchet@bootlin.com
| * | | memory: ti-aemif: Make AEMIF driver architecture agnosticBastien Curutchet2024-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AEMIF controller is present on other SoCs than the Keystone ones. Remove Keystone specificities from the driver to be able to use it from other architectures. Adapt the ks2_evm/board.c to fit the new driver. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2025-03-03 22:06:22 +0000