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* dts: automatically build necessary .dtb filesRasmus Villemoes2022-02-091-0/+2
* doc: replace @return by Return:Heinrich Schuchardt2022-01-192-6/+6
* efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt2022-01-153-6/+7
* riscv: revert Complete efi header for RV32/64Heinrich Schuchardt2022-01-151-10/+0
* riscv: qemu: Split devicetree files for qemu_riscv32/64Simon Glass2021-12-233-1/+15
* riscv: Enable SPI flash env for SiFive Unmatched.Thomas Skibo2021-12-021-0/+13
* riscv: Support booting SiFive Unmatched from SPI.Thomas Skibo2021-12-021-0/+11
* riscv: dts: Split Microchip device treePadmarao Begari2021-12-022-389/+700
* riscv: add #define in asm/io.h for some device driversWei Fu2021-11-081-0/+4
* riscv: function to retrieve SBI implementation versionHeinrich Schuchardt2021-11-082-0/+20
* riscv: Avoid io read/write cause wrong resultNick Hu2021-10-201-9/+9
* riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas2021-10-183-11/+3
* fdtdec: Support reserved-memory flagsThierry Reding2021-10-131-1/+1
* fdtdec: Support compatible string list for reserved memoryThierry Reding2021-10-131-1/+1
* image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass2021-10-081-2/+2
* riscv: ae350: enable Coherence Manager for ae350Leo Yu-Chi Liang2021-10-071-0/+42
* sysreset: provide SBI based sysreset driverHeinrich Schuchardt2021-10-073-1/+25
* riscv: add missing SBI extension definitionsHeinrich Schuchardt2021-10-071-2/+37
* riscv: Fix setting no-map in reserved memory nodesSamuel Holland2021-10-071-4/+1
* lmb: riscv: Add arch_lmb_reserve()Marek Vasut2021-09-231-0/+13
* Merge tag 'v2021.10-rc4' into nextTom Rini2021-09-1614-141/+75
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| * riscv: lib: modify the indentZong Li2021-09-071-1/+1
| * board: sifive: use ccache driver instead of helper functionZong Li2021-09-078-140/+4
| * riscv: lib: implement enable_caches for sifive cacheZong Li2021-09-073-0/+33
| * common: board_r: support enable_caches for RISC-VZong Li2021-09-071-0/+4
| * riscv: show code leading to exceptionHeinrich Schuchardt2021-09-071-0/+33
* | Kconfig: Remove all default n/no optionsMichal Simek2021-08-311-2/+0
* | Finish converting CONFIG_SYS_CACHELINE_SIZE to KconfigTom Rini2021-08-311-0/+2
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* riscv: cpu: fu740: Fix typo of dateZong Li2021-08-171-1/+1
* efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt2021-08-141-2/+5
* i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass2021-07-281-1/+1
* board: sifive: drop stuff related to unmatched revision 1Zong Li2021-07-214-1501/+1
* riscv: booti: do not force relocation if force_reloc is not setVitaly Wool2021-07-211-1/+6
* riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei2021-07-071-2/+2
* riscv: dts: add dts for unmatched rev1Zong Li2021-07-064-1/+1501
* board: sifive: Add an interface to get PCB revisionZong Li2021-07-061-0/+15
* riscv: sifive: fu740: Support i2c in splZong Li2021-07-062-0/+5
* riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li2021-07-061-0/+2
* board: riscv: add openpiton-riscv64 SoC supportTianrui Wei2021-07-063-0/+158
* Merge tag 'v2021.07-rc5' into nextTom Rini2021-06-284-8/+64
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| * riscv: andes_plic: Fix riscv_get_ipi() maskBin Meng2021-06-171-1/+3
| * riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng2021-06-173-0/+54
| * riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng2021-06-171-1/+1
| * riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng2021-06-172-4/+0
| * riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng2021-06-172-2/+2
| * riscv: ae350: dts: Add SPDX license headerBin Meng2021-06-172-0/+4
* | k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson2021-06-171-0/+2
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* riscv: cpu: fu740: clear feature disable CSRGreen Wan2021-05-311-0/+15
* board: sifive: add HiFive Unmatched board supportGreen Wan2021-05-311-0/+4
* riscv: dts: add SiFive Unmatched board supportGreen Wan2021-05-314-0/+1790
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