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* Merge patch series "Add fdt-fixups for AM62P variants"WIP/14Jan2025Tom Rini2025-01-143-0/+210
|\ | | | | | | | | | | | | | | | | | | | | | | | | Aparna Patra <a-patra@ti.com> says: This series implements fdt fixups, by reading hardware information from registers and accordingly delete/modify the DT nodes, at run-time. Logs for AM62P boot: https://gist.github.com/itsme-aparna/b889fe59882c1acf0ef25a644bd325c4 Link: https://lore.kernel.org/r/20250108044939.392785-1-a-patra@ti.com
| * arm: mach-k3: am62p: Set a53 cpu freq based on speed-gradeAparna Patra2025-01-141-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | The maximum frequency of the A53 CPU on the AM62P depends on the speed grade of the SoC. This value is hardcoded in the DT for all AM62P variants, potentially causing specifications to be exceeded. Moreover, setting a common lower frequency for all variants increases boot time. To prevent these issues, modify the DT at runtime from the R5 core to adjust the A53 CPU frequency. Signed-off-by: Aparna Patra <a-patra@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
| * arm: mach-k3: am62p: Fixup a53 max cpu frequency by speed-gradeAparna Patra2025-01-142-0/+31
| | | | | | | | | | | | | | | | | | | | | | AM62P SoC has multiple speed grades. Add function to delete non-relevant CPU frequency nodes, based on the information retrieved from hardware registers. Fastest grade's maximum frequency also depends on PMIC voltage, hence to simplify implementation use the smaller value. Signed-off-by: Aparna Patra <a-patra@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
| * arm: mach-k3: am62p: Fixup thermal zone critical pointsAparna Patra2025-01-142-0/+54
| | | | | | | | | | | | | | | | | | Read the max temperature for the SoC temperature grade from the hardware and modify the critical trip nodes on each thermal zone of FDT at runtime so they are correct with the hardware value for its grade. Signed-off-by: Aparna Patra <a-patra@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
| * arm: mach-k3: am62p: Fixup CPU core, CAN-FD and Video-codec nodes in fdtAparna Patra2025-01-142-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62P SOC is available in multiple variants: -CPU cores (Cortex-A) AM62Px1 (1 core), AM62Px2 (2 cores), AM62Px4 (4 cores) -With and without CAN-FD & Video-codec support Remove the relevant FDT nodes by reading the actual configuration from the SoC registers, with that change it is possible to have a single dts/dtb file handling the different variant at runtime. Signed-off-by: Aparna Patra <a-patra@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
* | Merge patch series "Inline ECC Series"Tom Rini2025-01-147-16/+119
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Santhosh Kumar K <s-k6@ti.com> says: Hello, This series adds support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX, J721E, J721S2, J722S and J784S4 devices. Test Results: https://gist.github.com/santhosh21/88de920771ed2efa0463a5a367cb8d7b Link: https://lore.kernel.org/r/20250106090708.1541212-1-s-k6@ti.com
| * | board: ti: Pull redundant DDR functions to a common location and Fixup DDR ↵Santhosh Kumar K2025-01-143-1/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | size when ECC is enabled As there are few redundant functions in board/ti/*/evm.c files, pull them to a common location of access to reuse and include the common file to access the functions. Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the device tree and resize the available amount of DDR, if ECC is enabled. Otherwise, fixup the device tree using the regular fdt_fixup_memory_banks(). Also call dram_init_banksize() after every call to fixup_ddr_driver_for_ecc() is made so that gd->bd is populated correctly. Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR controllers present. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
| * | arm: mach-k3: Set NR_DRAM_BANKS to 2Neha Malcom Francis2025-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the memory/ node for lower and higher addressible DDR regions. This allows use of FDT functions from fdt_support.c to set up and fix up the memory/ node correctly. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
| * | arm: dts: k3-*-ddr: Add ss_cfg reg entrySanthosh Kumar K2025-01-143-15/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ss_cfg memory region which maps the DDRSS configuration region for the memory controller node. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Neha Malcom Francis <n-francis@ti.com>
* | | Merge patch series "SMBIOS improvements"Tom Rini2025-01-144-0/+380
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raymond Mao <raymond.mao@linaro.org> says: Motivations for changes: Current SMBIOS library and command-line tool is not fully matching with the requirements: 1. Missing support for other mandatory types (#7, #9, #16, #17, #19). 2. Only a few platforms support SMBIOS node from the device tree. 3. Values of some fields are hardcoded in the library other than fetching from the device hardware. 4. Embedded data with dynamic length is not supported (E.g. Contained Object Handles in Type #2 and Contained Elements in Type #3) Changes: 1. Refactor the SMBIOS library and command-line tool to better align with the SMBIOS spec. 2. Create an arch-specific driver for all aarch64-based platforms to fetch SMBIOS private data from the device hardware (processor and cache). 3. Create a sysinfo driver to poppulate platform SMBIOS private data. 4. Add generic SMBIOS DTS file for arm64 platforms for those common strings and values which cannot be retrieved from the system registers. Vendors can create their own SMBIOS node using this as an example. For those boards without SMBIOS nodes, this DTS file can be included to have a generic SMBIOS information of the system. 5. Add support for Type #7 (Cache Information) and link its handles to Type #4. 6. To minimize size-growth for those platforms which have not sufficient ROM spaces or the platforms which don't need detailed SMBIOS information, new added fields are only being built when kconfig GENERATE_SMBIOS_TABLE_VERBOSE is selected. Once this patch is acceptted, subsequent patch sets will add other missing types (#9, #16, #17, #19). Tests: To test this with QEMU arm64, please follow the guide on dt_qemu.rst to get a merged DT to run with. ``` qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \ | dtc - -o merged.dtb qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \ -dtb merged.dtb ``` Link: https://lore.kernel.org/r/20241206225438.13866-1-raymond.mao@linaro.org
| * | | armv8: Add generic smbios information into the device treeRaymond Mao2025-01-142-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common smbios information that can be used by all armv8 platforms and set it as default for qemu-arm64. >From now smbios library can load values from here for those fields doesn't exist in the sysinfo driver. To run this with QEMU arm64, we need to dump the generated DTB from QEMU first, merge it with the one we build and then re-run QEMU with the merged DTB. ``` qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | \ grep -v /dts-v1/) | dtc - -o merged.dtb qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \ -dtb merged.dtb ``` For details please take reference on dt_qemu.rst Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
| * | | armv8: Add arch-specific sysinfo platform driverRaymond Mao2025-01-142-0/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sysinfo platform driver for all armv8 platforms to retrieve hardware information on processor and cache. Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | arm64: zynqmp: Add eeprom labels for System Controller dtsJonathan Stroud2025-01-142-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Label all eeproms so we can open by label rather than a fixed i2c address. Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/878558c3c859599d29bc4ae2278baebf84b368e0.1736152966.git.michal.simek@amd.com
* | | | arm64: zynqmp: Enable iio-hwmon description only for SOMMichal Simek2025-01-142-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Description is coming from SOM only that's why enable it only on SOM. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/08ee4ce2fe242905dd99cea2b87373b57d8fea91.1736152939.git.michal.simek@amd.com
* | | | arm64: zynqmp: Sync DTs with Linux v6.13-rc1Michal Simek2025-01-146-35/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync zynqmp* DTS files with v6.13-rc1 Linux kernel including three patches from Sean: arm64: zynqmp: Enable AMS for all boards arm64: zynqmp: Expose AMS to userspace as HWMON arm64: zynqmp: Add thermal zones Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/06e466d64c9d8e718e2f06a76cc65d6da2a37a7b.1733996500.git.michal.simek@amd.com
* | | | arm64: zynqmp: add clock-output-names property in clock nodesNaman Trivedi2025-01-141-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace underscores with hyphens in the clock node names as per dt-schema rule. Also, add clock-output-names property to all clock nodes, so that the resulting clock name do not change when clock node name is changed. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1080e31393c3e1b49735b77e7ddc14d570b83222.1733991159.git.michal.simek@amd.com
* | | | arm64: zynqmp: Do not use hardcoded address in do_zynqmp_reboot()Michal Simek2025-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | multi_boot is already the part of csu_base structure that's why use it directly instead of using register offset value. Fixes: fc001432e5b0 ("arm64: zynqmp: Add u-boot command to boot into recovery image") Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3e5c6ea426b81cc73b90e6425764e41a98deb2a6.1733735454.git.michal.simek@amd.com
* | | | arm64: Add MIDR entries for Cortex-A57 and Cortex-A76Marek Vasut2025-01-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively. Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* | | | arm64: Convert core type check macros into inline functionsMarek Vasut2025-01-121-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent. Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* | | | rockchip: rk3308: Implement checkboard() to print SoC variantJonas Karlman2025-01-101-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement checkboard() to print current SoC variant used by a board, e.g. one of: SoC: RK3308 SoC: RK3308B SoC: RK3308B-S when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 02 2024 - 20:26:25 +0000) Model: Radxa ROCK Pi S SoC: RK3308B DRAM: 512 MiB (effective 510 MiB) Information about the SoC variant is read from GRF. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
* | | | rockchip: rk3588: Implement checkboard() to print SoC variantJonas Karlman2025-01-102-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3582 SoC: RK3588 SoC: RK3588J SoC: RK3588S SoC: RK3588S2 when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000) Model: Generic RK3588S/RK3588 SoC: RK3588S2 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk356x: Implement checkboard() to print SoC variantJonas Karlman2025-01-102-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3566 SoC: RK3566T SoC: RK3568 SoC: RK3568B2 SoC: RK3568J when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:39:37 +0000) Model: Generic RK3566/RK3568 SoC: RK3568J DRAM: 8 GiB (effective 7.7 GiB) Information about the SoC model and variant is read from OTP. Also update rk356x-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | clk: rockchip: rk3588: fix mask define for aclk_vop_rootHeiko Stuebner2025-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mask for aclk_vop_root is 3-bit wide, not 2-bit wide according to the TRM, so set the mask accordingly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3588-nanopc-t6-lts: Add missing board -u-boot.dtsiJonas Karlman2025-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However, a board specific -u-boot.dtsi file was never added. Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is never tagged with bootph props. When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env can successfully load from SPI flash on the non-LTS variant, something that does not work on the LTS variant due to missing bootph-some-ram props in the LTS fdt. Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS -u-boot.dtsi file. Reported-by: Ricardo Pardini <ricardo@pardini.net> Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399: Drop unneeded bob and kevin board specific codeJonas Karlman2025-01-101-22/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IO-domain driver will configure io_vsel and always-on/boot-on regulators will be enabled based on the board device tree now that required nodes and Kconfig options is enabled for SPL. Remove the bob and kevin board specific code from the common rk3399.c, the IO-domain and regulator driver provide similar functionality. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
* | | | rockchip: rk3399-gru: Include pinctrl and regulators in SPLJonas Karlman2025-01-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootph props and enable related Kconfig options to include vital regulators in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399-gru: Remove unused nodes from xPL control FDTJonas Karlman2025-01-101-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The eMMC PHY and SPI flash is not used in all xPL phases. Change to no longer include emmc_phy and spi_flash in all xPL phases. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399: Drop common Kconfig options already impliedJonas Karlman2025-01-101-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The last two RK3399 boards, chromebook bob and kevin, have now migraded to use common bss and stack addresses. Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig when all boards now use common bss and stack addresses. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom imageJonas Karlman2025-01-101-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image. Change to include the binman generated FIT for the u-boot.rom image. This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399-gru: Fix include of TPL in u-boot.rom imageJonas Karlman2025-01-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chromebook specific u-boot.rom image does not include TPL when building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y. Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node for the u-boot.rom binman image. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset propJonas Karlman2025-01-102-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option instead of a hardcoded 0x40000 for the FIT payload offset. This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399: Fix TPL build of bob and kevinJonas Karlman2025-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building chromebook_bob/kevin with TPL=y ends with a linking error: arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init': arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): undefined reference to `spl_gpio_output' arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output' make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1 make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2 make: *** [Makefile:568: __build_one_by_one] Error 2 Change to only use spl_gpio functions in SPL to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: use OF_UPSTREAM for rk3066a/rk3188Johan Jonker2025-01-109-2856/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree for rk3066a/rk3188 combined is now available in the /dts/upstream directory. Use imply OF_UPSTREAM to migrate all rk3066a/rk3188 boards. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: Add support for Radxa ROCK 5CFUKAUMI Naoki2025-01-102-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer. [1] https://radxa.com/products/rock5/5c Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | board: rockchip: add FriendlyElec NanoPi R3STianling Shen2025-01-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps Ethernet ports designed and developed by FriendlyElec for IoT applications. Specification: - Rockchip RK3566 - 2GB LPDDR4X RAM - optional 32GB eMMC module - SD card slot - 2x 1000 Base-T - 3x LEDs (POWER, LAN, WAN) - 2x Buttons (Reset, MaskROM) - 1x USB 3.0 Port - Type-C 5V 2A Power Signed-off-by: Tianling Shen <cnsztl@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Fix slow Ethernet initializionJonas Karlman2025-01-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Firefly-RK3288 use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Migrate to OF_UPSTREAMJonas Karlman2025-01-104-539/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree for Firefly-RK3288 in dts/upstream can be used as-is by U-Boot, migrate board to use OF_UPSTREAM. Add chosen stdout-path prop to board u-boot.dtsi as it is missing in DT from dts/upstream. Also change to use the upstream power_led symbol. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Include sdmmc regulator in SPLJonas Karlman2025-01-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Include required DT nodes in xPLJonas Karlman2025-01-101-5/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Use common bss and stack addressesJonas Karlman2025-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate to use common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc. ENV_OFFSET is using the default value of 0x3f8000 and is also dropped. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Sort u-boot.dtsi nodes alphabeticallyJonas Karlman2025-01-101-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort the nodes in rk3288-firefly-u-boot.dtsi in alphabetical order. This has no intended change to board DT, this only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-firefly: Drop unused SPL_LED related codeJonas Karlman2025-01-102-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The firefly-rk3288_defconfig build target does not enable the SPL_LED Kconfig option. Drop the unused SPL_LED related code and replace it with a default-state prop to ensure the LED driver enable the LED at U-Boot proper phase. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3399-rockpro64: Hook sysreset gpio to enable full resetPaul Kocialkowski2025-01-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
* | | | rockchip: rk3399-roc-pc: Hook sysreset gpio to enable full resetPaul Kocialkowski2025-01-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Without this patch, reading from the micro sd slot fails after a reset. With this mechanism, U-Boot is able to boot from it reliably. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
* | | | board: rockchip: add Khadas Edge2 RK3588 boardJacobe Zang2025-01-101-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) by Khadas. There are tree variants depending on the DRAM size : 8G and 16G. Specification: Rockchip RK3588S SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MP4 GPU 3x MIPI CSI 4x lanes 2x MIPI-DSI DPHY 4x lanes 32/64GB eMMC 1x USB 2.0, 1x USB 3.0, 2x USB-Type-C 1x HDMI 2.1 output, 1x DP 1.4 output USB PD over USB Type-C Kernel commit: 04d552993522 ("arm64: dts: rockchip: Add Khadas edge2 board") Signed-off-by: Jacobe Zang <jacobe.zang@wesion.com>
* | | | rockchip: rk3288-miqi: Fix slow Ethernet initializionJonas Karlman2025-01-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. MiQi use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-miqi: Migrate to OF_UPSTREAMJonas Karlman2025-01-103-434/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree for mqmaker MiQi in dts/upstream can be used as-is by U-Boot, migrate board to OF_UPSTREAM. The change to use DT from dts/upstream will include minor changes and fixes related to work led and usb otg. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-miqi: Include sdmmc regulator in SPLJonas Karlman2025-01-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-miqi: Include required DT nodes in xPLJonas Karlman2025-01-101-2/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | | rockchip: rk3288-miqi: Use TPL with common bss and stack addressesJonas Karlman2025-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate to use TPL, common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc. ENV_OFFSET is using the default value of 0x3f8000 and is also dropped. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-03-03 23:21:59 +0000