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* x86: cpu: Add missing header inclusionAndy Shevchenko2024-10-181-0/+1
| | | | | | | | | | | | | | Without asm/cpu_x86.h inclusion a compiler is not happy: arch/x86/cpu/cpu_x86.c:14:5: warning: no previous prototype for ‘cpu_x86_bind’ [-Wmissing-prototypes] arch/x86/cpu/cpu_x86.c:29:5: warning: no previous prototype for ‘cpu_x86_get_vendor’ [-Wmissing-prototypes] arch/x86/cpu/cpu_x86.c:41:5: warning: no previous prototype for ‘cpu_x86_get_desc’ [-Wmissing-prototypes] arch/x86/cpu/cpu_x86.c:55:5: warning: no previous prototype for ‘cpu_x86_get_count’ [-Wmissing-prototypes] Add missing header inclusion. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: cpu: Add a few prototypes to the header fileAndy Shevchenko2024-10-181-0/+7
| | | | | | | | | | | | The compiler is not happy to have no prototypes for the functions that are not defined static. Add them. This helps avoiding the compiler warnings: arch/x86/cpu/cpu.c:197:13: warning: no previous prototype for ‘board_final_init’ [-Wmissing-prototypes] arch/x86/cpu/cpu.c:205:13: warning: no previous prototype for ‘board_final_cleanup’ [-Wmissing-prototypes] arch/x86/cpu/cpu.c:307:5: warning: no previous prototype for ‘reserve_arch’ [-Wmissing-prototypes] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: cpu: Mark a few functions staticAndy Shevchenko2024-10-183-3/+3
| | | | | | | | | | | | | Some functions are not used anywhere except the same file where they are defined. Mark them static. This helps avoiding the compiler warnings: arch/x86/cpu/cpu.c:343:6: warning: no previous prototype for ‘detect_coreboot_table_at’ [-Wmissing-prototypes] arch/x86/cpu/mtrr.c:90:6: warning: no previous prototype for ‘mtrr_write_all’ [-Wmissing-prototypes] arch/x86/cpu/i386/interrupt.c:240:6: warning: no previous prototype for ‘__do_irq’ [-Wmissing-prototypes] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: cpu: Use default print_cpuinfo() for allAndy Shevchenko2024-10-189-58/+5
| | | | | | | | | | | | | Most of the copies of the print_cpuinfo() call the default method. Remove all of those in order to have only the default one when no `cpu` command is compiled. This also helps avoiding compiler warning, e.g.: arch/x86/cpu/tangier/tangier.c:23:5: warning: no previous prototype for ‘print_cpuinfo’ [-Wmissing-prototypes] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* expo: Allow menu items to have valuesSimon Glass2024-10-181-0/+3
| | | | | | | | | | | | At present menu items are stored according to their sequence number in the menu. In some cases we may want to have holes in that sequence, or not use a sequence at all. Add a new 'value' property for menu items. This will be used for reading and writing, if present. If there is no 'value' property, then the normal sequence number will be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: dts: Add missing sandbox, emul phandle to sandbox-pmicMarek Vasut2024-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | This phandle was missing in the sandbox DT, add it, otherwise sandbox-i2c driver cannot look up the emulator via i2c_emul_find(). This fixes the following i2c_emul_find() error: " $ ./u-boot -Dc "" ... i2c_emul_find() No emulators for device 'sandbox_pmic' sandbox_pmic_write() write error to device: 0000000018c568d0 register: 0x0! out_set_value() PMIC write failed: -5 i2c_emul_find() No emulators for device 'sandbox_pmic' sandbox_pmic_write() write error to device: 0000000018c568d0 register: 0x0! out_set_value() PMIC write failed: -5 ... " Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* sandbox_spl: Restrict use of UPL when not enabledSimon Glass2024-10-181-2/+3
| | | | | | | | | | | With sandbox_spl we want to use the file-based boot in CI, so that this flow is tested. The recent UPL change enabled booting via that method, thus overriding the file-based boot. Correct this by using UPL only when the --upl flag is given. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 91fde8e1764 ("sandbox: Add an SPL loader for UPL")
* x86: coreboot: Add timestamps from coreboot to bootstageSimon Glass2024-10-181-0/+2
| | | | | | | | Receiving timestamps from coreboot was unceremoniously dropped some time ago. Add it back. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 8ad01ce36f7 ("x86: Remove x86 specific GD flags as they are...")
* x86: coreboot: Update the timestamp code to use sysinfoSimon Glass2024-10-181-4/+7
| | | | | | | Rather than using a special variable, get the timestamp info from the coreboot sysinfo struct. Return a proper error as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Ensure the CPU identity exists for timer initSimon Glass2024-10-183-0/+20
| | | | | | | | | When bootstage is used the timer can be inited before the CPU identity is set up, resulting in the checks for the vendor not working. Add a special call to work around this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Show the CPU vendor in bdinfoSimon Glass2024-10-183-40/+69
| | | | | | | Refactor the cpu code and use it to show the CPU vendor, e.g. AuthenticAMD or GenuineIntel Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make default_print_cpuinfo be a weak alias for print_cpuinfoTom Rini2024-10-186-25/+2
| | | | | | | | While a few SoCs have a unique print_cpuinfo function, a number of them just use default_print_cpuinfo. Make default_print_cpuinfo have a weak alias to provie print_cpuinfo. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-imx-master-20241018a' of ↵Tom Rini2024-10-183-477/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22796 - Switch to using upstream DT on DH i.MX8MP DHCOM PDK2/PDK3. - Add ability to build fallback DTBOs from arch/$(ARCH)/dts. - Remove fdt_high and initrd_high env variables from imx6-dhcom. - Add dummy clk for imx8. - Fix DT corruption in imx8_cpu. - Improve DDR stability on pico-imx7d.
| * arm64: dts: imx: Switch to using upstream DT on DH i.MX8MP DHCOM PDK2/PDK3Marek Vasut2024-10-183-477/+0
| | | | | | | | | | | | | | | | | | Enable OF_UPSTREAM to use upstream DT and add freescale/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi and DTBOs from arch/$(ARCH)/dts/ directory. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de>
* | Merge tag 'u-boot-at91-fixes-2025.01-a' of ↵Tom Rini2024-10-181-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 fixes for the 2025.01 cycle: This small set includes the maintainer e-mail update and a missing header that was causing some build issues.
| * | ARM: at91: clock: Add missing include of asm/io.hAlexander Dahl2024-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In one inline function in this header `readl()` is used, but the declaration was not found, so buildman gave this warning: w+include/asm/arch/clk.h: In function 'get_h32mxdiv': w+include/asm/arch/clk.h:65:16: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Fixes: 927b901b47a6 ("ARM: atmel: add sama5d4ek board support") Signed-off-by: Alexander Dahl <ada@thorsis.com>
* | | Merge patch series "Cleanup dma device in spl and move dma channel[0]"Tom Rini2024-10-171-1/+23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prasanth Babu Mantena <p-mantena@ti.com> says: The channel allocation and deallocation for dma copy was happening on every dma transfer. This is a overhead for transactions like NAND, which does page reads recursively for complete data. So, moving the dma allocation to probe and implement corresponding remove function and cleanup dma device while exiting from spl. Enable SPL_DM_DEVICE_REMOVE, for device removal capability in SPL. Link: https://lore.kernel.org/r/20241009145703.1970034-1-p-mantena@ti.com
| * | | mach-k3: common.c: Remove dma device in spl exitPrasanth Babu Mantena2024-10-171-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While exiting from spl, remove any dma device active through spl_board_prepare_for_boot(). This is required for cleaning up any dma channels being used in spl and avoid issues with overlapping channel allocation in the next stage bootloaders. Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
* | | | arm: dts: k3-j722s-binman: Add support for HS-SEUdit Kumar2024-10-171-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J722S SOC have two variants as HS-FS and HS-SE. Add binman support for HS-SE variant. Signed-off-by: Udit Kumar <u-kumar1@ti.com> [j-choudhary@ti.com: Fix load-dm-data entry and indentation] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
* | | | arm: mach-k3: j784s4: Add clk and power support for wkup_uartBhavya Kapoor2024-10-172-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clk and device data which can be used by wkup_uart driver to configure clocks and PSC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
* | | | arm: mach-k3: am62: fixup thermal cooling device cpusParth Pancholi2024-10-171-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM62x devices now support CPU throttling based on thermal alerts with a Linux commit 10e7bfd8114c ("arm64: dts: ti: k3-am62: Enable CPU freq throttling on thermal alert"). However, this functionality does not work correctly across all variants of the AM62x SoCs which have different numbers of Cortex-A CPU cores: AM62x1 (1 core), AM62x2 (2 cores), and AM62x4 (4 cores). On single-core and dual-core AM62x devices, the following error is observed in the Linux kernel: OF: /thermal-zones/main0-thermal/cooling-maps/map0: could not find phandle 94 OF: /thermal-zones/main1-thermal/cooling-maps/map0: could not find phandle 94 This commit adds a fixup to dynamically adjust the cooling-device nodes in the thermal zones based on the actual number of CPU cores available. This resolves the issue of CPU throttling not working correctly on single-core and dual-core AM62x devices, while maintaining the functionality for AM62x quad-core devices. A similar approach is implemented for example on i.MX8MM SoC. Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
* | | | Merge tag 'u-boot-stm32-20241017' of ↵Tom Rini2024-10-1729-2878/+101
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/22732 - stm32mp: fix boot issue with OP-TEE - stm32mp: Add script to install U-Boot from SD/eMMC to SPI NOR on DH STM32MP15xx - stm32mp: Switch to using upstream DT on DH STM32 DHSOM - stm32mp: Generate u-boot.itb using binman on DH STM32 DHSOM
| * | | | stm32mp: fix name of optee reserved memory nodePatrick Delaunay2024-10-161-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In OP-TEE, the "optee_core@" node is reserved, appended in non secure device tree (see mark_tzdram_as_reserved() function under CFG_DT) so this name must be checked in optee_get_reserved_memory(). We keep the check on /reserved-memory/optee@ node to have backward compatibility with STMT32Image booting, when the reserved node is already present in U-Boot or SPL device tree with name "optee@". This patch solves a boot issue on board with OP-TEE for U-Boot compiled with stm32mp15_defconfig and without secure configuration device tree (stm32mp157c-dk2.dts for example). Fixes: 5fe9e0deabb1 ("stm32mp: allow calling optee_get_reserved_memory() from U-Boot") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | ARM: stm32mp: enable data cache after LMB configuration for STM32MP1Patrick Delaunay2024-10-162-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the stm32mp1 data cache reconfiguration after the lmb init call board_r::initr_lmb to allow parsing of the reserved region with no-map tag. After this patch the DDR is not fully mapped up to arch_early_init_r() call, only the relocation region is mapped, but it is enough for the first board_r initialization phases; later, when arch_early_init_r() is called, the LMB is already initialized and the function lmb_is_reserved_flags() function is functional, this LMB function is called in the weak function dram_bank_mmu_setup() when dcache_enable() is executed. Without this change, as LMB is not initialized when it is used in dram_bank_mmu_setup, the OP-TEE region is mapped cache-able by U-Boot and we have some firewall violation since "LMB memory map global and persistent" series. Fixes: ed17a33fed29 ("lmb: make LMB memory map persistent and global") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | stm32mp: compute ram_top based on the optee base address only for STM32MP1Patrick Delaunay2024-10-161-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reserved memory for OP-TEE is located at end of DDR for STM32MP1 SoC only (STM32MP13 and STM32MP15) and the OP-TEE reserved memory is located at the beginning of DDR for STM32MP25 SoC, before CONFIG_TEXT_BASE and with reserved memory for companion coprocessor. So the ram_top is limited by OP-TEE reserved memory only for STM32MP1 SoC. This patch solves an issue for ram_top value on STM32MP25 SoC because the generic reserved memory management, based on LMB, is no more used before relocation. Fixes: 8242f14a3e6f ("stm32mp: compute ram_top based on the optee base address") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | ARM: dts: stm32: Generate u-boot.itb using binman on DH STM32 DHSOMMarek Vasut2024-10-163-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Describe the u-boot.its generation in stm32mp15xx-dhsom-u-boot.dtsi binman {} DT node as a replacement for current CONFIG_SPL_FIT_SOURCE use, dispose of both u-boot-dhcom.its and u-boot-dhcor.its. Use fdt-SEQ/config-SEQ to generate a list of fdt-N fitImage images {} and matching configuration {} node entries. The configuration node entry names no longer encode _somrevN_boardrevN suffix, which was never really used, so drop this functionality by default. Rework board_fit_config_name_match() to match on the new configuration node entry names. Users who do need the match on _somrevN_boardrevN can either replace the fdt-SEQ/config-SEQ with fixed fdt-N/config-N nodes which each encode the matching 'description = "NAME_somrevN_boardrevN"' to restore the old behavior verbatim, or better use SPL DT overlays for U-Boot control DT the same way e.g. i.MX8MP DHCOM does to support multiple SoM and board variants. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | ARM: dts: stm32: Switch to using upstream DT on DH STM32 DHSOMMarek Vasut2024-10-1622-2865/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable OF_UPSTREAM to use upstream DT and add st/ prefix to the DEFAULT_DEVICE_TREE. And thereby directly build DTB from dts/upstream/src/ including *-u-boot.dtsi from arch/$(ARCH)/dts/ directory. The previous setup used generic SoC prefix like stm32mp15xx-dhco* for generic DTs which could be used on any STM32MP15xx DHSOM variant. The new setup uses specific SoC prefix stm32mp157c-dhco* to match Linux DT names. Since the hardware present on STM32MP153 and STM32MP157 is not enabled in the board configuration and not supported by U-Boot except for the DSI host, using the existing Linux DTs poses no issue even on plain STM32MP151A based SoMs. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | ARM: dts: stm32: Duplicate cpu0-opp-table node into stm32mp15-u-boot.dtsiMarek Vasut2024-10-161-8/+22
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu0-opp-table {} node does not exist in upstream Linux stm32mp151.dtsi file, in order to enable conversion to OF_UPSTREAM, duplicate the node from current U-Boot stm32mp151.dtsi into stm32mp15-u-boot.dtsi. This makes STM32 DTs buildable even with OF_UPSTREAM enabled. No functional change, since the current U-Boot stm32mp151.dtsi already contains the cpu0-opp-table {} node, stm32mp15-u-boot.dtsi is applied at the end, and does not bring in any new content. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* / | | rockchip: rk3588-rock-5b: Add USB-C controller to u-boot.dtsiSebastian Reichel2024-10-171-0/+28
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB-C controller (fusb302), which will be used by U-Boot to initialize USB-PD. This is needed, because USB-PD communication must happen within 5 seconds after the USB-C connector got plugged. On my Rock 5B it often takes 5 seconds to jump to the Linux binary, so it must happen before Linux is initialized. This adds the DT node to the U-Boot specific file, since the Linux kernel DT currently does not describe it to avoid a system reset. The plan is to add it to the Linux DT with status = 'fail' and then let U-Boot mark it as status = 'okay' if it properly dealt with early USB-PD initialization. Until the Kernel DT has the node, let's add it in U-Boot to get things going. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Soeren Moch <smoch@web.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* | | x86: e820: use the lmb API for adding RAM memorySughosh Ganu2024-10-151-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | The EFI_CONVENTIONAL_MEMORY type is now being managed through the LMB module. Add a separate function, lmb_arch_add_memory() to add the RAM memory to the LMB memory map. The efi_add_known_memory() function is now used for adding any other memory type to the EFI memory map. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
* | | layerscape: use the lmb API's to add RAM memorySughosh Ganu2024-10-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The EFI memory allocations are now being done through the LMB module, and hence the memory map is maintained by the LMB module. Use the lmb_arch_add_memory() API function to add the usable RAM memory to the LMB's memory map. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
* | | stm32mp: remove efi_add_known_memory() function definitionSughosh Ganu2024-10-151-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The efi_add_known_memory() function for the stm32mp platforms is adding the EFI_CONVENTIONAL_MEMORY type. This memory is now being handled through the LMB module -- the lmb_add_memory() adds this memory to the memory map. Remove the definition of the now superfluous efi_add_known_memory() function. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ti: k3: remove efi_add_known_memory() function definitionSughosh Ganu2024-10-151-11/+0
| |/ |/| | | | | | | | | | | | | | | | | | | | | The efi_add_known_memory() function for the TI K3 platforms is adding the EFI_CONVENTIONAL_MEMORY type. This memory is now being handled through the LMB module -- the lmb_add_memory() adds this memory to the memory map. Remove the definition of the now superfluous efi_add_known_memory() function. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dts: Deduplicate dtbs targetWIP/14Oct2024Marek Vasut2024-10-1412-96/+6
| | | | | | | | | | | | | | | | | | | | | | The dtbs: target is almost identical in all architecture Makefiles. All architecture Makefiles include scripts/Makefile.dts . Deduplicate the dtbs: target into scripts/Makefile.dts . No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom, OF_UPSTREAM
* | Merge tag 'u-boot-amlogic-next-20241014' of ↵Tom Rini2024-10-143-4/+30
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic - Add Libre Computer boards into proper libre-computer board directory - Add new Boards: - Libre Computer aml-s905d3-cc - Libre Computer aml-a311d-cc - Add capsule update to libretech-ac and the new boards since they have an onboard SPI nor flash - Fix HDMI support after sync to v6.11 and regulator enable from Marek - Fix khadas-vim3 android config for android-mainline kernel - Disable meson64 boot targets when configs are not eavailable
| * | dts: meson-g12-common-u-boot: do not disable canvasNeil Armstrong2024-10-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were disabling canvas, which causes meson vpu probe failure, just stop and leave canvas alone. Fixes: ce9fa7bffc5 ("ARM: dts: meson-g12a: add U-Boot specific DT for graphics") Link: https://lore.kernel.org/r/20241008-u-boot-topic-g12-do-not-disable-canvas-v1-1-b89659370012@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * | ARM: meson: add support for Libre Computer aml-s905d3-ccNeil Armstrong2024-10-141-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Libre Computer aml-s905d3-cc "Solitude" board: https://libre.computer/products/aml-s905d3-cc/ The Solitude board has a Credit Card form factor, similar to the the previous "Le Potato" card, but with the Amlogic A311D SoC, MIPI DSI and CSI connectors. PoE header and a single USB2 Type-C connector replacing the microUSB one for power and USB 2.0. The board has an embedded SPI NOR flash, and EFI Capsule support is added. The GUID is dynamically generated for the board, to get it: => efidebug capsule esrt ======================================== ESRT: fw_resource_count=1 ESRT: fw_resource_count_max=1 ESRT: fw_resource_version=1 [entry 0]============================== ESRT: fw_class=4302C3CB-2502-5EFE-87E0-894A8A322893 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success ======================================== On the host (with the aml_encrypt_g12a result binary): $ eficapsule --guid 4302C3CB-2502-5EFE-87E0-894A8A322893 -i 1 u-boot.bin u-boot.cap On the board (from USB disk containing u-boot.cap at root): => load usb 0:1 $kernel_addr_r u-boot.cap => efidebug capsule update $kernel_addr_r The binary will then be flashed on the SPI. Link: https://lore.kernel.org/r/20240920-u-boot-topic-libre-computer-solitude-alta-v1-2-8915b108840b@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * | ARM: meson: add support for Libre Computer aml-a311d-ccNeil Armstrong2024-10-141-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Libre Computer aml-a311d-cc "Alta" board: https://libre.computer/products/aml-a311d-cc/ The Alta board has a Credit Card form factor, similar to the the prvevious "Le Potato" card, but with the Amlogic A311D SoC, MIPI DSI and CSI connectors. PoE header and a single USB2 Type-C connector replacing the microUSB one for power and USB 2.0. The board has an embedded SPI NOR flash, and EFI Capsule support is added. The GUID is dynamically generated for the board, to get it: => efidebug capsule esrt ======================================== ESRT: fw_resource_count=1 ESRT: fw_resource_count_max=1 ESRT: fw_resource_version=1 [entry 0]============================== ESRT: fw_class=17E07D9D-4D91-53F4-8780-1D91F279C1A5 ESRT: fw_type=unknown ESRT: fw_version=0 ESRT: lowest_supported_fw_version=0 ESRT: capsule_flags=0 ESRT: last_attempt_version=0 ESRT: last_attempt_status=success ======================================== On the host (with the aml_encrypt_g12a result binary): $ eficapsule --guid 17E07D9D-4D91-53F4-8780-1D91F279C1A5 -i 1 u-boot.bin u-boot.cap On the board (from USB disk containing u-boot.cap at root): => load usb 0:1 $kernel_addr_r u-boot.cap => efidebug capsule update $kernel_addr_r The binary will then be flashed on the SPI. Link: https://lore.kernel.org/r/20240920-u-boot-topic-libre-computer-solitude-alta-v1-1-8915b108840b@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | | Merge branch 'u-boot-nand-20241012' of ↵Tom Rini2024-10-143-133/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-nand-flash This merge request add support for BCMBCA raw nand driver for bcm96846 board that switch using OF_UPSTREAM and allow use onfi ecc params when they are available in the atmel nand controller The patches pass the pipeline CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22638
| * | | board: bcm96846: Switch to using OF_UPSTREAMLinus Walleij2024-10-123-133/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board clearly develops first in Linux which had more hardware listed, so let's start to use OF_UPSTREAM. This makes the NAND driver work. Suggested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | drivers: nand: bcmbca: Enable on BCM6846Linus Walleij2024-10-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BCM6846 has the BRCMBCA NAND controller so enable it. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/13Oct2024Tom Rini2024-10-1321-3116/+111
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This switches all boards with the Allwinner H616/H618/H313/H700 SoCs over to use OF_UPSTREAM. We are doing it for this SoC family only since the DTs between the U-Boot and the kernel repo are exactly identical, whereas other families have one compatibility fix in U-Boot to allow booting older kernels. Other will follow if this plays out well. The biggest chunk otherwise is adding support for an Anbernic game console, using the H700 SoC. For that we need to enhance the DRAM support code, and pick two DT commits from the mainline kernel/DT rebasing repo, followed by the defconfig patch. On top of that two small fixes for the old Allwinner A80. Gitlab CI passed, and I booted that briefly on some boards, including an H616 and an H618 one (with LPDDR4).
| * | | | sunxi: H616: dram: Update mbus prioritiesJernej Skrabec2024-10-101-20/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CSI1 channel (22) is missing and IOMMU (25) has priority flag set in vendor bootloader. Fix that. While at it, replace bandwidth flag with priority since original flag has always value "true". Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
| * | | | sunxi: H616: DRAM: Adjust size scan procedureJernej Skrabec2024-10-101-13/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's safer to start scanning for columns first and then rows. Columns reside on LSB address pins, which means that second configuration will already have all needed row pins active. This is also preparation for introducing DDR4 support, which need scan for banks and bank groups too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Chris Morgan <macromorgan@hotmail.com>
| * | | | sunxi: H616: DRAM: Adjust configuration procedureJernej Skrabec2024-10-101-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When comparing configuration procedure to vendor driver, I noticed that one command was out of order and that some delays were missing. Fix that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Chris Morgan <macromorgan@hotmail.com>
| * | | | sunxi: H616: DRAM: Add alternative pin mappingChris Morgan2024-10-102-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that different dies need different PHY pin mapping. Select alternatives at compile time. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> [adapted to switch from runtime to compile time config] Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
| * | | | sunxi: H616: dram: LPDDR4: adjust settingsJernej Skrabec2024-10-102-11/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust H616 LPDDR4 DRAM settings to be in line with vendor driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Chris Morgan <macromorgan@hotmail.com>
| * | | | sunxi: H616: switch to OF_UPSTREAMAndre Przywara2024-10-1019-3070/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent "old-style sunxi" sync and the penultimate OF_UPSTREAM DT update, both directories were based on the same v6.10 kernel tree. And while there is one subtle difference in many Allwinner SoC's DT files, the H616 ones turn out to be identical. Remove the old copies of the H616 related .dts and .dtsi files, and switch the whole H616 SoC over to use OF_UPSTREAM. This immediately benefits from the recent upstream DT update, to kernel v6.11. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | | Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-shTom Rini2024-10-131-4/+7
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| * | | | sh: cache: Fill in invalidate_icache_all()Marek Vasut2024-10-131-4/+7
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement invalidate_icache_all() by clearing all V bits in IC and OC. This is done by setting CCR cache control register ICI and OCI bits. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com> Cc: u-boot@lists.denx.de
generated by cgit (git 2.34.1) at 2025-03-01 01:07:37 +0000