| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: Rename SiFive CLINT to RISC-V ALINT | Bin Meng | 2023-07-12 | 1 | -1/+1 |
| * | Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE | Simon Glass | 2022-10-31 | 1 | -1/+1 |
| * | riscv: dts: add OpenPiton RISC-V board dts support | Tianrui Wei | 2021-07-07 | 1 | -1/+2 |
| * | board: riscv: add openpiton-riscv64 SoC support | Tianrui Wei | 2021-07-06 | 4 | -0/+86 |
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