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* arm: mvebu: turris_omnia: Specify VHV gpio for eFUSE programmingPali Rohár2022-10-061-0/+2
| | | | | | | | | | | | | | VHV gpio is connected to MCU and only on updated board design. Without it eFUSE programming does not work. Omnia MCU driver exports this GPIO to U-Boot under name mcu_56 and only when it is supported by MCU. So U-Boot fuse command refuse eFUSE programming on older board design when VHV gpio is not available. We tested that Armada 385 without connected VHV gpio can do eFUSE programming but only for some bits and only sometimes - it is unstable. And better to be disabled on older board design without VHV gpio support. Signed-off-by: Pali Rohár <pali@kernel.org>
* board/km: remove kirkwood boardsHolger Brunck2022-10-066-497/+0
| | | | | | | These boards are out of maintenance and can be removed. Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge branch 'next'WIP/03Oct2022Tom Rini2022-10-03125-358/+1545
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| * Merge tag 'u-boot-stm32-20220927' of ↵Tom Rini2022-09-2712-25/+16
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm into next - Increase SYS_MALLOC_F_LEN for STM32 MCU's board - SPL fixes for STM32F7 MCUs - Device tree alignement with kernelv6.0-rc4 for MCU's board - Device tree alignement with kernelv6.0-rc3 for MPU's board - Update DDR node for STM32MP15 - Cleanup config file for STM32MP1 - Update for cmd_stm32key command - Fix compatible string to add partitions for STM32MP1 - Update for stm32programmer tool
| | * configs: increase SYS_MALLOC_F_LEN for STM32 MCU's boardPatrice Chotard2022-09-2712-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some STM32 MCU's board need their SYS_MALLOC_F_LEN value enlarged to avoid the "alloc space exhausted" error message during their boot process. Use the default SYS_MALLOC_F_LEN value which is set to 0x2000 in Kconfig. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * configs: stm32f769-disco: Fix internal flash sizePatrice Chotard2022-09-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| | * configs: stm32746g-eval: Fix CONFIG_SYS_SPL_ARGS_ADDRPatrice Chotard2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| | * configs: stm32f746-disco: Fix CONFIG_SYS_SPL_ARGS_ADDRPatrice Chotard2022-09-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| | * configs: stm32746g-eval: Fix SPL bootPatrice Chotard2022-09-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| | * configs: stm32f769-disco: Fix SPL bootPatrice Chotard2022-09-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| | * configs: stm32f746-disco: Fix SPL bootPatrice Chotard2022-09-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
| * | Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵WIP/26Sep2022-nextTom Rini2022-09-262-0/+203
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
| | * | arm64: versal-net: Add support for mini configurationMichal Simek2022-09-261-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Versal NET mini configuration is designed for running memory test. Current output is on DCC but changing serial0 alias to pl011 will move console to serial port. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
| | * | arm64: versal-net: Add defconfig for Versal NETMichal Simek2022-09-261-0/+131
| | |/ | | | | | | | | | | | | | | | | | | | | | Use one defconfig for supporting multiple different platforms. DTB reselection is enabled to choose DT based on SOC detection. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/82cc7c1ca8850270cc2ebc992d835a37aa3d236f.1663589964.git.michal.simek@amd.com
| * | Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini2022-09-265-3/+4
| |\ \ | | | | | | | | | | | | into next
| | * | riscv: ae350: Disable AVAILABLE_HARTSRick Chen2022-09-262-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable AVAILABLE_HARTS mechanism to make sure that all harts can boot to Kernel shell successfully. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| | * | spl: introduce SPL_XIP to configNikita Shubin2022-09-262-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
| * | | sandbox: Convert to use driver model for SCSISimon Glass2022-09-257-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox is producing a warning about SCSI migration. Drop the legacy code and replace it with a new implementation. Also drop the SATA command, which does not work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Enable SCSI for all buildsSimon Glass2022-09-255-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be needed to run unit tests, once the SCSI code is used for USB as well. Enable it for all sandbox builds. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | board: mediatek: add MT7981 reference boardsWeijie Gao2022-09-233-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | | board: mediatek: add MT7986 reference boardsWeijie Gao2022-09-233-0/+194
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add general board files based on MT7986 SoCs. MT7986 uses one mmc controller for booting from both SD and eMMC. Both MT7986A and MT7986B use the same pins for spi controller. Configs for various boot types: 1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B 2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only 3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * | Merge branch 'next' of ↵WIP/20Sep2022-nextTom Rini2022-09-204-4/+5
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-marvell into next - Enable CONFIG_TIMER for all Kirkwood / MVEBU boards (Stefan) - u-boot-spl.kwb/SPL: Add / improve size limit setup / detection (Pali) - mvebu: theadorable: Misc updates in defconfig und dts (Stefan)
| | * | kirkwood: lsxl: Sync defconfigsStefan Roese2022-09-202-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent changes in the Orion timer driver Kconfig setup, the board specific enabling is not needed any more. This patch sync's these 2 boards with their current defconfig version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Michael Walle <michael@walle.cc> Tested-by: Tony Dinh <mibodhi@gmail.com>
| | * | arm: mvebu: theadorable: Misc defconfig changesStefan Roese2022-09-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove EFI support as it's not used on this board - Disable CONFIG_FIT_PRINT to reduce the serial output (minimal speedup) Signed-off-by: Stefan Roese <sr@denx.de>
| | * | arm: mvebu: turris_omnia: Add CONFIG_BOARD_SIZE_LIMITPali Rohár2022-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Maximal size of u-boot kwb image binary is $CONFIG_ENV_OFFSET which is 0xF0000 = 983040 bytes. So add missing CONFIG_BOARD_SIZE_LIMIT definition to ensure that u-boot binary does not overflow to the u-boot env storage. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | Merge tag 'u-boot-at91-2023.01-a' of ↵Tom Rini2022-09-201-0/+4
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2023.01 cycle: This feature set includes the important update on PIO4 pinctrl driver that solves a long time mismatch between Linux and U-boot, related on the unification of pinctrl and gpio driver support, now respecting the pinctrl bindings ABI; and also support for pinctrl subnodes. The feature set also adds support for PDA screen detection for sam9x60_curiosity board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks.
| | * | configs: sama9x60_curiosity: add onewire and eeprom driversDurai Manickam KR2022-09-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAM9X60 SoC can have extra clip boards (PDAs) connected, which have an EEPROM memory for identification. A special GPIO can be used to read this memory over 1wire protocol. Enabling one wire and eeprom drivers for this memory. Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
| * | | Merge branch 'master' into nextTom Rini2022-09-1932-24/+367
| |\ \ \ | | |/ / | |/| | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | configs: Resync with savedefconfigTom Rini2022-09-1633-59/+13
| | | | | | | | | | | | | | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | blk: Drop unnecessary CONFIG_SPL_LEGACY_BLOCK in defconfigsSimon Glass2022-09-165-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is defined automatically when needed, so drop it from the few defconfig files that define it manually. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | blk: Rename HAVE_BLOCK_DEVICESimon Glass2022-09-165-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option is fact really related to SPL. For U-Boot proper we always use driver model for block devices, so CONFIG_BLK is enabled if block devices are in use. It is only for SPL that we have two cases: - SPL_BLK is enabled, in which case we use driver model and blk-uclass.c - SPL_BLK is not enabled, in which case (if we need block devices) we must use blk_legacy.c Rename the symbol to SPL_LEGACY_BLOCK to make this clear. This is different enough from BLK and SPL_BLK that there should be no confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | blk: Enable CONFIG_BLK for all mediaSimon Glass2022-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable this option on all boards which support block devices. Drop the related depencies on BLK since these are not needed anymore. Disable BLOCK_CACHE on M5253DEMO as this causes a build error. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | Nokia RX-51: Set default SYS_LOAD_ADDR to 0x80008000Pali Rohár2022-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At address 0x80000100 are stored initial atags passed to U-Boot by NOLO. So do not overwrite them when using $loadaddr variable which value is set from CONFIG_SYS_LOAD_ADDR option. Signed-off-by: Pali Rohár <pali@kernel.org>
| * | | configs: Add configs for j721s2 High Security EVMJayesh Choudhary2022-09-152-0/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add j721s2 High Security EVM defconfig. These configs are same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_BOOTCOMMAND uses FIT images for booting Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
| * | | configs: Add configs for J7200 High Security EVMAndrew Davis2022-09-152-0/+380
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add J7200 High Security EVM defconfig. These defconfigs are the same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_BOOTCOMMAND uses FIT images for booting Signed-off-by: Andrew Davis <afd@ti.com> [j-choudhary@ti.com: add few configs from GP variant which were missing] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
| * | | brppt1: Update environment to support new boot conceptBernhard Messerklinger2022-09-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Drop legacy /boot/PPTImage.md5 check * Update device tree naming * Update t30args#0 root cmd line property to support latest kernel versions (root=/dev/mmcblk0p2 for linux < 4 and root=/dev/mmcblk1p2 for linux >= 4) * Add custom bootloader version string * Destroy invalid dtb at ${dtbaddr} and configuration script at ${cfgaddr} to ensure proper boot in warm restart case. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * | | include: configs: brppt1: Fix commit 0ea4fc4dcf90Bernhard Messerklinger2022-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr") destroys the boot targets b_t30lgcy#0 and b_t30lgcy#1. The reason behind this is, that b_t30lgcy#0 and b_t30lgcy#1 both load the for booting needed device trees from mmc and the cfgscr script patches those. Because of this, cfgscr is not allowed to destroy the previously loaded device tree otherwise cfgscr will fail. This patch moves the device trees invalidation on warm restart to the PREBOOT cmd to fix that issue. Fixes: 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr") Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * | | brppt1: Fix SPL boot stageBernhard Messerklinger2022-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs the am335x device tree with the latest linux kernel am335x device tree. That causes problems with device tree in SPL stage. To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the synced bus addresses correctly. A custom U-Boot device tree is also needed since the SPL build removes bus properties from bus nodes which are not explicitly marked with the u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of the in the SPL needed devices must be marked with u-boot,dm-pre-reloc. Also since there is no driver for "ti,sysc" compatible property in SPL the buses marked with this compatible string must also be marked with compatible = "simple-bus" to make the underlying devices visible in SPL. Otherwise the matching device drivers aren't found and the uclass drivers are dropped. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * | | brppt1: Remove unused board variantsBernhard Messerklinger2022-09-152-252/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI and NAND board variants never went into production. Drop those board variants. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * | | Merge tag 'efi-next-2022-09-14' of ↵WIP/14Sep2022-nextTom Rini2022-09-141-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi into next Pull request for efi next UEFI: Implement a command eficonfig to maintain Load Options and boot order via menus.
| | * | | test: unit test for eficonfigMasahisa Kojima2022-09-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a unit test for the eficonfig command. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * | | | mips: octeon_nic23: Add PCIe FLR fixup via cyclic infrastructureAaron Williams2022-09-131-0/+3
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a fixup function related to a PCIe FLR (Function Level Reset) problem on the NIC23 PCIe board. This function is imported from the Marvell Octeon 2013 U-Boot version as a (nearly) verbatim copy. It uses the newly introduced cyclic infrastructure, so that this function gets called every 100us, which is needed to detect this FLR issue. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | configs: aspeed: Enable CONFIG_SPI_DIRMAPChin-Ting Kuo2022-09-132-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_SPI_DIRMAP on ASPEED platforms. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
| * | | configs: aspeed: Enable SPI flash featuresChin-Ting Kuo2022-09-132-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable ASPEED SPI controller driver. - Enable SPI flash memory configurations. - Enable configurations for SPI flash manufacturers supported on both ASPEED AST2500 and AST2600 AVL. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
| * | | arm64: versal: Enable zynqmp_gqspi driverAshok Reddy Soma2022-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Versal supports gqspi ip, so enable zynqmp_gqspi driver for Versal platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-7-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
| * | | xilinx: versal: Disable LMB for mini configurationsMichal Simek2022-09-133-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There shouldn't be a reason to have LMB on for these configurations. LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs: zynqmp: Disable LMB for mini u-boot"). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/17d1e9b50b2fd032352911f94f4f213828e0a3f7.1662460892.git.michal.simek@amd.com
| * | | xilinx: Enable CMD_GREPENV/SETEXPR by defaultMichal Simek2022-09-134-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both of these commands in Xilinx SoCs to be able to use them in boot scripts. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
| * | | xilinx: Add env redund offsetT Karthik Reddy2022-09-133-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env variables is overwriting data at 0 offset, which is wrong. So add default redund env offset for Zynq, ZynqMP, Versal and microblaze platforms. Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE). In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000. Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of ENV_IS_IN_SPI_FLASH config. Below table specifies platform specific env and env redund offsets. PLAT ENV_OFFSET ENV_OFFSET_REDUND ---- ---------- ----------------- ZYNQ 0xE0000 0xE40000 ZYNQMP 0x1E00000 0x1E80000 VERSAL 0x7F40000 0x7F00000 MICROBLAZE 0x1080000 0x10C0000 Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
| * | | xilinx: zynq: Enable mkeficapsule tools compilationMichal Simek2022-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynq can use efi capsule infrastructure that's why enable it by default. For capsule generation for zynq you can use: pushd spl ../tools/mkeficapsule -g "1ba29a15-9969-40aa-b424-e86121618664" boot.bin \ --index 1 ../capsule1.bin popd ./tools/mkeficapsule -g "1a5178f0-87d3-4f36-ac63-3b31a23be305" u-boot.img \ --index 2 capsule2.bin Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a8194ecfa7932f2d8ada5ee508b2a026c782f15e.1660055571.git.michal.simek@amd.com
| * | | xilinx: versal: Define CONFIG_CQSPI_REF_CLKAshok Reddy Soma2022-09-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 55b3ba4c2ba4 ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig. The static value via Kconfig is a fallback option in case of clock framework is not enabled or fails for some reason. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
generated by cgit (git 2.34.1) at 2025-02-27 07:54:34 +0000