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* clk: sunxi: Extend DM_RESET selection to SPLSamuel Holland2021-10-251-0/+1
* clk: sifive: Fix -Wint-to-pointer-cast warningBin Meng2021-10-201-3/+3
* clk: fixed_rate: add dummy disable() functionWIP/2021-10-19-assorted-changesSamuel Holland2021-10-191-0/+1
* clk: rockchip: rk3568: update clksElaine Zhang2021-10-151-2/+9
* rockchip: px30: add support for setting cpll clockChris Morgan2021-10-151-0/+3
* Merge https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-10-1217-13/+235
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| * clk: sunxi: Add drivers for A31 and H6 PRCM CCUsSamuel Holland2021-10-114-0/+136
| * clk: sunxi: Add support for I2C gates/resetsSamuel Holland2021-10-1112-0/+86
| * clk: sunxi: Move header out of arch directorySamuel Holland2021-10-1113-13/+13
* | clk: ti: add am33xx/am43xx spread spectrum clock supportDario Binacchi2021-10-111-3/+128
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* clk: k210: Try harder to get the best configSean Anderson2021-10-071-0/+24
* k210: clk: Refactor out_of_spec testsSean Anderson2021-10-071-54/+53
* clk: k210: Fix checking if ulongs are less than 0Sean Anderson2021-10-071-4/+5
* Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodia...Tom Rini2021-09-301-1/+4
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| * clk: versal: Enable only GATE type clocksT Karthik Reddy2021-09-301-1/+4
* | WS cleanup: remove SPACE(s) followed by TABWIP/2021-09-30-whitespace-cleanupsWolfgang Denk2021-09-301-1/+1
* | WS cleanup: remove trailing empty linesWolfgang Denk2021-09-303-3/+0
* | Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/...WIP/27Sep2021-nextTom Rini2021-09-279-47/+49
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| * | clk: Rename clk_get_by_driver_info()Simon Glass2021-09-251-4/+3
| * | treewide: Try to avoid the preprocessor with OF_REALSimon Glass2021-09-256-32/+35
| * | treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass2021-09-256-7/+7
| * | treewide: Simply conditions with the new OF_REALSimon Glass2021-09-256-12/+12
* | | Merge tag 'v2021.10-rc5' into nextTom Rini2021-09-272-4/+13
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| * clk: ti: k3: Update driver to account for divider flagsSuman Anna2021-09-171-2/+2
| * clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach2021-09-171-2/+11
* | clk: at91: clk-master: split master clock in pres and dividerClaudiu Beznea2021-09-214-50/+144
* | mmc: Rename MMC_SUPPORT to MMCSimon Glass2021-09-041-3/+3
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* drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim2021-08-253-0/+221
* drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim2021-08-253-1/+708
* clk: clk_versaclock: Add support for versaclock driverAdam Ford2021-08-213-0/+1110
* clk: stm32mp1: add support of BSEC clockPatrick Delaunay2021-08-161-0/+1
* rockchip: px30: Support configure SFCJon Lin2021-08-121-0/+32
* clk: stm32mp1: add support of missing SPI clocksPatrick Delaunay2021-07-271-0/+13
* clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek2021-07-261-0/+1
* Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u...WIP/17Jul2021Tom Rini2021-07-171-1/+22
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| * clk: imx8mm: Add SPI clocksFrieder Schrempf2021-07-101-1/+22
* | Merge branch '2021-07-15-assorted-fixes'Tom Rini2021-07-161-1/+5
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| * | clk: Detect failure to set defaultsSimon Glass2021-07-151-1/+5
* | | clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay2021-07-161-0/+1
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* / clk: uniphier: Add PCIe clock entryKunihiko Hayashi2021-07-141-0/+3
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* clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek Behún2021-07-082-0/+2
* Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmWIP/07Jul2021Tom Rini2021-07-071-0/+2
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| * dm: define LOG_CATEGORY for all uclassPatrick Delaunay2021-07-061-0/+2
* | drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan2021-07-061-3/+3
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* Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u...WIP/01Jul2021-nextTom Rini2021-07-013-0/+198
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| * clk: zynq: Add clock wizard driverZhengxun2021-06-233-0/+198
* | Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh int...WIP/28Jun2021-nextTom Rini2021-06-287-0/+371
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| * | clk: renesas: Add R8A779A0 clock tablesHai Pham2021-06-247-0/+338
| * | clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2021-06-242-0/+33
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* | Merge tag 'v2021.07-rc5' into nextTom Rini2021-06-281-2/+6
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