aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/...WIP/27Sep2021-nextTom Rini2021-09-279-47/+49
|\
| * clk: Rename clk_get_by_driver_info()Simon Glass2021-09-251-4/+3
| * treewide: Try to avoid the preprocessor with OF_REALSimon Glass2021-09-256-32/+35
| * treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass2021-09-256-7/+7
| * treewide: Simply conditions with the new OF_REALSimon Glass2021-09-256-12/+12
* | Merge tag 'v2021.10-rc5' into nextTom Rini2021-09-272-4/+13
|\ \ | |/ |/|
| * clk: ti: k3: Update driver to account for divider flagsSuman Anna2021-09-171-2/+2
| * clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach2021-09-171-2/+11
* | clk: at91: clk-master: split master clock in pres and dividerClaudiu Beznea2021-09-214-50/+144
* | mmc: Rename MMC_SUPPORT to MMCSimon Glass2021-09-041-3/+3
|/
* drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim2021-08-253-0/+221
* drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim2021-08-253-1/+708
* clk: clk_versaclock: Add support for versaclock driverAdam Ford2021-08-213-0/+1110
* clk: stm32mp1: add support of BSEC clockPatrick Delaunay2021-08-161-0/+1
* rockchip: px30: Support configure SFCJon Lin2021-08-121-0/+32
* clk: stm32mp1: add support of missing SPI clocksPatrick Delaunay2021-07-271-0/+13
* clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek2021-07-261-0/+1
* Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u...WIP/17Jul2021Tom Rini2021-07-171-1/+22
|\
| * clk: imx8mm: Add SPI clocksFrieder Schrempf2021-07-101-1/+22
* | Merge branch '2021-07-15-assorted-fixes'Tom Rini2021-07-161-1/+5
|\ \
| * | clk: Detect failure to set defaultsSimon Glass2021-07-151-1/+5
* | | clk: stm32mp1: add support of SYSCFG clockPatrick Delaunay2021-07-161-0/+1
|/ /
* / clk: uniphier: Add PCIe clock entryKunihiko Hayashi2021-07-141-0/+3
|/
* clk: armada-37xx: Set DM_FLAG_PRE_RELOCMarek Behún2021-07-082-0/+2
* Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dmWIP/07Jul2021Tom Rini2021-07-071-0/+2
|\
| * dm: define LOG_CATEGORY for all uclassPatrick Delaunay2021-07-061-0/+2
* | drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan2021-07-061-3/+3
|/
* Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u...WIP/01Jul2021-nextTom Rini2021-07-013-0/+198
|\
| * clk: zynq: Add clock wizard driverZhengxun2021-06-233-0/+198
* | Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh int...WIP/28Jun2021-nextTom Rini2021-06-287-0/+371
|\ \
| * | clk: renesas: Add R8A779A0 clock tablesHai Pham2021-06-247-0/+338
| * | clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock codeMarek Vasut2021-06-242-0/+33
| |/
* | Merge tag 'v2021.07-rc5' into nextTom Rini2021-06-281-2/+6
|\|
| * clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3Giulio Benetti2021-06-091-0/+2
| * clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APBGiulio Benetti2021-06-091-2/+4
* | Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodi...WIP/19Jun2021-nextTom Rini2021-06-192-0/+2960
|\ \
| * | rockchip: rk3568: add clock driverElaine Zhang2021-06-182-0/+2960
* | | clk: cosmetic change in uclassPatrick Delaunay2021-06-181-1/+1
|/ /
* | clk: k210: Move k210 clock out of its own subdirectorySean Anderson2021-06-175-15/+14
* | clk: k210: Remove bypass driverSean Anderson2021-06-172-274/+1
* | clk: k210: Don't set PLL rates if we are already at the correct rateSean Anderson2021-06-171-7/+8
* | clk: k210: Re-add support for setting rateSean Anderson2021-06-171-5/+84
* | clk: k210: Implement soc_clk_dumpSean Anderson2021-06-171-2/+66
* | clk: k210: Move pll into the rest of the driverSean Anderson2021-06-173-594/+601
* | clk: k210: Rewrite to remove CCFSean Anderson2021-06-173-523/+439
* | clk: Allow force setting clock defaults before relocationSean Anderson2021-06-172-11/+18
* | clk: add support for TI K3 SoC clocksTero Kristo2021-06-113-0/+387
* | clk: add support for TI K3 SoC PLLTero Kristo2021-06-113-0/+296
* | clk: fix set_rate to clean up cached rates for the hierarchyTero Kristo2021-06-111-0/+19
* | clk: fix assigned-clocks to pass with deferring providerTero Kristo2021-06-111-0/+18
generated by cgit (git 2.34.1) at 2025-03-04 05:10:59 +0000