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* net: fec: Allow the PHY node to be retrievedFabio Estevam2020-06-222-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we move towards driver model, it is required to let the FEC driver know how to properly deal with an Ethernet PHY subnode in the device tree. For example: &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy@0 { reg = <0>; qca,clk-out-frequency = <125000000>; }; }; }; Currently the PHY node pointer is incorrectly associated with the Ethernel controller instead of the PHY node itself. This causes the PHY properties, such as "qca,clk-out-frequency" in the example above to not get parsed. Fix this problem by populating the phy_of_node node. Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Tom Rini <trini@konsulko.com>
* phy: atheros: ar8035: Fix clock output calculationFabio Estevam2020-06-221-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock ouput frequency is calculated incorrectly for AR8035 due to wrong masking of priv->clk_25m_reg and priv->clk_25m_mask. This same issue has been already fixed in the kernel by: commit b1f4c209d84057b6d40b939b6e4404854271d797 Author: Oleksij Rempel <o.rempel@pengutronix.de> Date: Wed Apr 1 11:57:32 2020 +0200 net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035 The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set for the values that comprise the fields, not zero-bits-set. This patch fixes the clock frequency configuration for ATH8030 and ATH8035 Atheros PHYs by removing the erroneous "~". To reproduce this bug, configure the PHY with the device tree binding "qca,clk-out-frequency" and remove the machine specific PHY fixups. Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> Apply the same fix in the U-Boot driver. Tested on a i.MX6 Hummingboard. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Tom Rini <trini@konsulko.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2020-06-083-11/+162
|\ | | | | | | | | | | | | - DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug fixes - Add TBI PHY access through MII - DDR: Rework errata workaround for A008109, A008378, 009942
| * net: tsec: Access TBI PHY through the corresponding MIIHou Zhiqiang2020-06-041-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: tsec: Access eTSEC registers using virtual addressHou Zhiqiang2020-06-041-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | The current code accesses eTSEC registers using physical address directly, it's not correct, though no problem on current platforms. It won't work on platforms, which does not support 1:1 virtual-physical address map. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * net: tsec: fsl_mdio: add DM MDIO supportMadalin Bucur2020-06-041-6/+134
| | | | | | | | | | | | | | Allow the MDIO devices to be probed based on the device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * drivers: net: e1000: with DM_ETH needs DM_PCI tooMadalin Bucur2020-06-031-0/+1
| | | | | | | | | | | | | | Compilation error occur when DM_ETH is enabled without DM_PCI. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | net: sun8i_emac: Add support for the H6 variantSamuel Holland2020-06-011-4/+10
| | | | | | | | | | | | | | | | The H6 EMAC is very similar to the H3 variant, except that it uses the same pinmux as R40. Add support for it. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | net: sun8i_emac: Use consistent clock bitfield definitionsSamuel Holland2020-06-011-3/+3
|/ | | | | | | | | | | | While the R40 uses a different register for EMAC clock configuration than other chips, the register has a very similar layout. Reuse the existing bitfield definitions in this file, since they match. This allows the driver to compile on the H6 platform, where the CCM_GMAC_CTRL definitions are not present. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* net: ks8851: Add Kconfig entriesMarek Vasut2020-05-221-0/+14
| | | | | | | | Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Add DM supportMarek Vasut2020-05-221-0/+103
| | | | | | | | Add support for U-Boot DM and DT probing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Receive one packet per recv callMarek Vasut2020-05-221-29/+36
| | | | | | | | | | | Instead of reading out the entire FIFO and possibly overwriting U-Boot memory, read out one packet per recv call, pass it to U-Boot network stack, and repeat. It is however necessary to cache RXFC value, because reading that one out clears it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Split non-DM specific bits from common codeMarek Vasut2020-05-221-16/+44
| | | | | | | | | Split network handling functions into non-DM specific parts and common code in preparation for conversion to DM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Pass around driver private dataMarek Vasut2020-05-221-124/+133
| | | | | | | | | | Introduce a private data structure for this driver with embedded struct eth_device and pass it around. This prepares the driver to work with both DM and non-DM systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Checkpatch cleanupMarek Vasut2020-05-221-9/+10
| | | | | | | | Fix various checkpatch complaints. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Clean up chip ID readoutMarek Vasut2020-05-221-19/+2
| | | | | | | | | | | There is only one chip ID in the table of chip IDs for this chip. Read out the chip ID instead and mask off the last "revision" bit to check the chip ID, this works for all chips in the family. Then drop the chip ID passing around. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Remove type_frame_headMarek Vasut2020-05-221-29/+7
| | | | | | | | | | The packet status and length information should be extracted from the FIFO per-packet. Adjust the code such that it reads the packet meta data and then the packet afterward, if applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Trim down struct ks_netMarek Vasut2020-05-221-61/+9
| | | | | | | | | Most of the entries in the structure are useless, remove them. Inline the rest of uses where applicable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Use 16bit RXQCR accessMarek Vasut2020-05-221-13/+4
| | | | | | | | | | Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors to it consistently and drop the ks_wrreg8() function altogether, as it is not used anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Remove RXQCR cacheMarek Vasut2020-05-221-9/+6
| | | | | | | | | The cached RXQCR value is never updated, remove the cache and just use the bits in the cache directly in the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* net: ks8851: Replace malloc()+memset() with calloc()Marek Vasut2020-05-221-6/+3
| | | | | | | | | | | Replace combination of malloc()+memset() with calloc() as the behavior is exactly the same and the amount of code is reduced. Moreover, remove printf() in the fail path, as it is useless, and return proper -ENOMEM return code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-05-202-5/+31
|\ | | | | | | | | | | | | - Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
| * net: fsl-mc: fixup DPC: add /board/ports node if missingRazvan Ionut Cirjan2020-05-191-3/+14
| | | | | | | | | | | | | | | | | | | | The DPC fixup for MAC address and enet_if is not made if /board/ports node is missing in DPC file. Add /board/ports or /ports nodes if them are missing. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Ioana Ciornei <Ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * drivers: net: fsl-mc: fixup msi-map propertyLaurentiu Tudor2020-05-191-1/+16
| | | | | | | | | | | | | | | | | | | | Similarly to iommu-map, the msi-map property must also be fixed up in the device tree, in order for the icid -> streamid translation be possible in the MSI case as well. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Diana Craciun <diana.craciun@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * driver: net: fm: minor fix in DM ETH supportMadalin Bucur2020-05-191-1/+1
| | | | | | | | | | | | | | | | Bus callback functions for read/write/reset need to be set only for DM_ETH, moving endif a bit lower. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | common: Drop linux/bitops.h from common headerSimon Glass2020-05-1845-0/+45
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/delay.h from common headerSimon Glass2020-05-1884-0/+84
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Fix some checkpatch warnings in calls to udelay()Simon Glass2020-05-184-30/+30
| | | | | | | | | | | | | | Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop linux/bug.h from common headerSimon Glass2020-05-188-0/+8
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop log.h from common headerSimon Glass2020-05-1877-1/+81
| | | | | | | | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | command: Remove the cmd_tbl_t typedefSimon Glass2020-05-188-28/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop image.h from common headerSimon Glass2020-05-187-0/+7
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop part.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* | common: Drop net.h from common headerSimon Glass2020-05-1832-0/+40
|/ | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOODTrevor Woerner2020-05-152-2/+2
| | | | | | | | Have this symbol follow the pattern of all other such symbols. This patch also removes a TODO from the code. Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* rename symbol: CONFIG_ORION5X -> CONFIG_ARCH_ORION5XTrevor Woerner2020-05-152-2/+2
| | | | | | | Have this symbol follow the pattern of all other such symbols. This patch removes a TODO from the code. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* net: bcmgenet: Don't set ID_MODE_DIS when not using RGMIINicolas Saenz Julienne2020-05-121-1/+4
| | | | | | | | | | | As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is RGMII. Don't enable it for the rest of setups. This has been seen to misconfigure RPi4's PHY when booting Linux. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* Merge tag 'ti-v2020.07-rc2' of ↵Tom Rini2020-05-111-0/+4
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix boot issues on Nokia RX-51 - Configure AM6 CPSW for 10Mbps in rgmii mode. - Minor changes for J721e
| * net: ethernet: ti: am65-cpsw-nuss: enable 10Mbps link speed in rgmii modeMurali Karicheri2020-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | In RGMII mode the 10Mbps link speed is supported only when CPSW2G MAC SL is configured for External Control ("in band") mode CPSW_PN_MAC_CONTROL_REG.CTL_EN(18) = 1 Hence update am65_cpsw_update_link() to follow documentation. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | eQos: Implement the read_rom_hwaddr callbackYe Li2020-05-101-0/+11
| | | | | | | | | | | | | | | | | | Implement the read_rom_hwaddr callback to load MAC address from fuse for imx8m platforms. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | fec: Move imx_get_mac_from_fuse declare to imx fileYe Li2020-05-101-2/+0
| | | | | | | | | | | | | | | | | | | | imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp, we have two different ENET controllers and both need to call this function. So decouple its declare from fec driver. Reviewed-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: eqos: implement callbaks to get interface and set txclk rateFugang Duan2020-05-101-3/+52
| | | | | | | | | | | | | | | | | | Implement the callbacks to get phy mode interface and txclk rate configuration. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: dwc_eth_qos: add dwc eqos for imx supportFugang Duan2020-05-101-14/+171
| | | | | | | | | | | | | | | | Add dwc eqos for imx support. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: phy: realtek: add rx delay support for RTL8211FFugang Duan2020-05-101-0/+11
| | | | | | | | | | | | | | | | Add RX delay enable support for RTL8211F PHY. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: Update eQos driver and FEC driver to use eth phy interfacesYe Li2020-05-102-16/+45
| | | | | | | | | | | | | | Update eQoS and fec ethernet drivers to support shared MDIO framework Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: Add eth phy generic driver for shared MDIOYe Li2020-05-103-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For dual ethernet controllers, the HW design may connect ETH phys to one MDIO ports. So two different ethernet drivers have to share MDIO bus. Since two ethernet drivers are independent, we can't ensure their probe order. To resolve this problem, introduce an eth phy generic driver and uclass. After eth-uclass binds, we search the mdio node and binds the phy node with the eth-phy-generic driver. When one eth driver get its phy device, the parent of phy device will probe prior than phy device. So this ensure the eth driver ownes the MDIO bus will be probed before using its MDIO. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | net: fec: add fuse checkPeng Fan2020-05-101-0/+14
|/ | | | | | | | Add fuse check for fec. If the fuse indicates the module will not work in the SoC, let's fail the initialization. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: consolidate {ar8031|ar8035}_config()Michael Walle2020-05-071-27/+3
| | | | | | | The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: ar8035: remove static clock configMichael Walle2020-05-071-13/+0
| | | | | | | | | | | | | | | We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* phy: atheros: add device tree bindings and configMichael Walle2020-05-071-2/+222
| | | | | | | | | | | | | | | | | Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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