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* drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass2024-10-114-16/+16
| | | | | | Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
* xpl: Rename spl_in_proper() to not_xpl()Simon Glass2024-10-111-1/+1
| | | | | | Give this function a slightly easier name. Signed-off-by: Simon Glass <sjg@chromium.org>
* xpl: Rename spl_phase() to xpl_phase()Simon Glass2024-10-111-1/+1
| | | | | | Rename this function to indicate that it refers to any xPL phase. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Avoid #ifdefs in RK3399 SPLSimon Glass2024-08-051-19/+21
| | | | | | | | | | | | The code here is confusing due to large blocks which are #ifdefed out. Add a function phase_sdram_init() which returns whether SDRAM init should happen in the current phase, using that as needed to control the code flow. This increases code size by about 500 bytes in SPL when the cache is on, since it must call the rather large rockchip_sdram_size() function. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Ensure memory size is available in RK3399 SPLSimon Glass2024-08-051-8/+14
| | | | | | | | | | | | At present gd->ram_size is 0 in SPL, meaning that it is not possible to enable the cache. Correct this by always populating the RAM size correctly. This increases code size by about 500 bytes in SPL, since it must call the rather large rockchip_sdram_size() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
* drivers: ram: Remove duplicate newlinesMarek Vasut2024-07-221-3/+0
| | | | | | Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"WIP/20May2024-nextTom Rini2024-05-2016-16/+14
| | | | | | | | As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini2024-05-1916-14/+16
| | | | | | | | | | | | When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
* ram: Remove <common.h> and add needed includesTom Rini2024-05-0716-16/+14
| | | | | | | Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: rk3308: Move cru and grf include files to arch-rockchipJonas Karlman2024-04-261-1/+1
| | | | | | | | Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used for all other Rockchip SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.hQuentin Schulz2024-03-138-8/+0
| | | | | | | | | | | | | The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
* rockchip: migrate hardware.h inclusion into appropriate filesQuentin Schulz2024-03-133-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | hardware.h is only defining macros which are "wrappers" around writel(). writel() is however not available in hardware.h, <asm/io.h> needs to be included. This means in order to use the wrappers in hardware.h, one also needs to include the <asm/io.h> header. However, this cannot be done currently because hardware.h is included in include/configs files, which are implicitly included by every code file by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds fail because ALIGN (the ARM assembly directive) got redefined by some of the include files coming from <asm.io.h>. Because nothing in the include/configs file actually use hardware.h, let's remove the inclusion of hardware.h from the include/configs files and explicitly add it wherever it is required. This prepares for the next commit where <asm/io.h> will be included in hardware.h. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
* ram: rockchip: Add rv1126 ddr4 supportTim Lunn2024-02-048-0/+533
| | | | | | | | | Add support for ddr4 on rv1126. Timing detection files are imported from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with define CONFIG_RAM_ROCKCHIP_DDR4. Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* common: Drop linux/printk.h from common headerWIP/23Sep2023Simon Glass2023-09-241-0/+1
| | | | | | | | | This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* core: remap: fix regmap_init_mem_plat() reg size handelingJohan Jonker2023-05-066-6/+6
| | | | | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so convert regmap_init_mem_plat() input to handel both. The syscon class driver also makes use of the regmap_init_mem_plat() function, but has no way of knowing the format of the device-specific platform data. In case of odd reg structures other then that the syscon class driver assumes the regmap must be filled in the individual syscon driver before pre-probe. Also fix the ARRAY_SIZE divider in the syscon class driver. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rk3399: add missing high row detectionJonathan Liu2023-04-211-0/+2
| | | | | | | | | | | | | | | | For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: Fix incorrect constant name in RAM init codeWIP/02Apr2023David Sebek2023-04-021-1/+1
| | | | | | | | A condition in the rk3399 RAM initialization code used the old CONFIG_RAM_RK3399_LPDDR4 constant name. This commit changes the condition to use the correct CONFIG_RAM_ROCKCHIP_LPDDR4 constant. Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: Add rk3588 ddr driver supportJagan Teki2023-02-282-0/+58
| | | | | | | | | Add ddr driver for rk3588 to get the ram capacity. Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* global: Finish CONFIG -> CFG migrationTom Rini2023-01-201-1/+1
| | | | | | | | | | | | | At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: Add rv1126 lpddr4 supportJagan Teki2023-01-168-0/+556
| | | | | | | Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: rv1126: Control ddr init prints via DEBUGJagan Teki2023-01-161-13/+25
| | | | | | | | | | | Control the ddr init print messages via RAM_ROCKCHIP_DEBUG instead of printing by default. This gives an option to configs to enable these prints or not. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Add rv1126 ddr driver supportJagan Teki2023-01-162-0/+3522
| | | | | | | | Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Add rv1126 ddr loader paramsJagan Teki2023-01-161-0/+197
| | | | | | | | Add DDR loader parameters for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Add rv1126 ddr3 supportJagan Teki2023-01-167-0/+504
| | | | | | | | Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Update ddr pctl regs for px30Jagan Teki2023-01-161-3/+3
| | | | | | | | Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Compute ddr capacity based on grf splitJagan Teki2023-01-164-5/+7
| | | | | | | | | | | | DDR chip capacity is computed based on GRF split in some Rockchip SoC's like PX30 and RV1126. Add split argument in ddr print info so-that the respective ddr driver will pass the grf split. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Add common ddr type configsJagan Teki2023-01-163-24/+21
| | | | | | | | | | | | We have common ddr types in rockchip or in general. So use the common ddr type names instead of per Rockchip SoC to avoid confusion. The respective ddr type names will use on the associated ddr SoC driver as these drivers are built per SoC at a time. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini2022-12-0512-62/+62
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: fix typo in KConfig option labelQuentin Schulz2022-10-191-1/+1
| | | | | | | | | RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo. Fixes: 2db36c64bd5a ("ram: rockchip: px30: add a config-based ddr selection") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Conduct memory training at 400MHzLee Jones2022-09-041-15/+21
| | | | | | | | | | | | | | | | | | Currently the default initialisation frequency is 50MHz. Although this does appear to be suitable for some LPDDR4 RAM chips, training at this low frequency has been seen to cause Column errors, leading to Capacity check errors on others. Here we force RAM initialisation to happen at 400MHz before ramping up to the final value running value of 800MHz after everything has been successfully configured. Link: https://lore.kernel.org/u-boot/Yo4v3jUeHXTovjOH@google.com/ Suggested-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Michal Suchánek <msuchanek@suse.de>
* ram: rk3399: Fix faulty frequency change reportsLee Jones2022-09-041-2/+2
| | | | | | | | | | | | | | Frequency changes to 400MHz are presently reported as: lpddr4_set_rate_0: change freq to 400000000 mhz 0, 1 This is obviously wrong by 6 orders of magnitude. Ensure frequency changes are reported accurately. Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Fix .set_rate_index() error handlingLee Jones2022-09-041-1/+3
| | | | | | | | | | Functions pointed to by this op pointer can return non-zero values indicating an error. Ensure any error value is propagated back up the call-chain. Signed-off-by: Lee Jones <lee@kernel.org> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* drivers: ram: rockchip: Fix dram channels calculation for rk3399Han Pengfei2022-09-041-2/+2
| | | | | | | | Only add the dram channel when we finally setup it successfully at the last step. Signed-off-by: Han Pengfei <pengphei@foxmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk3066: add sdram driverPaweł Jarosz2022-04-182-0/+893
| | | | | | | | Add rockchip rk3066 sdram driver Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: ram: sdram_rk3x88: replace comma by semicolonJohan Jonker2022-03-182-2/+2
| | | | | | | | | | | | A comma at the end of a line gives sometimes strange effects in combination with some code formatters, so replace a comma by a semicolon in the sdram_rk3188.c and sdram_rk3288.c files. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* WS cleanup: remove trailing empty linesWolfgang Denk2021-09-301-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* clk: Rename clk_get_by_driver_info()Simon Glass2021-09-251-1/+1
| | | | | | | | | | This is actually a misnomer now, since the phandle info may contain a driver_info index or a udevice index. Rename it to use the word 'phandle', which seems more accurate. Add a comment while we are here. Also add a test for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* treewide: Try to avoid the preprocessor with OF_REALSimon Glass2021-09-255-14/+18
| | | | | | | Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
* treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass2021-09-256-8/+8
| | | | | | | Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3568: Add sdram driverJoseph Chen2021-06-182-0/+57
| | | | | | | Add the driver for rk3568 u-boot to get sdram capacity. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-136-27/+22
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-136-12/+12
| | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-136-23/+23
| | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-136-6/+6
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-139-16/+16
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2020-10-302-0/+29
| | | | | | | | | | | | | | | The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang2020-07-221-0/+13
| | | | | | | | The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUGJagan Teki2020-07-221-4/+8
| | | | | | | | | | | | | | Right now all these debug statements are printing on the console to make sure proper dram initialization happens.   Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful and work like before since the RAM_ROCKCHIP_DEBUG is by default yet. No functionality changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Drop debug stride in driverJagan Teki2020-07-221-25/+0
| | | | | | | | | | stride debug is already present in sdram_common.c via RAM_ROCKCHIP_DEBUG. So, drop the redundant debug stride code in rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-02-25 17:41:56 +0000