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* Merge tag 'v2024.01-rc6' into nextTom Rini2024-01-031-1/+1
|\ | | | | | | Prepare v2024.01-rc6
| * spi: npcm_pspi: Fix the wrong clock divider calculationJim Liu2023-12-261-1/+1
| | | | | | | | | | | | Fix the wrong clock divider calculation. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
* | cache: add sifive private L2 cache driverZong Li2023-12-273-0/+52
| | | | | | | | | | | | | | | | This driver is currently responsible for enabling the clock gating feature of SiFive pre core's private L2 cache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | iommu: add qcom-hyp-smmuCaleb Connolly2023-12-213-0/+413
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a basic implementation of the ARM SMMU. This driver is intended for use on Qualcomm platforms where the SMMU has been configured by a previous bootloader, cannot be turned off, and doesn't support BYPASS streams. It keeps all existing stream mappings and only creates new ones for stream ids that aren't already configured. This driver is necessary to support peripherals that perform DMA which weren't configured by the previous stage bootloader (for example USB). It works by allocating a context bank using identity mapping (as U-Boot doesn't use virtual addresses). Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* | iommu: add a connect opCaleb Connolly2023-12-211-0/+11
| | | | | | | | | | | | | | | | Add an optional iommu callback to be invoked before a device probes. This can be used to configure the IOMMU in preparation for the device (e.g. by allocating a context bank) Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* | iommu: fix compilation when CONFIG_PCI disabledCaleb Connolly2023-12-211-2/+3
| | | | | | | | | | | | | | | | The dev_pci_iommu_enable() function is only available when CONFIG_PCI is enabled, replace the runtime check with a preprocessor one to fix compilation with pci disabled. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* | global: Remove duplicate common.h inclusionsTom Rini2023-12-213-3/+0
| | | | | | | | | | | | | | | | These files include <common.h> twice. Start by removing the second inclusion of the file. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | global: Drop common.h inclusionTom Rini2023-12-2116-19/+3
| | | | | | | | | | | | | | | | | | In order to make it easier to move on to dropping common.h from code directly, remove common.h inclusion from the rest of the header file which had been including it. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: Partial cleanup and audit usage of <config.h>Tom Rini2023-12-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | We need to include <config.h> directly when a file needs to have something such as CFG_SYS_SDRAM_SIZE referenced as this file is not automatically globally included and is most commonly indirectly included via common.h. Remove most cases of arm including config.h directly, but add it where needed. This includes a few board-specific fixes. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | global: Restrict use of '#include <linux/kconfig.h>'Tom Rini2023-12-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | In general terms, we -include include/linux/kconfig.h and so normal U-Boot code does not need to also #include it. However, for code which is shared with userspace we may need to add it so that either our full config is available or so that macros such as CONFIG_IS_ENABLED() can be evaluated. In this case make sure that we guard these includes with a test for USE_HOSTCC so that it clear as to why we're doing this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'u-boot-amlogic-next-20231220' of ↵WIP/20Dec2023-nextTom Rini2023-12-203-0/+146
|\ \ | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - Add support for new GXL MDIO mux, with driver and Linux DT sync from v6.4
| * | net: Add Amlogic GXL MDIO Mux driverNeil Armstrong2023-12-193-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port the mdio-mux-meson-gxl.c Linux driver introduced in [1], and adapt it to U-Boot. This driver is needed to boot U-Boot with Linux DT since v6.4, since it switched the MDIO mux from the mmio to a proper GXL driver. [1] 9a24e1ff4326 ("net: mdio: add amlogic gxl mdio mux support") Link: https://lore.kernel.org/r/20231213-u-boot-gxl-mdio-mux-v2-1-c56bb02a75ea@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | | drivers: pinctrl: tegra: incorporate existing codeSvyatoslav Ryhel2023-12-1912-0/+2783
| | | | | | | | | | | | | | | | | | | | | Move all existing pinmux and funcmux code into a dedicated folder in pinctrl to simplify further maintenance. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | drivers: pinctrl: create Tegra DM pinctrl driverSvyatoslav Ryhel2023-12-196-0/+453
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing pinctrl driver available for Tegra SOC is well designed, but it lacks DM support. Let's add a DM compatible overlay, which allows use of the device tree, along with preserving backward compatibility with all existing setups and the ability to use it in SPL board configuration stage. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | mmc: tegra: use max-frequency from device tree if providedPeter Geis2023-12-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver currently hard-codes the max freqency for the sdhci controllers. If the controller is unable to operate at the max frequency, the mmc card will not be available on the first scan. Subsequent scans will eventually find a working combination. Fix this by allowing the driver to check for the max-frequency property and default to the original value if it doesn't exist. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | drivers: gpio-uclass: support PMIC GPIO childrenSvyatoslav Ryhel2023-12-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UCLASS_PMIC may have GPIO children without exposed fdt node, in this case if requesting fails, check if uclass is PMIC. Restrict build for supported devices only to save those precious bytes on devices with no spare memory. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | drivers: gpio: implement PALMAS GPIO cellSvyatoslav Ryhel2023-12-194-1/+149
| | | | | | | | | | | | | | | | | | | | | Add gpio driver for TI Palmas series PMIC. This has 8 gpio which can work as input/output. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | drivers: gpio: implement MAX77663 GPIO cellSvyatoslav Ryhel2023-12-194-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | MAXIM Semiconductor's PMIC, MAX77663 has 8 GPIO pins and 3 GPIO-like pins. It also supports interrupts from these pins. Add GPIO driver for these pins to control via GPIO APIs. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
* | | Merge patch series "Add support for MediaTek MT8365 EVK Board"Tom Rini2023-12-192-0/+767
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Julien Masson <jmasson@baylibre.com> says: This patch series add the support for the MediaTek MT8365 EVK Board [1]. Most of the code have been copied/adapted from Linux tag v6.7-rc2. For now we only enable/test these features: Boot, UART, Watchdog and MMC. [trini: This includes two clocks not listed in the Linux binding, which needs resyncing later]
| * | | clk: mediatek: add clock driver support for MediaTek MT8365 SoCJulien Masson2023-12-192-0/+767
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock driver support for MediaTek MT8365 SoC. The changes are based on the Linux source code tag v6.7-rc2. clk-mt8365.c has been written based on these kernel files: - clk-mt8365.c (a96cbb146a9736f501fe66ebda6a9018735e5e8a) - clk-mt8365-apmixedsys.c (65c9ad77cbc0eed78db94d80041aba675cfbdfa9) And adapted following the clk attributes supported by U-Boot. Signed-off-by: Julien Masson <jmasson@baylibre.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
* | | | mmc: mediatek: set b_max according CONFIG_SYS_MMC_MAX_BLK_COUNTJulien Masson2023-12-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The block count limit on MMC based devices should be set according to CONFIG_SYS_MMC_MAX_BLK_COUNT instead of hardcoding value. Signed-off-by: Julien Masson <jmasson@baylibre.com>
* | | | gpio: dw: Drop unused headersMaksim Kiselev2023-12-191-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | Drop headers which are not used or needed in this file. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
* | | | tee: optee: don't enumerate services if there ain't anyEtienne Carriere2023-12-191-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change optee driver service enumeration to not enumerate (and allocate a zero sized shared memory buffer) when OP-TEE reports that there is no service to enumerate. This change fixes an existing issue that occurs when the such zero sized shared memory buffer allocated from malloc() has a physical address of offset 0 of a physical 4kB page. In such case, OP-TEE secure world refuses to register the zero-sized shared memory area and makes U-Boot optee service enumeration to fail. Fixes: 94ccfb78a4d6 ("drivers: tee: optee: discover OP-TEE services") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
* | | | tee: optee: don't fail on services enumeration failureEtienne Carriere2023-12-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change optee probe function to only warn when service enumeration sequence fails instead of reporting an optee driver probe failure. Indeed U-Boot can still use OP-TEE even if some OP-TEE services are not discovered. Fixes: 94ccfb78a4d6 ("drivers: tee: optee: discover OP-TEE services") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
* | | | remoteproc: k3-dsp: Avoid reloading of firmwareUdit Kumar2023-12-191-0/+11
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | DSP core is going into abnormal state when load callback is called after starting of DSP core. Reload of firmware needs core to be stopped first, followed by load. So avoid loading of firmware, when core is started. Signed-off-by: Udit Kumar <u-kumar1@ti.com>
* | | Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵WIP/18Dec2023-nextTom Rini2023-12-181-7/+9
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment
| * | | timer: starfive: Add Starfive timer supportKuan Lim Lee2023-12-181-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Changes for v2: - correct driver name, comment, variable Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | | | Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi ↵Tom Rini2023-12-1810-7/+209
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next - spi_nor_read_sfdp_dma_unsafe (Vaishnav) - w25q01/02 (Jim)
| * | | | spi: cadence-quadspi: Fix error message on stuck busy stateJan Kiszka2023-12-141-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since day 1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor-ids: add support for xtx XT55Q02GBruce Suen2023-12-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for XTX XT55Q02G(1.8V,2Gbit). Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spinand: add support for ESMT F50x1G41LBIgor Prusov2023-12-143-1/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptation of Linux commit d74c36480a67 This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parseVaishnav Achath2023-12-141-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor: add flash model w25q01/02 supportJim Liu2023-12-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add flash w25q01jv, w25q01jvfim and w25q02jv support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | spi: cadence_qspi: Select flash subnode at runtimeUdit Kumar2023-12-092-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor: Add MT25QU128AB paramsGodfrey Mwangi2023-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Micron MT25QU128AB flash. Signed-off-by: Godfrey Mwangi <godmwan@microsoft.com> [jagan: fix the commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor: Add MT25U01G part number for SPI NOR FlashJit Loon Lim2023-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> [jagan: fix the id position and commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flashTeik Heng Chong2023-12-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | | mtd: spi-nor: Add support for Silicon Kaiser sk25lp128Jonas Karlman2023-12-062-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Silicon Kaiser sk25lp128 SPI NOR flash found in Pine64 PinePhone Pro and PineTab2. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
| * | | | spi: bcm63xx-hsspi: Fix compiler warningWilliam Zhang2023-12-061-1/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When build for arm64 target, comipler reports the following warning: drivers/spi/bcm63xx_hsspi.c: In function ‘bcm63xx_hsspi_xfer_dummy_cs’: include/linux/kernel.h:184:17: warning: comparison of distinct pointer types lacks a cast 184 | (void) (&_min1 == &_min2); \ | ^~ drivers/spi/bcm63xx_hsspi.c:298:22: note: in expansion of macro ‘min’ 298 | size_t curr_step = min(step_size, data_bytes); This change fix this warning by casting the data_bytes to size_t. Fixes: 0e144ec38cbb ("spi: bcm63xx-hsspi: Add prepend mode support") Signed-off-by: William Zhang <william.zhang@broadcom.com>
* | | | Merge tag 'v2024.01-rc5' into nextTom Rini2023-12-1814-11/+377
|\ \ \ \ | |_|/ / |/| | / | | |/ | |/| Prepare v2024.01-rc5
| * | test: dm: clk_ccf: test ccf_clk_opsYang Xiwen2023-12-152-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assign ccf_clk_ops to .ops of clk_ccf driver so that it can act as an clk provider. Also add "#clock-cells=<1>" to its device tree node. Add "i2c_root" to clk_test in the device tree and driver for testing. Get "i2c_root" clock in CCF unit tests and add tests for it. Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231111-enable_count-v3-2-08a821892fa9@outlook.com
| * | clk: Check that composite clock's div has set_rate()Igor Prusov2023-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's possible for composite clocks to have a divider that does not implement set_rate() operation. For example, sandbox_clk_composite() registers composite clock with a divider that only has get_rate(). Currently clk_composite_set_rate() only checks thate rate_ops are present, so for sandbox it will cause NULL dereference during clk_set_rate(). This patch adds rate_ops->set_rate check tp clk_composite_set_rate(). Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com
| * | clk: get correct ops for clk_enable() and clk_disable()Yang Xiwen2023-12-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations are called on clocks. This fixes the incorrect enable_count issue as described in [1]. [1]: https://lore.kernel.org/all/SEZPR06MB695927A6DEEEF8489A06897396A7A@SEZPR06MB6959.apcprd06.prod.outlook.com/ Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231111-enable_count-v2-2-20e3728600b5@outlook.com
| * | clk: check parent_name in clk_register to avoid confusing log_error() outputYang Xiwen2023-12-151-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some gate clocks and fixed clocks without a parent, calling clk_register will print an useless error message indicating that parent is missing. Fix that by gaurding log_xxx() with an if-statement. Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Suggested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20230807-clk-fix-v2-1-0b688e21fb4e@outlook.com
| * | ddr: imx: Add 3600 MTps rate supportMarek Vasut2023-12-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps PLL setting, except the divider is not 9 but 8 . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps ratesMarek Vasut2023-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The new MX8M DDR tool 3.31 now generates a programming file which uses data rate 3734 instead of 3733 or 3732 . Handle another rounding option . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | drivers: misc: Kconfig: Fix SPL_FS_LOADER promptAlexander Gendin2023-12-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Both FS_LOADER and SPL_FS_LOADER have the same menu prompt. To avoid confusion, make prompt for SPL_FS_LOADER different. Signed-off-by: Alexander Gendin <agendin@matrox.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2023-12-094-0/+346
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - StarFive: Add StarFive watchdog driver - VisionFive2: Support device tree overlay for VisionFive2 board - Andes: Fix PLIC-SW setting - RISC-V: Fix NVMe support by implying NVME_PCI for QEMU - RISC-V: Fix binman for 64 bit format load address
| | * | watchdog: Add StarFive Watchdog driverChanho Park2023-12-053-0/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add to support StarFive watchdog driver. The driver is imported from linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support because there is no support of jh7100 SoC in u-boot yet. Howver, this patch has been kept the variant coding style because JH7100 can be added later and have a consistency with the linux driver. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| | * | clk: starfive: jh7110: Add watchdog clocksChanho Park2023-12-051-0/+9
| | |/ | | | | | | | | | | | | | | | | | | | | | Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit (git 2.34.1) at 2025-03-01 14:11:11 +0000