aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-usb ↵WIP/09Sep2024-nextTom Rini2024-09-098-12/+114
|\ | | | | | | into next
| * phy: test: Implement sandbox PHY .set_mode and DM testMarek Vasut2024-09-091-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement trivial extension to the sandbox PHY, which makes it pretend to support selecting USB Host mode and nothing else. Any other mode is rejected with -EINVAL. Any submode except for default submode 0 is rejected with -EOPNOTSUPP . The implementation behaves in this trivial way to permit easy unit testing using test which is also added in this commit. To run the test, use e.g. sandbox64_defconfig and run U-Boot as follows: $ ./u-boot -Tc 'ut dm phy_setup' Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| * phy: rcar: Split init and set_mode operationsMarek Vasut2024-09-091-5/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current init operation also sets the PHY into USB host mode. Split the mode configuration into set_mode callback instead and implement support for device and OTG modes as well. The OTG mode performs auto-detection and selects either host or device mode. In case the OTG mode is configured, submode field can be used to select full PHY (re)initialization or only mode auto-detection. The full (re)initialization is only necessary once, on start up. Since the OTG mode may enable IRQ generation in the PHY, disable that IRQ generation in the exit callback again. Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| * phy: Extend generic_setup_phy() with PHY mode and submodeMarek Vasut2024-09-096-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend generic_setup_phy() parameter list with PHY mode and submode and call generic_phy_set_mode() in generic_setup_phy(), so the generic PHY setup function can configure the PHY into correct mode before powering the PHY up. Update all call sites of generic_setup_phy() as well, all of which are USB host related, except for DM test which now behaves as a USB host test. Note that if the PHY driver does not implement the .set_mode callback, generic_phy_set_mode() call returns 0 and does not error out, so this should not break any existing systems. Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* | Merge branch 'qcom-next' of ↵Tom Rini2024-09-098-3/+330
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon into next Various improvements to Snapdragon support: * Bumped up the pagetable size to handle newer SoCs with much more RAM * Made memory map parsing more robust, fixing chainloading on SM8550/SM8650 * Populate fdt_addr_r with U-Boot's FDT by default, and set $loadaddr to prevent crashes with some commands which expect it * Added initial support for SC7280/QCM6490 and the new RB3 Gen 2 board * Add debug config fragments to enable debug UART on some SoCs. * Enable RPMh regulators on SM8550/SM8650 * Map the cmd-db memory explicitly since it may not be in the memory map CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/22255
| * iommu: qcom-smmu: add sc7280-smmu-500 compatibleCaleb Connolly2024-09-061-0/+1
| | | | | | | | | | | | | | | | This soc doesn't have the generic compatible. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| * clk/qcom: add initial clock driver for sc7280Caleb Connolly2024-09-064-0/+142
| | | | | | | | | | | | | | | | | | We don't actually need any clocks to get UFS up and running, resets are useful though. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| * regulator: qcom-rpmh-regulator: add support for PM8550 & related regulatorsNeil Armstrong2024-09-061-0/+136
| | | | | | | | | | | | | | | | Add the PM8550 & related regulators found on the SM8550 and SM8650 platforms. The tables are imported from the Linux driver. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
| * soc: qcom: rpmh-rsc: add back __tcs_set_trigger() for SM8550/SM8650Neil Armstrong2024-09-061-0/+43
| | | | | | | | | | | | | | | | | | | | The TCS writes has no effect after the removal of the __tcs_set_trigger() call, obviously it seems the RSC version 3 requires it to complete the transactions. Fixes: 80c5be164ad ("soc: qcom: rpmh-rsc: drop unused multi-threading and non-active TCS support") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # sm8250 rb5 Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
| * soc: qcom: cmd-db: map cmd-db regionCaleb Connolly2024-09-061-2/+7
| | | | | | | | | | | | | | | | On at least SM8650 this region might not be included in the memory map. Use the new mmu_map_region() helper to map it during bind(). Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| * soc: qcom: cmd-db: use strncmp() instead of memcmp()Caleb Connolly2024-09-061-1/+1
| | | | | | | | | | | | | | | | memcmp() can cause aborts on some platforms and generally seems to be the wrong approach here. Use strncmp() instead which is more correct. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* | regulator: fixed: fix regulator-fixed-clockWIP/05Sep2024-nextJohn Keeping2024-09-051-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For regulator-fixed-clock, the device's private data is never set so in fixed_clock_regulator_set_enable() is null and the function cannot complete successfully. Rename the _plat structure to _priv to better represent its role and set this as the private data. As shown by the set_enable() function and by using the same .of_to_plat hook as regulator-fixed, the platform data is regulator_common_plat so also set .plat_auto correctly. Finally, set up the private data by adding a .probe function to look up the clock and set the member variable. Fixes: f3b5100aff3 ("regulator: fixed: add possibility to enable by clock") Signed-off-by: John Keeping <jkeeping@inmusicbrands.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | power: regulator: tps6287x: Add driver for TPS6287x step down convertorsKeerthy2024-09-053-0/+191
|/ | | | | | | | Add driver for TPS6287x step down convertors Data sheet: https://www.ti.com/lit/ds/slvsgc5a/slvsgc5a.pdf Signed-off-by: Keerthy <j-keerthy@ti.com>
* mmc: consider cd-gpios in Synopsys DesignWare driverHeinrich Schuchardt2024-09-051-0/+9
| | | | | | | | | | | The JH7110 SoC uses a GPIO for card detect. * In the of_to_plat function check if a cd-gpios definition exists and request the GPIO. * In the getcd function return the GPIO value in this case. Reported-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* mmc: msm_sdhci: program core_vendor_specCaleb Connolly2024-09-051-0/+11
| | | | | | | | | | After resetting the host controller, program in the POR val for this register just like the Linux driver does. This seems to help with initialization when running U-Boot as the primary bootloader on some boards. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* mmc: Change the frequency to MMC_HS_52 when selecting hs400Venkatesh Yadav Abbarapu2024-09-051-3/+3
| | | | | | | | | | | | | | Per JESD84-B51 P47, host need to change frequency to <=52MHz after setting HS_TIMING to 0x1, and host need to set the 8-bit DDR buswidth. Currently setting the frequency to 26MHz and trying to switch 8-bit DDR buswidth resulting timeouts. mmc dev 1 0 Select HS400 failed -110 switch to partitions #0, OK mmc1(part 0) is current device Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
* mmc: sdhci-cadence: Add support for Cadence sdmmc v6Kuan Lim Lee2024-09-054-51/+375
| | | | | | | | | | Cadence SDMMC v6 controller has a lot of changes on initialize compared to v4 controller. PHY is needed by v6 controller. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Co-developed-by: Alex Soo <yuklin.soo@starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* Merge patch series "provide names for emmc hardware partitions"Tom Rini2024-09-051-0/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tim Harvey <tharvey@gateworks.com> says: Modern eMMC v4+ devices have multiple hardware partitions per the JEDEC specification described as: Boot Area Partition 1 Boot Area Partition 2 RPMB Partition General Purpose Partition 1 General Purpose Partition 2 General Purpose Partition 3 General Purpose Partition 4 User Data Area These are referenced by fields in the PARTITION_CONFIG register (Extended CSD Register 179) which is defined as: bit 7: reserved bit 6: BOOT_ACK 0x0: No boot acknowledge sent (default 0x1: Boot acknowledge sent during boot operation Bit bit 5:3: BOOT_PARTITION_ENABLE 0x0: Device not boot enabled (default) 0x1: Boot Area partition 1 enabled for boot 0x2: Boot Area partition 2 enabled for boot 0x3-0x6: Reserved 0x7: User area enabled for boot bit 2:0 PARTITION_ACCESS 0x0: No access to boot partition (default) 0x1: Boot Area partition 1 0x2: Boot Area partition 2 0x3: Replay Protected Memory Block (RPMB) 0x4: Access to General Purpose partition 1 0x5: Access to General Purpose partition 2 0x6: Access to General Purpose partition 3 0x7: Access to General Purpose partition 4 Note that setting PARTITION_ACCESS to 0x0 results in selecting the User Data Area partition. You can see above that the two fields BOOT_PARTITION_ENABLE and PARTITION_ACCESS do not use the same enumerated values. U-Boot uses a set of macros to access fields of the PARTITION_CONFIG register: EXT_CSD_BOOT_ACK_ENABLE (1 << 6) EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) EXT_CSD_BOOT_ACK(x) (x << 6) EXT_CSD_BOOT_PART_NUM(x) (x << 3) EXT_CSD_PARTITION_ACCESS(x) (x << 0) EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1) EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7) EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7) There are various places in U-Boot where the BOOT_PARTITION_ENABLE field is accessed via EXT_CSD_EXTRACT_PARTITION_ACCESS and converted to a hardware partition consistent with the definition of the PARTITION_ACCESS field used by the various mmc_switch incarnations. To add some sanity to the distinction between BOOT_PARTITION_ENABLE (used to specify the active device on power-cycle) and PARTITION_ACCESS (used to switch between hardware partitions) create two enumerated types and use them wherever struct mmc * part_config is used or the above macros are used. Additionally provide arrays of the field names and allow those to be used in the 'mmc partconf' command and in board support files. The first patch adds enumerated types and makes use of them which represents no compiled code change. The 2nd patch adds the array of names and uses them in the 'mmc partconf' command. The 3rd patch uses the array of hardware partition names in a board support file to show what emmc hardware partition U-Boot is being loaded from.
| * mmc: allow use of hardware partition names for mmc partconfTim Harvey2024-09-051-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eMMC v4+ devices have hardware partitions that are accessed via the PARTITION_CONFIG (Extended CSD Register 179) PARTITION_ACCESS and BOOT_PARTITION_ENABLE fields defined as: bit 5:3: BOOT_PARTITION_ENABLE   0x0: Device not boot enabled (default)   0x1: Boot Area partition 1 enabled for boot   0x2: Boot Area partition 2 enabled for boot   0x3-0x6: Reserved   0x7: User area enabled for boot bit 2:0 PARTITION_ACCESS 0x0: No access to boot partition (default) 0x1: Boot Area partition 1 0x2: Boot Area partition 2 0x3: Replay Protected Memory Block (RPMB) 0x4: Access to General Purpose partition 1 0x5: Access to General Purpose partition 2 0x6: Access to General Purpose partition 3 0x7: Access to General Purpose partition 4 Add char arrays to provide names for these values. Use these names which displaying or setting the PARTITION_CONFIG register via the 'mmc partconf' command. Before: u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2 EXT_CSD[179], PARTITION_CONFIG: BOOT_ACK: 0x1 BOOT_PARTITION_ENABLE: 0x2 PARTITION_ACCESS: 0x0 After: u-boot=> mmc partconf 2 1 1 0 && mmc partconf 2 EXT_CSD[179], PARTITION_CONFIG: BOOT_ACK: 0x1 BOOT_PARTITION_ENABLE: 0x1 (boot0) PARTITION_ACCESS: 0x0 (user) u-boot=> mmc partconf 2 1 boot1 0 && mmc partconf 2 EXT_CSD[179], PARTITION_CONFIG: BOOT_ACK: 0x1 BOOT_PARTITION_ENABLE: 0x2 (boot1) PARTITION_ACCESS: 0x0 (user) Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | Merge patch series "Make LMB memory map global and persistent"Tom Rini2024-09-032-34/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sughosh Ganu <sughosh.ganu@linaro.org> says: This is a follow-up from an earlier RFC series [1] for making the LMB and EFI memory allocations work together. This is a non-rfc version with only the LMB part of the patches, for making the LMB memory map global and persistent. This is part one of a set of patches which aim to have the LMB and EFI memory allocations work together. This requires making the LMB memory map global and persistent, instead of having local, caller specific maps. This is being done keeping in mind the usage of LMB memory by platforms where the same memory region can be used to load multiple different images. What is not allowed is to overwrite memory that has been allocated by the other module, currently the EFI memory module. This is being achieved by introducing a new flag, LMB_NOOVERWRITE, which represents memory which cannot be re-requested once allocated. The data structures (alloced lists) required for maintaining the LMB map are initialised during board init. The LMB module is enabled by default for the main U-Boot image, while it needs to be enabled for SPL. This version also uses a stack implementation, as suggested by Simon Glass to temporarily store the lmb structure instance which is used during normal operation when running lmb tests. This does away with the need to run the lmb tests separately. The tests have been tweaked where needed because of these changes. The second part of the patches, to be sent subsequently, would work on having the EFI allocations work with the LMB API's. [1] - https://lore.kernel.org/u-boot/20240704073544.670249-1-sughosh.ganu@linaro.org/T/#t Notes: 1) These patches are on next, as the alist patches have been applied to that branch. 2) I have tested the boot on the ST DK2 board, but it would be good to get a T-b/R-b from the ST maintainers. 3) It will be good to test these changes on a PowerPC platform (ideally an 85xx, as I do not have one).
| * | sandbox: iommu: remove lmb allocation in the driverSughosh Ganu2024-09-031-19/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandbox iommu driver uses the LMB module to allocate a particular range of memory for the device virtual address(DVA). This used to work earlier since the LMB memory map was caller specific and not global. But with the change to make the LMB allocations global and persistent, adding this memory range has other side effects. On the other hand, the sandbox iommu test expects to see this particular value of the DVA. Use the DVA address directly, instead of mapping it in the LMB memory map, and then have it allocated. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | lmb: make LMB memory map persistent and globalSughosh Ganu2024-09-032-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current LMB API's for allocating and reserving memory use a per-caller based memory view. Memory allocated by a caller can then be overwritten by another caller. Make these allocations and reservations persistent using the alloced list data structure. Two alloced lists are declared -- one for the available(free) memory, and one for the used memory. Once full, the list can then be extended at runtime. [sjg: Use a stack to store pointer of lmb struct when running lmb tests] Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Signed-off-by: Simon Glass <sjg@chromium.org> [sjg: Optimise the logic to add a region in lmb_add_region_flags()]
* | | Merge patch series "net: dwc_eth_qos: Add glue driver for Intel MAC"Tom Rini2024-09-0311-9/+626
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Philip Oberfichtner <pro@denx.de> says: This patch series implements the dwc_eth_qos glue driver for Intel SOCs. Before doing that, a few general adaptions to the dwc_eth_qos.c main driver are required. Most notably, the preparation for PCI based driver instances, which do not necessarily use a device tree.
| * | | net: dwc_eth_qos: Add glue driver for Intel MACPhilip Oberfichtner2024-09-036-0/+527
| | | | | | | | | | | | | | | | | | | | | | | | Add dwc_eth_qos glue driver for the Intel Elkhart-Lake SOC. Signed-off-by: Philip Oberfichtner <pro@denx.de>
| * | | net: dwc_eth_qos: Implement bind() for PCI devicesPhilip Oberfichtner2024-09-031-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI devices do not necessarily use a device tree. Implement a bind() function to assign unique device names in that case. Signed-off-by: Philip Oberfichtner <pro@denx.de>
| * | | net: dwc_eth_qos: Adapt probe() for PCI devicesPhilip Oberfichtner2024-09-037-8/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI devices do not necessarily use a device tree. In that case, the driver currently fails to find eqos->config and eqos->regs. This commit factors out the respective functionality. Device tree usage remains default, but board specific implementations will be possible as well. Signed-off-by: Philip Oberfichtner <pro@denx.de>
| * | | net: dwc_eth_qos: Fix header to be self-containedPhilip Oberfichtner2024-09-031-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, usage of this header relied on a specific include order. Fix it by including all dependencies. Signed-off-by: Philip Oberfichtner <pro@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* | | | Merge tag 'u-boot-imx-next-20240902' of ↵WIP/02Sep2024-nextTom Rini2024-09-023-2/+89
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22211 - Enable SPI NOR flash support and MTD partitions for phycore_imx8mp. - Convert mx6slevk to OF_UPSTREAM and watchdog DM. - Cleanup some mx5/mx6 USB options. - Make PLL settings configurable at board level. - Set CONFIG_SPL_LOAD_FIT_ADDRESS for verdin-imx8m/p. - Make the mxc-gpio reading state of GPIO pins in output mode to be consistent with the Linux kernel. - Add HUK derivation support for ELE AHAB.
| * | | | usb: ehci-mx5: Add a default for CFG_MXC_USB_PORTSCFabio Estevam2024-08-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like drivers/usb/host/ehci-mx6.c, add a default for drivers/usb/host/ehci-mx5.c. The motivation for doing this is to remove CFG_MXC_USB_PORTSC from board config files. All the mx5 boards, with the exeption of mx51evk, define CFG_MXC_USB_PORTSC as: #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) So move this definition as a default into ehci-mx5.c. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | | | gpio: mxc_gpio: fix reading state of GPIO pins in output modeTomas Paukrt2024-08-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSR register works correctly for GPIO pins in input mode, but always returns 0 for GPIO pins in output mode unless the SION bit is set. The DR register should be used for GPIO pins in output mode to allow correct getting of previously set output value. Please note that the Linux gpio-mxc driver and the NXP U-Boot mxc_gpio driver already use the DR register for all GPIO pins in output mode: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=442b2494b17d1a4f0a14721580271eb23ebffd42 https://github.com/nxp-imx/uboot-imx/commit/4afc3f90943c6b117f79b66d2cd04e64f437b0c2 Signed-off-by: Tomas Paukrt <tomaspaukrt@email.cz> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Fabio Estevam <festevam@gmail.com>
| * | | | imx: ele_ahab: Add HUK derivation supportMathieu Othacehe2024-08-301-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new ahab_derive command that derives the hardware unique key (HUK) into a 16 or 32 bytes key and stores it at the given address. Signed-off-by: Mathieu Othacehe <othacehe@gnu.org> Reviewed-by: Ye Li <ye.li@nxp.com>
* | | | | Merge tag 'u-boot-amlogic-next-20240902' of ↵Tom Rini2024-09-022-27/+60
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - meson_nand: R/W support for pages used by boot ROM
| * | | | | mtd: rawnand: meson: read/write access for boot ROM pagesArseniy Krasnov2024-08-281-10/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM on Meson needs some pages to be read/written in a special mode: 384 byte ECC mode (so called "short" by Amlogic) and with scrambling enabled. Such pages are located on the chip in the following way (for example): [ p0 ][ p1 ][ p2 ][ p3 ][ p4 ][ p5 ][ p6 ][ p7 ] ... [ pN ] ^ ^ ^ ^ pX is page number "X". "^" means "special" page used by boot ROM - e.g. every 2nd page in the range of [0, 7]. Step (2 here) and last page in range is read from the device tree. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/r/20240826131710.29746-4-avkrasnov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * | | | | mtd: rawnand: meson: refactor use of 'meson_nfc_cmd_access()'Arseniy Krasnov2024-08-281-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move call 'meson_nfc_cmd_seed()' and check for 'NAND_NEED_SCRAMBLING' to 'meson_nfc_cmd_access()', thus removing code duplication. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/r/20240826131710.29746-3-avkrasnov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * | | | | mtd: rawnand: nand_base: support for 'NAND_IS_BOOT_MEDIUM' flagArseniy Krasnov2024-08-281-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Linux kernel: commit f922bd798bb9 ("mtd: rawnand: add an option to specify NAND chip as a boot device") Allow to define a NAND chip as a boot device. This can be helpful for the selection of the ECC algorithm and strength in case the boot ROM supports only a subset of controller provided options. Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/r/20240826131710.29746-2-avkrasnov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | | | | | Merge tag 'v2024.10-rc4' into nextTom Rini2024-09-021-4/+2
|\| | | | | | | | | | | | | | | | | | | | | | | Prepare v2024.10-rc4
| * | | | | usb: gadget: ux500: Do not redefine ops if CONFIG_USB_MUSB_HOST setMarek Vasut2024-08-221-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case CONFIG_USB_MUSB_HOST is set, the ux500_gadget_ops get overridden to musb_usb_ops . Simply set the ops one way or the other depending on whether CONFIG_USB_MUSB_HOST is set or not. Fixes: ac4bf5d48a9e ("usb: gadget: ux500: Convert interrupt handling to usb_gadget_generic_ops") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20240818200425.89045-1-marek.vasut+renesas@mailbox.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
* | | | | | Merge patch series "Add support for Ethernet Boot on SK-AM62"WIP/30Aug2024-nextTom Rini2024-08-304-4/+38
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chintan Vankar <c-vankar@ti.com> says: This series enables Ethernet Boot on SK-AM62 device. This series is based on commit 'f4f845b85926' of origin/next branch of U-Boot. Logs for Ethernet Boot for AM625-SK: https://gist.github.com/chintanv133/464782796a9a60b9f5a49e674c5fc31a
| * | | | | | dma: ti: k3-udma: Add support for native configuration of chan/flowKishon Vijay Abraham I2024-08-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Existing UDMA driver performed the above mentioned configuration for UDMA. Add similar configuration for PKTDMA here. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
| * | | | | | soc: ti: k3-navss-ringacc: Fix reconfiguration of qmode APIChintan Vankar2024-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function "k3_ringacc_ring_reconfig_qmode_raw()" should reset qmode to requested value and should not update other fields in ring configuration register. Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | | | | | soc: ti: k3-navss-ringacc: Fix reset ring APIVignesh Raghavendra2024-08-301-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expectation of k3_ringacc_ring_reset_raw() is to reset the ring to requested size and not to 0. Fix this. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
| * | | | | | soc: ti: k3-navss-ringacc: Initialize base address of ring cfg registersKishon Vijay Abraham I2024-08-301-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize base address of ring config registers required to natively setup ring cfg registers in the absence of Device Manager (DM) services at R5 SPL stage. Since register property is defined as "ring" for PKTDMA and "cfg" for UDMA, configure base address of ring configuration register accordingly. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
| * | | | | | firmware: ti_sci: Add No-OP for "RX_FL_CFG"Kishon Vijay Abraham I2024-08-301-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX_FL_CFG message should not be forwarded to TIFS and should be handled within R5 SPL (when DM services are not available). Add a no-op function to not handle RX_FL_CFG messages. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
* | | | | | | list: use list_count_nodes() to count list entriesSughosh Ganu2024-08-301-5/+3
| |_|/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the API function list_count_nodes() to count the number of list entries. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | | gpio: Add G7 Aspeed gpio controller driverBilly Tsai2024-08-273-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the 7th generation of the SoC from Aspeed, the control logic of the GPIO controller has been updated to support per-pin control. Each pin now has its own 32-bit register, allowing for individual control of the pin’s value, direction, interrupt type, and other settings. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
* | | | | | dm: core: Make SPL_DM_SEQ_ALIAS select SPL_STRTOGaskell, Oliver2024-08-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling CONFIG_DM_SEQ_ALIAS enables code which relies on `trailing_strtol()` - which is only linked in SPL when CONFIG_SPL_STRTO is enabled. CONFIG_SPL_STRTO is not enabled by default - to ensure this function is available in SPL, CONFIG_SPL_DM_SEQ_ALIAS should select CONFIG_SPL_STRTO. Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | | | Merge patch series "dm: core: Avoid multiple calls to fdt_parent_offset()"Tom Rini2024-08-273-13/+30
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jonas Karlman <jonas@kwiboo.se> says: Use of fdt_parent_offset() is very expensive as detailed by the function documentation: NOTE: This function is expensive, as it must scan the device tree structure from the start to nodeoffset, *twice*. This series remove multiple calls to fdt_parent_offset() or ofnode_get_parent() when instead a single call can be made and the returned value can be reused. This series help reduce boot time by around: - ~137ms on a Radxa ROCK Pi 4 (RK3399) - ~33ms on a Radxa ZERO 3W (RK3566)
| * | | | | | dm: core: regmap: Avoid multiple calls to ofnode_get_parent()Jonas Karlman2024-08-271-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until a live tree is used in U-Boot proper after relocation, use of ofnode_get_parent() will trigger a call to the very expensive fdt_parent_offset(), as detailed by the function documentation: NOTE: This function is expensive, as it must scan the device tree structure from the start to nodeoffset, *twice*. Re-use the returned value from a single call instead of having to make multiple calls for same node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | | | dm: core: ofnode: Avoid multiple calls to ofnode_get_parent()Jonas Karlman2024-08-271-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until a live tree is used in U-Boot proper after relocation, use of ofnode_get_parent() will trigger a call to the very expensive fdt_parent_offset() as detailed by the function documentation: NOTE: This function is expensive, as it must scan the device tree structure from the start to nodeoffset, *twice*. Re-use the returned value from a single call instead of having to make multiple calls for same node. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | | | dm: core: fdtaddr: Avoid multiple calls to fdt_parent_offset()Jonas Karlman2024-08-271-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use of fdt_parent_offset() is very expensive as detailed by the function documentation: NOTE: This function is expensive, as it must scan the device tree structure from the start to nodeoffset, *twice*. Re-use the returned value from a single call instead of having to make multiple calls for same nodeoffset. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2025-03-04 06:32:42 +0000