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* arm64: dts: ti: k3-j7200: Fix OSPI bootUdit Kumar2024-11-221-0/+1
| | | | | | | | OSPI boot is broken due to missing bootph property in pin mux of OSPI. So add bootph to fix OSPI boot. Signed-off-by: Udit Kumar <u-kumar1@ti.com>
* Merge tag 'u-boot-rockchip-20241111' of ↵Tom Rini2024-11-113-6/+946
|\ | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/23280 - Add board: rk3328: FriendlyElec NanoPi R2S Plus rk3568: Qnap TS433 rk3588: Cool Pi CM5 GenBook - Move rk3399_force_power_on_reset to TPL for puma board;
| * arm64: dts: rockchip: Add DTS for FriendlyARM NanoPi R2S PlusSergey Bostandzhyan2024-11-111-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R2S Plus is basically an R2S with additional eMMC. The eMMC configuration for the DTS has been extracted and copied from rk3328-nanopi-r2.dts, v2017.09 branch from the friendlyarm/uboot-rockchip repository. Signed-off-by: Sergey Bostandzhyan <jin@mediatomb.cc> Link: https://lore.kernel.org/r/20240814170048.23816-2-jin@mediatomb.cc Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: b8c02878292200ebb5b4a8cfc9dbf227327908bd ] (cherry picked from commit c9bf98827964441f4dd16faa45bd4046f472e693) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Add support for rk3588 based Cool Pi CM5 GenBookAndy Yan2024-11-111-0/+349
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cool Pi CM5 GenBook works as a carrier board connect with CM5 [0]. Specification: - Rockchip RK3588 - LPDDR5X 8/32 GB - eMMC 64 GB - HDMI Type A out x 1 - USB 3.0 Host x 1 - USB-C 3.0 with DisplayPort AltMode - PCIE M.2 E Key for RTL8852BE Wireless connection - PCIE M.2 M Key for NVME connection - eDP panel with 1920x1080 This patch add basic support to bringup eMMC/USB HOST/WiFi/TouchPad/ Battery/PCIE NVME, and can also drive a HDMI output with out of tree hdmi patches. [0] https://www.crowdsupply.com/shenzhen-tianmao-technology-co-ltd/genbook-rk3588 Signed-off-by: Andy Yan <andyshrk@163.com> Link: https://lore.kernel.org/r/20240730102433.540260-3-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 4a8c1161b843c366776fc872a6fe45b743b2983e ] (cherry picked from commit dc6316da23734d9321e09f8c8a7669f4b4cb9f75) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add product-data eeproms to QNAP TS433Heiko Stuebner2024-11-081-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device contains two i2c-connected eeproms holding some product- specific values. One sitting on the mainboard and one on the statically connected backplane. While the eeprom chips themself have a size of 512 byte, the eeprom data only uses 256 byte each, probably to stay compatible with other models. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240810211438.286441-3-heiko@sntech.de [ upstream commit: da6f4130234448122fe3e66c8116f7d9eea8a5c7 ] (cherry picked from commit 0b3109708caf5002ba188ae28eae9ce46b2c39b4) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: actually enable pmu-io-domains on qnap-ts433Heiko Stuebner2024-11-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to the vendor-kernel the pmu-io-domains are not enabled by default. This resulted in the value not being set according to the regulator, which in turn made the gmac0 interface that is connected to the vccio4 supply inoperable. Fixes: 64b7f16fb394 ("arm64: dts: rockchip: add 2 pmu_io_domain supplies for Qnap-TS433") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240805162052.3345768-1-heiko@sntech.de [ upstream commit: 40cc4257169712f0ae3835820a4c5afbdd1a16ff ] (cherry picked from commit f509fcb1fb82117e551b489592ac5714a6c5cd8d) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Simplify network PHY connection on qnap-ts433Uwe Kleine-König2024-11-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While it requires to have the right phy driver loaded (i.e. motorcomm) to make the phy asserting the right delays, this is generally the preferred way to define the MAC <-> PHY connection. Signed-off-by: Uwe Kleine-König <ukleinek@debian.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20240304084612.711678-2-ukleinek@debian.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: e8d45544f806f3b55c30345de84262cbb9504902 ] (cherry picked from commit e0bbe061fd537bd7b113c53eb046bbcbf0e6597d) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add 2 pmu_io_domain supplies for Qnap-TS433Heiko Stuebner2024-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the two supplies for the pmu-io-domains that are defined in the vendor devicetree for the TS433. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-15-heiko@sntech.de [ upstream commit: 64b7f16fb3947e5d08d9e9b860ce966250e45d52 ] (cherry picked from commit 9b4d4c02b5762196063ab03c5439f96cbbaf2485) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable gpu on Qnap-TS433Heiko Stuebner2024-11-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TS433 doesn't provide display output, but the gpu nevertheless can be used for compute tasks for example. So there is no reason not to enable it. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-14-heiko@sntech.de [ upstream commit: 9130eb62586f4cef0557d0378fb7e78d7397ab2d ] (cherry picked from commit e324a9e8ea083ebdca207b5ca2ed86d2b5f862a0) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add missing pmic information on Qnap-TS433Heiko Stuebner2024-11-081-1/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fill in the missing pieces for RK809 pmic used on the TS433. The regulator setup comes from the vendor-devicetree, so without proper schematics its accuracy is somewhat unclear, but it looks really similar to all the other rk3568 boards, so follows the reference design it seems. The one caveat is related to vcc3v3_sd. This regulator needs to stay on. When turned off because of no users, access to both PCIe controllers will stall. Maybe this rail does supply the 100MHz refclk generation or so. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-13-heiko@sntech.de [ upstream commit: ee078c7daa98353496410b715a5acbb41d7d3a90 ] (cherry picked from commit 48951cb085998a5c8e3650351a794b136dac648f) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: define cpu-supply on the Qnap-TS433Heiko Stuebner2024-11-081-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TS433 seems to use a silergy,syr827 regulator for the cpu supply. At least that is the compatible used in the vendor devicetree, though it could very well also be another fan53555 clone. Define the needed regulator node and hook up the cpu-supply to the cpu cores. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-12-heiko@sntech.de [ upstream commit: 99b36ba910d896bddbb9a190ca686c6d9cd0325f ] (cherry picked from commit 2f0afd1a3cbf6f3192dc7a5c496affab718671b3) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add gpio-keys to Qnap-TS433Heiko Stuebner2024-11-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TS433 has 3 buttons, power and copy in the front as well as a reset pinhole button on the back. The power-button is connected to the embedded controller while the other two buttons are just gpio connected. Add the gpio-keys definition for the two buttons we can handle right now. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-11-heiko@sntech.de [ upstream commit: 9b682d31b24f1f70b5b4d0618095d46e0722b9d8 ] (cherry picked from commit f0b858c751382ee9faf18f9b19b0817c6b50ac1c) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable the tsadc on the Qnap-TS433Heiko Stuebner2024-11-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable the tsadc node to allow for temperature measurements of the soc. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-10-heiko@sntech.de [ upstream commit: 2dfdddd9d20306fd0d04b88fcbbf36d76fb67f11 ] (cherry picked from commit d33949501abd1145ea572b605844f0ef4247478d) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add hdd leds to Qnap-TS433Heiko Stuebner2024-11-081-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the 4 gpio-controlled LEDs to the Qnap-TS433. They are meant for individual disk activitivy, but I haven't found a way for how to connect them to their individual sata slot yet. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-9-heiko@sntech.de [ upstream commit: ea91aabf18bcad6f5eceae6848ea6570ea61f126 ] (cherry picked from commit 5a11b1bb40ac7b39e04077c045c3e3409fa352e2) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add board-aliases for Qnap-TS433Heiko Stuebner2024-11-081-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the aliases for the internal network interface as well as the emmc on the board and make sure the dedicated RTC is always the first one. The TS433 actually has two rtc devices. One coming from the rk809 pmic without added functionality and also a dedicated RTC from Mycrocrystal that is battery backed to keep the time. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-8-heiko@sntech.de [ upstream commit: dadd4256e12360d3ff1f6481b2e4697f9d890caf ] (cherry picked from commit cb53815764403f7f17967a32eec2aeb6625b396f) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable sata1+2 on Qnap-TS433Heiko Stuebner2024-11-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TS433 has 4 bays. The last two are accessed via a pci-connected sata controller, while the first two are accessed via the rk3568's sata controllers. Enable these two now. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-7-heiko@sntech.de [ upstream commit: 673c1353b3d476b9c5df6b84a777ed171e5594f5 ] (cherry picked from commit dfa45bbda057851d0c2167b4c311c0301637cc19) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: add stdout path on Qnap-TS433Heiko Stuebner2024-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As most Rockchip boards do, the TS433 also uses uart2 for its serial output. Set the correct chosen entry for it. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-6-heiko@sntech.de [ upstream commit: e1cb5d8a92e41171bf4d5ddc459bd96372500901 ] (cherry picked from commit 1e1af2af2192490a3d174624ac1bb976aa6afffa) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable usb ports on Qnap-TS433Heiko Stuebner2024-11-081-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable usb controllers and phys and add regulator infrastructure for the usb ports on the TS433. Of course there are no schematics available for the device, so the regulator information comes from the vendor-devicetree with unknown accuracy. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-5-heiko@sntech.de [ upstream commit: d992203f57c5caad0dbd4a9c669d79b315873c81 ] (cherry picked from commit bb745ef13efb9f6589f9eda8f66664bf263a13f3) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable uart0 on Qnap-TS433Heiko Stuebner2024-11-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Uart0 is connected to an MCU on the board that handles system control like the fan-speed. So far no driver for it is available though. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-4-heiko@sntech.de [ upstream commit: 07ef8be476bebd77cba3ca4804be03cc0dba414f ] (cherry picked from commit aaa5b1c4bd8f0e4327078d513f0eef05cb829bcf) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: enable second PCIe controller on the Qnap-TS433Heiko Stuebner2024-11-081-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TS433 uses both pcie controllers for sata and the 2nd network interface. Set the needed data-lanes in the pcie3 phy and enable the second pcie controller, as well as remove the bifurcation comment. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-3-heiko@sntech.de [ upstream commit: 0f5f87a1d602a33028522784eb005647fa1b5c11 ] (cherry picked from commit 7d8f260e65cc84076ec9456954de0f136948a2c8)
| * arm64: dts: rockchip: add PCIe supply regulator to Qnap-TS433Heiko Stuebner2024-11-081-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the vcc3v3-supply regulator and its link to the pcie controllers. Tested-by: Uwe Kleine-König <ukleinek@debian.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240723195538.1133436-2-heiko@sntech.de [ upstream commit: e0ec6d48226fb3d4df18895b56f0b7a94c0fe474 ] (cherry picked from commit 59939b4343db08fa08098238160007e6ded72be9) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier boardMarek Vasut2024-11-091-0/+20
|/ | | | | | | | | | | | | | | | | | Add support for the DH electronics i.MX6DL DHCOM SoM and a PDK2 evaluation board. The evaluation board features three serial ports, USB OTG, USB host with an USB hub, Fast or Gigabit ethernet, eMMC, uSD, SD, analog audio, PCIe and HDMI video output. All of the aforementioned features except for mSATA are supported, mSATA is not available on i.MX6DL and is only available on DHCOM populated with i.MX6Q SoC which is already supported upstream. Backport from linux-next commit c3f5d76a6e03 ("ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier board") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2024-10-291-0/+6
|\ | | | | | | | | | | | | | | CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23080 - board: migrate PolarFire to use OF_UPSTREAM - dts: align DT with QEMU amd-microblaze-v-virt platform - riscv: fix resume utility
| * riscv: dts: mpfs: migrate to OF_UPSTREAMConor Dooley2024-10-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The U-Boot copy of the mpfs devicetree has, in general, been neglected somewhat in comparison to the one in Linux. Moving to OF_UPSTREAM to keep both in sync should serve to eliminate that discrepancy. Additionally, moving to OF_UPSTREAM will let U-Boot automatically pick up the devicetree rework that is in progress at [1]. Link: https://lore.kernel.org/all/20241002-private-unequal-33cfa6101338@spud/ [1] Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
* | Merge patch series "boards: siemens: iot2050: SM variant, sysinfo support, ↵Tom Rini2024-10-295-10/+79
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes & cleanups" Jan Kiszka <jan.kiszka@siemens.com> says: This adds support for the new IOT2050 SM variant, introduces a sysinfo driver which also permits SMBIOS support and switches the board to OF_UPSTREAM. There are some further fixes for the boards included as well. Not yet included is configuration support for DMA isolation via the PVU as this depends on not yet merged DT bindings and another overlay. [trini: This is just the first 10 patches in the series for now] Link: https://lore.kernel.org/r/cover.1729577070.git.jan.kiszka@siemens.com
| * arm64: dts: ti: iot2050: Add overlays for M.2 used by firmwareJan Kiszka2024-10-282-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow firmware to pick up all DTs from here, move the overlays that are normally applied during DT fixup to the kernel source as well. Hook then into the build nevertheless to ensure that regular checks are performed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/91f8b825467651ebd51a4051f153ab136eeb1849.1724830741.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com> [ upstream commit: dba27d026fc841d28a0ed373f617cc84ec0e4504 ] (cherry picked from commit 741915246a92fc4c21537f9623a69612f7cef03a)
| * arm64: dts: ti: iot2050: Disable lock-step for all iot2050 boardsLi Hua Qian2024-10-283-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PG1 A variant of the iot2050 series has been identified which partially lacks support for lock-step mode. This implies that all iot2050 boards can't support this mode. As a result, lock-step mode has been disabled across all iot2050 boards for consistency and to avoid potential issues. Signed-off-by: Li Hua Qian <huaqian.li@siemens.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/d1f5f84db7a1597cd29628a0b503e578367b7b40.1724830741.git.jan.kiszka@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com> [ upstream commit: e0133f883cf115d9e97e704169a9fb6003caefb2 ] (cherry picked from commit 4b4872feb66a9043741819a57af280ffb4a96608)
* | arm64: dts: rockchip: add SPI flash on NanoPC-T6Marcin Juszkiewicz2024-10-261-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board. It is populated with 32MB one on LTS version. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-5-edff247e8c02@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: a22a629c63b1addcf2d81eaf30383c1deca5b7a9 ] (cherry picked from commit 7588da65fdf09c7de9f903780c212a8ae96f2866) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: add NanoPC-T6 LTSMarcin Juszkiewicz2024-10-261-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the LTS (2310) version the miniPCIe slot got removed and USB 2.0 setup has changed. There are two external accessible ports and two ports on the internal header. There is an on-board USB hub which provides: - one external connector (bottom one) - two internal ports on pin header - one port for m.2 E connector The top USB 2.0 connector comes directly from the SoC. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-4-edff247e8c02@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: db1dcbe5f752d423421f77d54d246398b196f670 ] (cherry picked from commit f4a834fbc8cdb40fddd63d083e8d1c6189ba62dc) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: move NanoPC-T6 parts to DTSMarcin Juszkiewicz2024-10-262-17/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MiniPCIe slot is present only in first version of NanoPC-T6 (2301). Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-3-edff247e8c02@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: aea8d84070fe0846961deb23228d9dd3f8caefb3 ] (cherry picked from commit 697963b1c22336a44ac2e33536c652aae1671b3d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: prepare NanoPC-T6 for LTS boardMarcin Juszkiewicz2024-10-262-930/+947
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FriendlyELEC introduced a second version of NanoPC-T6 SBC. Create common include file and make NanoPC-T6 use it. Following patches will add LTS version. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Link: https://lore.kernel.org/r/20240829-friendlyelec-nanopc-t6-lts-v6-2-edff247e8c02@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: d14f3a4f1feabb6bb5935bf3b275a1e6bf2208eb ] (cherry picked from commit e8b52bdfe5a1444edd1b9bb7cc10b9781d72cc84) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: Add Hardkernel ODROID-M1SJonas Karlman2024-10-251-0/+663
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hardkernel ODROID-M1S is a single-board computer based on Rockchip RK3566 SoC. It features e.g. 4/8 GB LPDDR4 RAM, 64 GB eMMC, SD-card, GbE LAN, HDMI 2.0, M.2 NVMe and USB 2.0/3.0. Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240827211825.1419820-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 10dc64fe0f980c47c7e747885ddf7a8c12780337 ] (cherry picked from commit f811548e758b52896f725753086c42b49dc42c0d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: Correct vendor prefix for Hardkernel ODROID-M1Jonas Karlman2024-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vendor prefix for Hardkernel ODROID-M1 is incorrectly listed as rockchip. Use the proper hardkernel vendor prefix for this board, while at it also drop the redundant soc prefix. Fixes: fd3583267703 ("arm64: dts: rockchip: Add Hardkernel ODROID-M1 board") Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240827211825.1419820-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 735065e774dcfc62e38df01a535862138b6c92ed ] (cherry picked from commit e7259a2c4a6f2ebdfc96b8bbffc77fe67604b11f) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: dts: rockchip: Add Hardkernel ODROID-M2Jonas Karlman2024-10-251-0/+903
|/ | | | | | | | | | | | | | | | | | The Hardkernel ODROID-M2 is a single-board computer based on Rockchip RK3588S2 SoC. It features e.g. 8/16 GB LPDDR5 RAM, 64 GB eMMC, SD-card, GbE LAN, HDMI 2.0, M.2 NVMe and USB 2.0/3.0/Type-C. Add initial support for eMMC, SD-card, Ethernet, PCIe and USB. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240901112020.3224704-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: ce48b8c976ce439c336def6e06bf8224a8ff9125 ] (cherry picked from commit 7ba62d8b4cb010c6fcb7077550b46d5f5fb5af6d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* Merge tag 'u-boot-imx-master-20241018a' of ↵Tom Rini2024-10-182-1/+29
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22796 - Switch to using upstream DT on DH i.MX8MP DHCOM PDK2/PDK3. - Add ability to build fallback DTBOs from arch/$(ARCH)/dts. - Remove fdt_high and initrd_high env variables from imx6-dhcom. - Add dummy clk for imx8. - Fix DT corruption in imx8_cpu. - Improve DDR stability on pico-imx7d.
| * dts: Add ability to build fallback DTBOs from arch/$(ARCH)/dtsMarek Vasut2024-10-182-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the enablement of OF_UPSTREAM results on the build system searching for DTs only in dts/upstream/ . There are platforms which use U-Boot specific DTBOs applied on top of U-Boot control DT during SPL stage, and source DTs for these are located in arch/$(ARCH)/dtb. Add dedicated 'dtbos' target which builds only .dtbos and not .dtbs and in case CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS is enabled, build this target for arch/$(ARCH)/dtb to generate local U-Boot specific DTBOs. Adjust top level Makefile so binman would search for .dtb and .dtbo in both OF_UPSTREAM specific paths and arch/$(ARCH)/dtb for the .dtbo case in case CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS is enabled. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de>
* | Extend usage for OF_OVERLAY_LIST beyond SPLJan Kiszka2024-10-171-2/+2
|/ | | | | | | | | | | Allow to use OF_OVERLAY_LIST also for the case that the overlays just need be built, e.g. when they will be picked up by binman as artifacts of the final U-Boot image. The IOT2050 boards have such a need when switching to OF_UPSTREAM. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* dts: Deduplicate dtbs targetWIP/14Oct2024Marek Vasut2024-10-143-24/+0
| | | | | | | | | | | The dtbs: target is almost identical in all architecture Makefiles. All architecture Makefiles include scripts/Makefile.dts . Deduplicate the dtbs: target into scripts/Makefile.dts . No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom, OF_UPSTREAM
* Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/13Oct2024Tom Rini2024-10-132-3/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This switches all boards with the Allwinner H616/H618/H313/H700 SoCs over to use OF_UPSTREAM. We are doing it for this SoC family only since the DTs between the U-Boot and the kernel repo are exactly identical, whereas other families have one compatibility fix in U-Boot to allow booting older kernels. Other will follow if this plays out well. The biggest chunk otherwise is adding support for an Anbernic game console, using the H700 SoC. For that we need to enhance the DRAM support code, and pick two DT commits from the mainline kernel/DT rebasing repo, followed by the defconfig patch. On top of that two small fixes for the old Allwinner A80. Gitlab CI passed, and I booted that briefly on some boards, including an H616 and an H618 one (with LPDDR4).
| * arm64: dts: allwinner: h616: Add r_i2c pinctrl nodesChris Morgan2024-10-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl nodes for the r_i2c node. Without the pinmux defined the r_i2c bus may fail to work, possibly if the bootloader uses rsb mode for the PMIC. Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file") Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file") Link: https://lore.kernel.org/r/20240710231718.106894-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: 7c9ea4ab76176f65f4f55aa144f9145a4bccaacb ] (cherry-picked from commit 1665557aa57c2140d014d68dfe1a1f92f9baac82) Reviewed-by: Andre Przywara <andre.przywara@arm.com>
| * arm64: dts: allwinner: h616: Change RG35XX Series from r_rsb to r_i2cChris Morgan2024-10-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the Anbernic RG35XX series to use the r_i2c bus for the PMIC instead of the r_rsb bus. This is to keep the device tree consistent as there are at least 3 devices (the RG35XX-SP, RG28XX, and RG40XX-H) that have an external RTC on the r_i2c bus. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Ryan Walklin <ryan@testtoast.com> Link: https://lore.kernel.org/r/20240710231718.106894-4-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org> [ upstream commit: c712e5d0985628b1df13930489b49b740e610a2b ] (cherry picked from commit 43c3a035746af3c8cad5b65055d88f1de8406823) Reviewed-by-by: Andre Przywara <andre.przywara@arm.com>
* | Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"WIP/11Oct2024Tom Rini2024-10-111-1/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simon Glass <sjg@chromium.org> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
| * global: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass2024-10-111-1/+1
| | | | | | | | | | | | | | | | | | Complete this rename for all directories outside arch/ board/ drivers/ and include/ Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
* | Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstreamWIP/01Oct2024-nextTom Rini2024-10-011487-17123/+69996
|/ | | | [1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
* arm64: dts: ti: k3-am62x-sk-common: Add bootph-all property in phy_gmii_sel nodeChintan Vankar2024-08-301-0/+4
| | | | | | | | | | | | | | | | Add missing bootph-all property for CPSW MAC's PHY node phy_gmii_sel. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Chintan Vankar <c-vankar@ti.com> Link: https://lore.kernel.org/r/20240430085048.3143665-1-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> [ upstream commit: ba50141137fae205a731005e70687f4a52289050 ] (cherry picked from commit 2bdd1743a9f6515efe7c3648a25d63b4a9ce4a10) Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
* arm64: dts: rockchip: change spi-max-frequency for Radxa ROCK 3CFUKAUMI Naoki2024-08-121-1/+1
| | | | | | | | | | | | | SPI NOR flash chip may vary, so use safe(lowest) spi-max-frequency. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20240623023329.1044-3-naoki@radxa.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 06f6dd4d607766a527e37529f2f3f90dd1464293 ] (cherry picked from commit dd40945a1d0e28ae6eaf9da04f8e2dcebf8233ea) Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* arm64: dts: rockchip: add ROCK 5 ITX boardHeiko Stuebner2024-08-091-0/+1177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ROCK 5 ITX as the name suggests is made in the ITX form factor and actually built in a form to be used in a regular case even providing connectors for regular front-panel io. It can be powered either by 12V, ATX power-supply or PoE. Notable peripherals are the 4 SATA ports, M.2 M-Key slot, M.2 E-key slot, 2*2.5Gb PCIe-connected Ethernet NICs. As of yet unsupported display options consist of 2*HDMI, DP via USB-c, eDP + 2*DSI via PCB connectors. USB ports are 4*USB3 + 2*USB2 on the back panel and 2-port front-panel connector. Schematics for the board can be found on - https://dl.radxa.com/rock5/5itx/radxa_rock_5_itx_X1100_schematic.pdf - https://dl.radxa.com/rock5/5itx/v1110/radxa_rock_5itx_v1110_schematic.pdf Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240704153815.837392-3-heiko@sntech.de [ upstream commit: 31390eb8ffbf2b6be7d789708ec08b635d7a3eb8 ] (cherry picked from commit 9cff9fef0a295e3b8feb7bc4116a297a842cad01) Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* arm64: dts: rockchip: add thermal zones information on RK3588Alexey Charkov2024-08-091-0/+153
| | | | | | | | | | | | | | | | | | | | | | | | This includes the necessary device tree data to allow thermal monitoring on RK3588(s) using the on-chip TSADC device, along with trip points for automatic thermal management. Each of the CPU clusters (one for the little cores and two for the big cores) get a passive cooling trip point at 85C, which will trigger DVFS throttling of the respective cluster upon reaching a high temperature condition. All zones also have a critical trip point at 115C, which will trigger a reset. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20240617-rk-dts-additions-v5-1-c1f5f3267f1e@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: 510cd9e688453166b2bff3999ed21cac97385bb5 ] (cherry picked from commit 33e7079543d5eee1415b937054e8634000d1bde4) Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPsDragan Simic2024-08-097-3076/+3090
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their contents appropriately, to prepare them for the ability to specify different CPU and GPU OPPs for each of the supported RK3588 SoC variants. As already discussed, [1][2][3][4] some of the RK3588 SoC variants require different OPPs, and it makes more sense to have the OPPs already defined when a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file to also include a separate rk3588*-opp.dtsi file. The choice of the SoC variant is already made by the inclusion of the SoC dtsi file into the board dts(i) file, and it doesn't make much sense to, effectively, allow the board dts(i) file to include and use an incompatible set of OPPs for the already selected RK3588 SoC variant. The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra" suffixes to denote the DT data shared between all RK5588 SoC variants, and the DT data shared between the unrestricted SoC variants, respectively. For example, the DT data for the RK3588 includes both rk3588-base.dtsi and rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT data for the RK3588S variant includes rk3588-base.dtsi only, because it's a restricted SoC variant, feature- and interface-wise. This achieves a more logical naming of the RK3588 SoC dtsi files, which reflects the way DT data for the SoC variants is built by "stacking" the SoC variant features made available through the "-base" and "-extra" SoC dtsi files. Additionally, the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are no longer parents to any other SoC variant dtsi files, which should help with making the new "stacking" approach cleaner and easier to follow. The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake of consistency. This also keeps the "-base" and "-extra" groups of the dtsi files together when looked at in a directory listing, which is helpful. The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no more than one SoC variant uses those OPPs, or be put into a separate "-opp" dtsi file that's shared between and included from two or more SoC variant dtsi files. An example for the former is the non-shared OPP data that should go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and an example for the latter is the shared OPP data that should be put into rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if the OPPs for the RK3588 and RK3588S SoC variants are ever made different, the shared rk3588-opp.dtsi file should be deleted and the new OPPs should be put directly into rk3588.dtsi and rk3588s.dtsi. [4] No functional changes are introduced, which was validated by decompiling and comparing all affected dtb files before and after these changes. As a side note, due to the nature of introduced changes, this commit is best viewed using the --break-rewrites option for git-log(1). [1] https://lore.kernel.org/linux-rockchip/646a33e0-5c1b-471c-8183-2c0df40ea51a@cherry.de/ [2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/ [3] https://lore.kernel.org/linux-rockchip/035a274be262528012173d463e25b55f@manjaro.org/ [4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: def88eb4d8365a4aa064d28405d03550a9d0a3be ] (cherry picked from commit bf8f631f62026a6b844d34c7e0549e4ec3fd4716) Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* arm64: dts: rockchip: Add FriendlyElec CM3588 NAS boardSebastian Kropatsch2024-08-092-0/+1431
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. To reflect the hardware setup, add device tree sources for the SoM and the NAS daughter board as separate files. Hardware features: - Rockchip RK3588 SoC - 4GB/8GB/16GB LPDDR4x RAM - 64GB eMMC - MicroSD card slot - 1x RTL8125B 2.5G Ethernet - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs - 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A - 1x USB 3.0 Type-C with DP AltMode support - 2x HDMI 2.1 out, 1x HDMI in - MIPI-CSI Connector, MIPI-DSI Connector - 40-pin GPIO header - 4 buttons: power, reset, recovery, MASK, user button - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector PCIe bifurcation is used to handle all four M.2 sockets at PCIe 3.0 x1 speed. Data lane mapping in the DT is done like described in commit f8020dfb311d ("phy: rockchip-snps-pcie3: fix bifurcation on rk3588"). This device tree includes support for eMMC, SD card, ethernet, all USB2 and USB3 ports, all four M.2 slots, GPU, beeper, IR, RTC, UART debugging as well as the buttons and LEDs. The GPIOs are labeled according to the schematics. Reviewed-by: Space Meyer <git@the-space.agency> Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de> Link: https://lore.kernel.org/r/20240616215354.40999-3-seb-dev@mail.de Signed-off-by: Heiko Stuebner <heiko@sntech.de> [ upstream commit: e23819cf273c110662fdc392dcb55a75b3888609 ] (cherry picked from commit c1a8bf31d96d890dd8328ae452fe62971ac555c2) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-03-01 08:10:50 +0000