From 6b84683acc86f94c7dc15d621b5bca533bf8a01a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Jun 2024 00:57:25 +0200 Subject: ARM: stm32: Fix TAMP_SMCR BKP..PROT fields on STM32MP15xx Update the TAMP_SMCR BKP..PROT fields to put first 10 registers into protection zone 1 and next 5 into zone 2. This fixes use of boot counter which is often in zone 3 and has to be updated from Linux, which runs in NS. Fixes: 73f7fc944cf6 ("ARM: stm32: Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index f096fe538d8..ca202bec8ee 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -148,8 +148,8 @@ static void security_init(void) */ clrsetbits_le32(TAMP_SMCR, TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, - FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) | - FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20)); + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F)); /* GPIOZ: deactivate the security */ writel(BIT(0), RCC_MP_AHB5ENSETR); -- cgit From b0348a97de9e01fe2165520cfc1bc9ed5594f9ab Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Jul 2024 13:43:23 +0200 Subject: ARM: stm32: Fix secure_waitbits() mask check Do not apply bitwise AND to register value and expected value, only apply bitwise AND to register value and mask, and only then compare the result with expected value that the function polls for. Fixes: b49105320a5b ("stm32mp: psci: Implement PSCI system suspend and DRAM SSR") Signed-off-by: Marek Vasut --- arch/arm/mach-stm32mp/stm32mp1/psci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index bfbf420fdb5..a02a8988a68 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -393,8 +393,7 @@ static int __secure secure_waitbits(u32 reg, u32 mask, u32 val) asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); for (;;) { tmp = readl(reg); - tmp &= mask; - if ((tmp & val) == val) + if ((tmp & mask) == val) return 0; asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); if ((end - start) > delay) -- cgit