From 3675ac081ad5129cbcb22b06fb6d8e3264a30d20 Mon Sep 17 00:00:00 2001 From: Oleh Kravchenko Date: Sat, 15 May 2021 00:18:31 +0300 Subject: Add out4.ru O4-iMX-NANO board Board designed for quick prototyping and has one microSD port, 2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO, UART interfaces, and 2 RGB LEDs. Signed-off-by: Oleh Kravchenko Cc: Stefano Babic --- board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg | 91 +++++++++++++++++++++++ board/out4/o4-imx6ull-nano/Kconfig | 57 ++++++++++++++ board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg | 91 +++++++++++++++++++++++ board/out4/o4-imx6ull-nano/Makefile | 4 + board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c | 86 +++++++++++++++++++++ 5 files changed, 329 insertions(+) create mode 100644 board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg create mode 100644 board/out4/o4-imx6ull-nano/Kconfig create mode 100644 board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg create mode 100644 board/out4/o4-imx6ull-nano/Makefile create mode 100644 board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c (limited to 'board') diff --git a/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg b/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg new file mode 100644 index 00000000000..c0dcfe9a0c5 --- /dev/null +++ b/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2016 Freescale Semiconductor, Inc. +// Copyright (C) 2021 Oleh Kravchenko + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +/* Samsung K4B4G1646D-BCMA */ +DATA 4 0x020e04b4 0x000c0000 +DATA 4 0x020e04ac 0x00000000 +DATA 4 0x020e027c 0x00000030 +DATA 4 0x020e0250 0x00000030 +DATA 4 0x020e024c 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e0288 0x000c0030 +DATA 4 0x020e0270 0x00000000 +DATA 4 0x020e0260 0x00000030 +DATA 4 0x020e0264 0x00000030 +DATA 4 0x020e04a0 0x00000030 +DATA 4 0x020e0494 0x00020000 +DATA 4 0x020e0280 0x00000030 +DATA 4 0x020e0284 0x00000030 +DATA 4 0x020e04b0 0x00020000 +DATA 4 0x020e0498 0x00000030 +DATA 4 0x020e04a4 0x00000030 +DATA 4 0x020e0244 0x00000030 +DATA 4 0x020e0248 0x00000030 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00030009 +DATA 4 0x021b083c 0x01440148 +DATA 4 0x021b0848 0x40403640 +DATA 4 0x021b0850 0x4040322a +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b08c0 0x00944009 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x1b333030 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x926d0b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00211740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0x84180000 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b001c 0x02008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x15108030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00000227 +DATA 4 0x021b0004 0x0002552d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig new file mode 100644 index 00000000000..c2497d521f8 --- /dev/null +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -0,0 +1,57 @@ +if TARGET_O4_IMX6ULL_NANO + +config SYS_BOARD + default "o4-imx6ull-nano" + +config SYS_VENDOR + default "out4" + +config SYS_CONFIG_NAME + default "o4-imx6ull-nano" + +choice + prompt "Memory model" + default K4B4G1646D_BCMA + help + Memory type setup. + + Please choose correct memory model here. + +config K4B4G1646D_BCMA + bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)" + help + Samsung DDR3 SDRAM + K4B4G1646D-BCMA + +config MT41K256M16HA_125E + bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)" + help + Micron DDR3L SDRAM + MT41K256M16HA-125:E + +endchoice + +choice + prompt "Mainboard model" + default O4_IMX_NANO + help + Mainboard setup. + + Please choose correct main board model here. + +config O4_IMX_NANO + bool "O4-iMX-NANO" + help + A baseboard for EV-iMX280-NANO module: + https://out4.ru/products/board/18-o4-imx-nano.html + +endchoice + +config IMX_CONFIG + default "board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg" if K4B4G1646D_BCMA + default "board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg" if MT41K256M16HA_125E + +config DEFAULT_DEVICE_TREE + default "o4-imx-nano" if O4_IMX_NANO + +endif diff --git a/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg b/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg new file mode 100644 index 00000000000..6f823a7272a --- /dev/null +++ b/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2016 Freescale Semiconductor, Inc. +// Copyright (C) 2021 Oleh Kravchenko + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +/* Micron MT41K256M16HA-125:E */ +DATA 4 0x020e04b4 0x000c0000 +DATA 4 0x020e04ac 0x00000000 +DATA 4 0x020e027c 0x00000030 +DATA 4 0x020e0250 0x00000030 +DATA 4 0x020e024c 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e0288 0x000c0030 +DATA 4 0x020e0270 0x00000000 +DATA 4 0x020e0260 0x00000030 +DATA 4 0x020e0264 0x00000030 +DATA 4 0x020e04a0 0x00000030 +DATA 4 0x020e0494 0x00020000 +DATA 4 0x020e0280 0x00000030 +DATA 4 0x020e0284 0x00000030 +DATA 4 0x020e04b0 0x00020000 +DATA 4 0x020e0498 0x00000030 +DATA 4 0x020e04a4 0x00000030 +DATA 4 0x020e0244 0x00000030 +DATA 4 0x020e0248 0x00000030 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x0005000b +DATA 4 0x021b083c 0x01400144 +DATA 4 0x021b0848 0x4040343a +DATA 4 0x021b0850 0x4040342a +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b08c0 0x00944009 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x1b333030 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x91eb0b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00211740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0x84180000 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b001c 0x02008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x15108030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00000227 +DATA 4 0x021b0004 0x0002552d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/out4/o4-imx6ull-nano/Makefile b/board/out4/o4-imx6ull-nano/Makefile new file mode 100644 index 00000000000..a3f4646d9e0 --- /dev/null +++ b/board/out4/o4-imx6ull-nano/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2021 Oleh Kravchenko + +obj-y := o4-imx6ull-nano.o diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c new file mode 100644 index 00000000000..fec1755c32e --- /dev/null +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +static int setup_fec_clock(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) { + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + } + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return setup_fec_clock(); +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_CMD_BMODE)) + add_board_boot_modes(NULL); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + const char *model; + + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (model) + env_set("board_name", model); + } + + if (is_boot_from_usb()) { + env_set("bootcmd", "run bootcmd_mfg"); + env_set("bootdelay", "0"); + } + + return 0; +} -- cgit From 1180baec98147e05a8b3b36199ae22010a4d4fe7 Mon Sep 17 00:00:00 2001 From: Oleh Kravchenko Date: Sat, 15 May 2021 00:18:33 +0300 Subject: Add EV-iMX280-NANO-X-MB board A simple prototyping board with one microSD port, one Ethernet port, 2 USB ports, I2C, SPI, GPIO, and UART interfaces. Signed-off-by: Oleh Kravchenko Cc: Stefano Babic --- board/out4/o4-imx6ull-nano/Kconfig | 7 +++++++ board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c | 22 ++++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'board') diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig index c2497d521f8..e2ab80b6d4d 100644 --- a/board/out4/o4-imx6ull-nano/Kconfig +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -45,6 +45,12 @@ config O4_IMX_NANO A baseboard for EV-iMX280-NANO module: https://out4.ru/products/board/18-o4-imx-nano.html +config EV_IMX280_NANO_X_MB + bool "EV-IMX280-NANO-X-MB" + help + A simple baseboard for EV-iMX280-NANO module: + http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html + endchoice config IMX_CONFIG @@ -53,5 +59,6 @@ config IMX_CONFIG config DEFAULT_DEVICE_TREE default "o4-imx-nano" if O4_IMX_NANO + default "ev-imx280-nano-x-mb" if EV_IMX280_NANO_X_MB endif diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index fec1755c32e..edb200e9e55 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -39,16 +39,18 @@ static int setup_fec_clock(void) if (ret) return ret; - /* - * Use 50M anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - - ret = enable_fec_anatop_clock(1, ENET_50MHZ); - if (ret) - return ret; + if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + } enable_enet_clk(1); } -- cgit From cd18f1e6e6144bd72110b07144e77f9e84b2e7c8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 3 May 2021 11:21:27 -0700 Subject: imx: ventana: enable dm support for PCI and FEC ethernet Enable driver model support for FEC ethernet which allows us to remove the iomux and board_eth_init function. Replace the toggling of the ethernet phy reset with dt configuration. Enable driver model support for PCI which allows us to remove the eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for PCI devices on init such as the e1000 that is present on the GW552x. Convert board_pci_fixup to use dm callback and remove pcidisable env variable which is not supported for DM_PCI and thus leave PCI always enabled during init. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/common.h | 1 - board/gateworks/gw_ventana/gw_ventana.c | 99 ++++++--------------------------- 2 files changed, 16 insertions(+), 84 deletions(-) (limited to 'board') diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index d73850c5b90..813f7d9f562 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -11,7 +11,6 @@ #include "ventana_eeprom.h" /* GPIO's common to all baseboards */ -#define GP_PHY_RST IMX_GPIO_NR(1, 30) #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 5237f2dac43..1ed9c1a39f4 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -54,42 +53,6 @@ DECLARE_GLOBAL_DATA_PTR; struct ventana_board_info ventana_info; static int board_type; -/* ENET */ -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* PHY nRST */ - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), -}; - -static void setup_iomux_enet(int gpio) -{ - SETUP_IOMUX_PADS(enet_pads); - - /* toggle PHY_RST# */ - gpio_request(gpio, "phy_rst#"); - gpio_direction_output(gpio, 0); - mdelay(10); - gpio_set_value(gpio, 1); - mdelay(100); -} - #ifdef CONFIG_USB_EHCI_MX6 /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */ int board_ehci_hcd_init(int port) @@ -195,40 +158,7 @@ int mv88e61xx_hw_reset(struct phy_device *phydev) } #endif // CONFIG_MV88E61XX_SWITCH -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FEC_MXC - struct ventana_board_info *info = &ventana_info; - - if (test_bit(EECONFIG_ETH0, info->config)) { - setup_iomux_enet(GP_PHY_RST); - cpu_eth_init(bis); - } -#endif - -#ifdef CONFIG_E1000 - e1000_initialize(bis); -#endif - -#ifdef CONFIG_CI_UDC - /* For otg ethernet*/ - usb_eth_initialize(bis); -#endif - - /* default to the first detected enet dev */ - if (!env_get("ethprime")) { - struct eth_device *dev = eth_get_dev_by_index(0); - if (dev) { - env_set("ethprime", dev->name); - printf("set ethprime to %s\n", env_get("ethprime")); - } - } - - return 0; -} - #if defined(CONFIG_VIDEO_IPUV3) - static void enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); @@ -427,7 +357,6 @@ int power_init_board(void) return 0; } -#if defined(CONFIG_CMD_PCI) int imx6_pcie_toggle_reset(void) { if (board_type < GW_UNKNOWN) { @@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void) #define MAX_PCI_DEVS 32 struct pci_dev { pci_dev_t devfn; + struct udevice *dev; unsigned short vendor; unsigned short device; unsigned short class; @@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS]; int pci_devno; int pci_bridgeno; -void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, - unsigned short vendor, unsigned short device, - unsigned short class) +void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev) { - int i; - u32 dw; + struct pci_child_plat *pdata = dev_get_parent_plat(udev); struct pci_dev *pdev = &pci_devs[pci_devno++]; + unsigned short vendor = pdata->vendor; + unsigned short device = pdata->device; + unsigned int class = pdata->class; + pci_dev_t dev = dm_pci_get_bdf(udev); + int i; debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); /* store array of devs for later use in device-tree fixup */ + pdev->dev = udev; pdev->devfn = dev; pdev->vendor = vendor; pdev->device = device; @@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, if (vendor == PCI_VENDOR_ID_PLX && (device & 0xfff0) == 0x8600 && PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { + ulong val; debug("configuring PLX 860X downstream PERST#\n"); - pci_hose_read_config_dword(hose, dev, 0x62c, &dw); - dw |= 0xaaa8; /* GPIO1-7 outputs */ - pci_hose_write_config_dword(hose, dev, 0x62c, dw); + pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32); + val |= 0xaaa8; /* GPIO1-7 outputs */ + pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32); - pci_hose_read_config_dword(hose, dev, 0x644, &dw); - dw |= 0xfe; /* GPIO1-7 output high */ - pci_hose_write_config_dword(hose, dev, 0x644, dw); + pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32); + val |= 0xfe; /* GPIO1-7 output high */ + pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32); mdelay(100); } } -#endif /* CONFIG_CMD_PCI */ #ifdef CONFIG_SERIAL_TAG /* -- cgit From b8916306d1061b254d066ccaa4c797896c96a2c1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 May 2021 18:43:06 -0300 Subject: pico-imx6: README: Fix the boot mode settings URL The original URL that explains the boot mode setting is no longer valid. Update to the new one. Signed-off-by: Fabio Estevam --- board/technexion/pico-imx6/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/technexion/pico-imx6/README b/board/technexion/pico-imx6/README index f1e84bfe829..f4970865022 100644 --- a/board/technexion/pico-imx6/README +++ b/board/technexion/pico-imx6/README @@ -20,7 +20,7 @@ If the eMMC has already a U-Boot flashed then the user can go to step 2 below in order to update U-Boot. Put pico board in USB download mode (Refer to the following link for details: -https://www.technexion.com/support/knowledgebase/boot-configuration-settings-for-pico-baseboards/). +https://developer.technexion.com/docs/pico-evaluation-kit-boot-mode-settings ) Connect a USB to serial adapter between the host PC and pico. -- cgit From fe133eb192a8a55813a4dc5ec72ecf45ba74f65e Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Mon, 31 May 2021 15:50:40 +0200 Subject: imx: support for conga-QMX8 board Add i.MX8QM qmx8 congatec board support U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx --- board/congatec/cgtqmx8/Kconfig | 14 ++ board/congatec/cgtqmx8/MAINTAINERS | 7 + board/congatec/cgtqmx8/Makefile | 11 + board/congatec/cgtqmx8/cgtqmx8.c | 460 ++++++++++++++++++++++++++++++++++++ board/congatec/cgtqmx8/imximage.cfg | 21 ++ board/congatec/cgtqmx8/spl.c | 77 ++++++ board/congatec/common/Kconfig | 48 ++++ board/congatec/common/Makefile | 23 ++ board/congatec/common/mmc.c | 49 ++++ 9 files changed, 710 insertions(+) create mode 100644 board/congatec/cgtqmx8/Kconfig create mode 100644 board/congatec/cgtqmx8/MAINTAINERS create mode 100644 board/congatec/cgtqmx8/Makefile create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c create mode 100644 board/congatec/cgtqmx8/imximage.cfg create mode 100644 board/congatec/cgtqmx8/spl.c create mode 100644 board/congatec/common/Kconfig create mode 100644 board/congatec/common/Makefile create mode 100644 board/congatec/common/mmc.c (limited to 'board') diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig new file mode 100644 index 00000000000..72730392615 --- /dev/null +++ b/board/congatec/cgtqmx8/Kconfig @@ -0,0 +1,14 @@ +if TARGET_CONGA_QMX8 + +config SYS_BOARD + default "cgtqmx8" + +config SYS_VENDOR + default "congatec" + +config SYS_CONFIG_NAME + default "cgtqmx8" + +source "board/congatec/common/Kconfig" + +endif diff --git a/board/congatec/cgtqmx8/MAINTAINERS b/board/congatec/cgtqmx8/MAINTAINERS new file mode 100644 index 00000000000..53bc0f93b76 --- /dev/null +++ b/board/congatec/cgtqmx8/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM CGTQMX8 BOARD +M: Oliver Graute +S: Maintained +F: board/congatec/cgtqmx8/ +F: arch/arm/dts/imx8qm-cgtqmx8.dts +F: include/configs/cgtqmx8.h +F: configs/cgtqmx8_defconfig diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile new file mode 100644 index 00000000000..4b59dbb6bc7 --- /dev/null +++ b/board/congatec/cgtqmx8/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cgtqmx8.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c new file mode 100644 index 00000000000..fb0cf091389 --- /dev/null +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 congatec AG + * Copyright (C) 2019 Oliver Graute + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void board_late_mmc_env_init(void); +void init_clk_usdhc(u32 index); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + /* sc_ipc_t ipcHndl = 0; */ + sc_err_t scierr = 0; + + /* When start u-boot in XEN VM, directly return */ + /* if (IS_ENABLED(CONFIG_XEN)) */ + /* return 0; */ + + /* ipcHndl = gd->arch.ipc_channel_handle; */ + + /* Power up UART0, this is very early while power domain is not working */ + scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (scierr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (scierr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (scierr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (onboard eMMC) USDHC1 + * mmc1 (external SD card) USDHC2 + * mmc2 (onboard µSD) USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + /* onboard eMMC */ + if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + /* external SD card */ + if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + case 2: + /* onboard µSD */ + if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#if (IS_ENABLED(CONFIG_FEC_MXC)) + +#include + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); +} + +static void enet_device_phy_reset(void) +{ + gpio_set_value(FEC0_RESET, 0); + udelay(50); + gpio_set_value(FEC0_RESET, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(struct bd_info *bis) +{ + setup_iomux_fec(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(void) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define BKL_ENABLE IMX_GPIO_NR(1, 7) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable LVDS */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable backlight */ + gpio_request(BKL_ENABLE, "bkl_enable"); + gpio_direction_output(BKL_ENABLE, 1); + + /* ethernet reset */ + gpio_request(FEC0_RESET, "enet0_reset"); + gpio_direction_output(FEC0_RESET, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: conga-QMX8\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +extern u32 _end_ofs; +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "QMX8"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef IMX_LOAD_HDMI_FIMRWARE + char *end_of_uboot; + char command[256]; + + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); + + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +/* Only Enable USB3 resources currently */ +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg new file mode 100644 index 00000000000..e324c7ca37c --- /dev/null +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c new file mode 100644 index 00000000000..2a5d4c1bcd5 --- /dev/null +++ b/board/congatec/cgtqmx8/spl.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig new file mode 100644 index 00000000000..5c205bd8304 --- /dev/null +++ b/board/congatec/common/Kconfig @@ -0,0 +1,48 @@ +if !ARCH_IMX8M && !ARCH_IMX8 + +config CHAIN_OF_TRUST + depends on !FIT_SIGNATURE && SECURE_BOOT + imply CMD_BLOB + imply CMD_HASH if ARM + select FSL_CAAM + select SPL_BOARD_INIT if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + select CMD_EXT4 if ARM + select CMD_EXT4_WRITE if ARM + bool + default y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y if CHAIN_OF_TRUST + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) + +endif + +config VOL_MONITOR_LTC3882_READ + depends on VID + bool "Enable the LTC3882 voltage monitor read" + default n + help + This option enables LTC3882 voltage monitor read + functionality. It is used by common VID driver. + +config VOL_MONITOR_LTC3882_SET + depends on VID + bool "Enable the LTC3882 voltage monitor set" + default n + help + This option enables LTC3882 voltage monitor set + functionality. It is used by common VID driver. + +config USB_TCPC + bool "USB Typec port controller simple driver" + default n + help + Enable USB type-c port controller (TCPC) driver diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile new file mode 100644 index 00000000000..d4ddfbf9716 --- /dev/null +++ b/board/congatec/common/Makefile @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else + +obj-y += mmc.o + +endif diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c new file mode 100644 index 00000000000..bb7a3d4a9aa --- /dev/null +++ b/board/congatec/common/mmc.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + */ +#include +#include +#include +#include +#include +#include +#include + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0)) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} -- cgit From a3a0bc85c0501c2374966104b8daca6c69101625 Mon Sep 17 00:00:00 2001 From: Navin Sankar Velliangiri Date: Tue, 18 May 2021 09:03:20 +0530 Subject: imx: Add SeeedStudio NPI-IMX6ULL Support CPU: Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 49C Reset cause: POR Model: Seeed NPi iMX6ULL Dev Board with NAND Board: Seeed NPi i.MX6ULL Dev Board DRAM: 512 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Navin Sankar Velliangiri Note: Changes in v2: * removed unnecessary space in imx6ull-seeed-npi-imx6ull-dev-board.dts file. * Used SZ_2M for CONFIG_SYS_MALLOC_LEN size allocation. --- board/seeed/npi_imx6ull/Kconfig | 12 ++ board/seeed/npi_imx6ull/MAINTAINERS | 9 ++ board/seeed/npi_imx6ull/Makefile | 4 + board/seeed/npi_imx6ull/README | 61 ++++++++++ board/seeed/npi_imx6ull/npi_imx6ull.c | 114 +++++++++++++++++++ board/seeed/npi_imx6ull/spl.c | 205 ++++++++++++++++++++++++++++++++++ 6 files changed, 405 insertions(+) create mode 100644 board/seeed/npi_imx6ull/Kconfig create mode 100644 board/seeed/npi_imx6ull/MAINTAINERS create mode 100644 board/seeed/npi_imx6ull/Makefile create mode 100644 board/seeed/npi_imx6ull/README create mode 100644 board/seeed/npi_imx6ull/npi_imx6ull.c create mode 100644 board/seeed/npi_imx6ull/spl.c (limited to 'board') diff --git a/board/seeed/npi_imx6ull/Kconfig b/board/seeed/npi_imx6ull/Kconfig new file mode 100644 index 00000000000..5e298299a32 --- /dev/null +++ b/board/seeed/npi_imx6ull/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NPI_IMX6ULL + +config SYS_BOARD + default "npi_imx6ull" + +config SYS_VENDOR + default "seeed" + +config SYS_CONFIG_NAME + default "npi_imx6ull" + +endif diff --git a/board/seeed/npi_imx6ull/MAINTAINERS b/board/seeed/npi_imx6ull/MAINTAINERS new file mode 100644 index 00000000000..c6a915c79b3 --- /dev/null +++ b/board/seeed/npi_imx6ull/MAINTAINERS @@ -0,0 +1,9 @@ +NPI_IMX6ULL BOARD +M: Navin Sankar Velliangiri +S: Maintained +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi +F: board/seeed/npi-imx6ull/ +F: configs/seeed_npi_imx6ull_defconfig +F: include/configs/npi_imx6ull.h diff --git a/board/seeed/npi_imx6ull/Makefile b/board/seeed/npi_imx6ull/Makefile new file mode 100644 index 00000000000..93ea413517d --- /dev/null +++ b/board/seeed/npi_imx6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := npi_imx6ull.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/seeed/npi_imx6ull/README b/board/seeed/npi_imx6ull/README new file mode 100644 index 00000000000..01d218a9bcb --- /dev/null +++ b/board/seeed/npi_imx6ull/README @@ -0,0 +1,61 @@ +How to use U-BOOT on SeeedStudio NPI-IMX6ULL Single Board Computer +------------------------------------------------------------------ + +- Configure and build U-Boot for NPI-IMX6ULL: + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-none-linux-gnueabihf- + $ make seeed_npi_imx6ull_defconfig + $ make + +This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 0 + SW4 -> 0 + SW5 -> 1 + SW6 -> 0 + SW7 -> 0 + SW8 -> 1 + +Boot from NAND: +- Boot the board using SD/MMC or Serial download and load the SPL into memory +either from SD/MMC or TFTP. + +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) + +Flash SPL to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr SPL + $ nand erase.part spl + $ nandbcb init $loadaddr 0x0 $filesize + +Flash u-boot image to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img + $ nand erase.part uboot + $ nand write $loadaddr uboot $filesize + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 1 + SW4 -> 0 + SW5 -> 0 + SW6 -> 1 + SW7 -> 0 + SW8 -> 0 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Reset the board using reset button and U-Boot should boot from NAND. diff --git a/board/seeed/npi_imx6ull/npi_imx6ull.c b/board/seeed/npi_imx6ull/npi_imx6ull.c new file mode 100644 index 00000000000..eb9ee555c85 --- /dev/null +++ b/board/seeed/npi_imx6ull/npi_imx6ull.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50MHz anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50MHz anatop loopbak REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Board: Seeed NPi i.MX6ULL Dev Board\n"); + + return 0; +} diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c new file mode 100644 index 00000000000..4b56f52d985 --- /dev/null +++ b/board/seeed/npi_imx6ull/spl.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration for Micron MT41K256M16TW-107 32M x 16 x 8 -> 512MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 32, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} -- cgit From 40496ac3b71b9589a9149d423b81133eebce07b1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 28 May 2021 10:26:57 -0300 Subject: mx7d: Add Storopack's SMEGW01 board Add support for Storopack's SMEGW01 board, which is an IoT gateway based on the i.MX7D SoC. Based on the original U-Boot work done by Phytec. Signed-off-by: Fabio Estevam --- board/storopack/smegw01/Kconfig | 12 +++++ board/storopack/smegw01/MAINTAINERS | 7 +++ board/storopack/smegw01/Makefile | 4 ++ board/storopack/smegw01/imximage.cfg | 100 +++++++++++++++++++++++++++++++++++ board/storopack/smegw01/smegw01.c | 95 +++++++++++++++++++++++++++++++++ 5 files changed, 218 insertions(+) create mode 100644 board/storopack/smegw01/Kconfig create mode 100644 board/storopack/smegw01/MAINTAINERS create mode 100644 board/storopack/smegw01/Makefile create mode 100644 board/storopack/smegw01/imximage.cfg create mode 100644 board/storopack/smegw01/smegw01.c (limited to 'board') diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig new file mode 100644 index 00000000000..4503b65419a --- /dev/null +++ b/board/storopack/smegw01/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SMEGW01 + +config SYS_BOARD + default "smegw01" + +config SYS_VENDOR + default "storopack" + +config SYS_CONFIG_NAME + default "smegw01" + +endif diff --git a/board/storopack/smegw01/MAINTAINERS b/board/storopack/smegw01/MAINTAINERS new file mode 100644 index 00000000000..6acb8b93418 --- /dev/null +++ b/board/storopack/smegw01/MAINTAINERS @@ -0,0 +1,7 @@ +SMEGW01 BOARD +M: Fabio Estevam +S: Maintained +F: board/storopack/ +F: arch/arm/dts/imx7d-smegw01.dts +F: configs/smegw01_defconfig +F: include/configs/smegw01.h diff --git a/board/storopack/smegw01/Makefile b/board/storopack/smegw01/Makefile new file mode 100644 index 00000000000..f02e7bb8b00 --- /dev/null +++ b/board/storopack/smegw01/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 NXP Semiconductors + +obj-y := smegw01.o diff --git a/board/storopack/smegw01/imximage.cfg b/board/storopack/smegw01/imximage.cfg new file mode 100644 index 00000000000..c7fa06996cc --- /dev/null +++ b/board/storopack/smegw01/imximage.cfg @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 PHYTEC America, LLC + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR initialization came from Phytec */ +DATA 4 0x30340004 0x4F400005 +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x0040002b +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x090b1109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000802 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00001f15 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f0f0707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000d6e +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 +CHECK_BITS_SET 4 0x307900c4 0x1 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c new file mode 100644 index 00000000000..e6bff80e556 --- /dev/null +++ b/board/storopack/smegw01/smegw01.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Fabio Estevam + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +}; + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_fec(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + return 0; +} -- cgit From ec3784d62646c8f765310d564a3fc898d9945088 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 7 Jun 2021 16:34:47 +0200 Subject: arm: mvebu: turris_mox: add support for board rescue mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add necessary config options and board code to support board factory reset / rescue mode on Turris MOX. In order to also support invoking rescue mode from U-Boot console, without having to press the factory reset button, put the rescue command into `bootcmd_rescue` default environment variable. When factory reset button is pressed, invoke rescue mode via distroboot by setting `boot_targets` to `rescue`. Rescue boot from console can be invoked by running run bootcmd_rescue Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 71 ++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) (limited to 'board') diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 15cbf92550e..a78f33661e7 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -10,11 +10,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -44,6 +46,8 @@ #define SFP_GPIO_PATH "/soc/internal-regs@d0000000/spi@10600/moxtet@1/gpio@0" #define PCIE_PATH "/soc/pcie@d0070000" #define SFP_PATH "/sfp" +#define LED_PATH "/leds/led" +#define BUTTON_PATH "/gpio-keys/reset" DECLARE_GLOBAL_DATA_PTR; @@ -373,6 +377,71 @@ int misc_init_r(void) return 0; } +static bool read_reset_button(void) +{ + struct udevice *button, *led; + int i; + + if (device_get_global_by_ofnode(ofnode_path(BUTTON_PATH), &button)) { + printf("Cannot find reset button!\n"); + return false; + } + + if (device_get_global_by_ofnode(ofnode_path(LED_PATH), &led)) { + printf("Cannot find status LED!\n"); + return false; + } + + led_set_state(led, LEDST_ON); + + for (i = 0; i < 21; ++i) { + if (button_get_state(button) != BUTTON_ON) + return false; + if (i < 20) + mdelay(50); + } + + led_set_state(led, LEDST_OFF); + + return true; +} + +static void handle_reset_button(void) +{ + if (read_reset_button()) { + const char * const vars[3] = { + "bootcmd", + "bootcmd_rescue", + "distro_bootcmd", + }; + + /* + * Set the above envs to their default values, in case the user + * managed to break them. + */ + env_set_default_vars(3, (char * const *)vars, 0); + + /* Ensure bootcmd_rescue is used by distroboot */ + env_set("boot_targets", "rescue"); + + printf("RESET button was pressed, overwriting boot_targets!\n"); + } else { + /* + * In case the user somehow managed to save environment with + * boot_targets=rescue, reset boot_targets to default value. + * This could happen in subsequent commands if bootcmd_rescue + * failed. + */ + if (!strcmp(env_get("boot_targets"), "rescue")) { + const char * const vars[1] = { + "boot_targets", + }; + + env_set_default_vars(1, (char * const *)vars, 0); + } + } +} + static void mox_print_info(void) { int ret, board_version, ram_size; @@ -543,6 +612,8 @@ int last_stage_init(void) printf("\n"); + handle_reset_button(); + return 0; } -- cgit From 45853413e2396e6a603d35e21d75712029a4cb19 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 7 Jun 2021 16:34:48 +0200 Subject: arm: mvebu: turris_mox: start blinking PHY LEDs when entering rescue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configure blinking on ethernet PHY LEDs on the MOX A board when entering rescue mode via reset button. Signed-off-by: Marek Behún Reviewed-by: Pali Rohár Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'board') diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index a78f33661e7..44c272c7cb8 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -377,6 +377,38 @@ int misc_init_r(void) return 0; } +static void mox_phy_modify(struct phy_device *phydev, int page, int reg, + u16 mask, u16 set) +{ + int val; + + val = phydev->drv->readext(phydev, MDIO_DEVAD_NONE, page, reg); + val &= ~mask; + val |= set; + phydev->drv->writeext(phydev, MDIO_DEVAD_NONE, page, reg, val); +} + +static void mox_phy_leds_start_blinking(void) +{ + struct phy_device *phydev; + struct mii_dev *bus; + + bus = miiphy_get_dev_by_name("neta@30000"); + if (!bus) { + printf("Cannot get MDIO bus device!\n"); + return; + } + + phydev = phy_find_by_mask(bus, BIT(1), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("Cannot get ethernet PHY!\n"); + return; + } + + mox_phy_modify(phydev, 3, 0x12, 0x700, 0x400); + mox_phy_modify(phydev, 3, 0x10, 0xff, 0xbb); +} + static bool read_reset_button(void) { struct udevice *button, *led; @@ -424,6 +456,9 @@ static void handle_reset_button(void) /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); + /* start blinking PHY LEDs */ + mox_phy_leds_start_blinking(); + printf("RESET button was pressed, overwriting boot_targets!\n"); } else { /* -- cgit From 3414712ba8a82d6566e00645da8d37ea085a9f7c Mon Sep 17 00:00:00 2001 From: Adrian Fiergolski Date: Tue, 8 Jun 2021 12:37:23 +0200 Subject: arm64: zynqmp: Writing correct value to ANALOG_BUS The default register configuration after powerup for PSSYSMON_ANALOG_BUS register is incorrect. Hence, fix this in SPL by writing correct fixed value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c") in Xilinx:embeddedsw[1]. [1] https://github.com/Xilinx/embeddedsw Signed-off-by: Adrian Fiergolski Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d05f0b2e120..ee4d0c85e6b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -287,6 +287,17 @@ int board_early_init_f(void) if (ret) return ret; + /* + * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon + * supply sense channel to SysMon supply registers inside the IP. + * This register must be programmed to complete SysMon IP + * configuration. The default register configuration after + * power-up is incorrect. Hence, fix this by writing the + * correct value - 0x3210. + */ + writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL, + ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS); + /* Delay is required for clocks to be propagated */ udelay(1000000); #endif -- cgit From 029bb91e806ed36dd48f0f967429bd5107464979 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 14 Jun 2021 16:45:58 +0200 Subject: arm: mvebu: turris_{omnia, mox}: ensure running bootcmd_rescue always works MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One of the points of putting the rescue boot command into default environment is that user can invoke it without physical access to the board (without having to press the factory reset button), by running run bootcmd_rescue in U-Boot's console. Therefore we have to ensure that bootcmd_rescue is always set to default value, regardless of whether the factory reset button was pressed. Otherwise the variable will be empty for example after upgrade from previous U-Boot. Fixes: ec3784d62646 ("arm: mvebu: turris_mox: add support for board rescue mode") Fixes: 176c3e7760a2 ("arm: mvebu: turris_omnia: support invoking rescue boot from console") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 14 +++++++++++--- board/CZ.NIC/turris_omnia/turris_omnia.c | 13 ++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-) (limited to 'board') diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 44c272c7cb8..428cd23a19d 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -440,10 +440,18 @@ static bool read_reset_button(void) static void handle_reset_button(void) { + const char * const vars[1] = { "bootcmd_rescue", }; + + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + if (read_reset_button()) { - const char * const vars[3] = { + const char * const vars[2] = { "bootcmd", - "bootcmd_rescue", "distro_bootcmd", }; @@ -451,7 +459,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(3, (char * const *)vars, 0); + env_set_default_vars(2, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index ade923f5994..8b2f94f959a 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -339,9 +339,17 @@ static int set_regdomain(void) static void handle_reset_button(void) { + const char * const vars[1] = { "bootcmd_rescue", }; int ret; u8 reset_status; + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); if (ret) { printf("omnia_mcu_read failed: %i, reset status unknown!\n", @@ -352,9 +360,8 @@ static void handle_reset_button(void) env_set_ulong("omnia_reset", reset_status); if (reset_status) { - const char * const vars[3] = { + const char * const vars[2] = { "bootcmd", - "bootcmd_rescue", "distro_bootcmd", }; @@ -362,7 +369,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(3, (char * const *)vars, 0); + env_set_default_vars(2, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); -- cgit From 864c3dbc0affea081264ff31c229232fbd45945a Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Wed, 14 Apr 2021 12:33:58 +0200 Subject: ls1012a: net: pfe: remove pfe stop from bootcmd When using bootefi to boot a EFI binary, u-boot is supposed to provide networking service for EFI application. Currently, 'pfe stop' command is called from bootcmd before running bootefi. As a result network stops working for EFI applications and console is flooded with "Rx pkt not on expected port" messages. Implement board_quiesce_devices() for ls1012a boards and call pfe_command_stop() from it instead of calling 'pfe stop' from *_bootcmd and bootcmd. Tested-by: Anji Jagarlmudi Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Ramon Fried [Fixed checkpatch space error] Signed-off-by: Priyanka Jain --- board/freescale/ls1012afrdm/ls1012afrdm.c | 8 ++++++++ board/freescale/ls1012aqds/ls1012aqds.c | 8 ++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 8 ++++++++ 3 files changed, 24 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 2cd651b943f..6473ee05728 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -23,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -185,6 +186,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + int ft_board_setup(void *blob, struct bd_info *bd) { arch_fixup_fdt(blob); diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index cfe3f3360cd..33a0910a198 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -32,6 +32,7 @@ #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -163,6 +164,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + int esdhc_status_fixup(void *blob, const char *compat) { char esdhc0_path[] = "/soc/esdhc@1560000"; diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 41bcf6f935e..62e8af48cf1 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -186,6 +187,13 @@ int board_init(void) return 0; } +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + #ifdef CONFIG_TARGET_LS1012ARDB int esdhc_status_fixup(void *blob, const char *compat) { -- cgit From c0eeb730f8038565a168a73f74b3ed56d8eac16c Mon Sep 17 00:00:00 2001 From: Priyanka Singh Date: Mon, 19 Apr 2021 11:15:04 +0530 Subject: board: freescale: vid.c: Add check for return value of adjust_vdd() Add check for return value of adjust_vdd() Signed-off-by: Biwen Li Signed-off-by: Priyanka Singh Reviewed-by: Priyanka Jain --- board/freescale/common/vid.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'board') diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6e8296293b8..13ef101e7fb 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-21 NXP * Copyright 2020 Stephen Carlson */ @@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp, char *const argv[]) { ulong override; + int ret = 0; if (argc < 2) return CMD_RET_USAGE; - if (!strict_strtoul(argv[1], 10, &override)) - adjust_vdd(override); /* the value is checked by callee */ - else + if (!strict_strtoul(argv[1], 10, &override)) { + ret = adjust_vdd(override); + if (ret < 0) + return CMD_RET_FAILURE; + } else return CMD_RET_USAGE; return 0; } -- cgit From 0753603e25dff5189ff4ba397b0625cc2d9a16c3 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Fri, 4 Jun 2021 09:25:00 +0000 Subject: keymile: common: fix hexadecimal env variable format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit df86d32 breaks linux kernel and product application boot. Linux kernel and our product application scripts are expecting 0x prefix for hexadecimal values, while env_set_hex writes them without a prefix. This patch partially revert env_set_hex usage for affected env variables. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/common/common.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 2ce7462c56f..016806a2a6c 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -46,12 +46,14 @@ int set_km_env(void) unsigned int pram; unsigned int varaddr; unsigned int kernelmem; - char *p; unsigned long rootfssize = 0; + char envval[16]; + char *p; pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; - env_set_hex("pnvramaddr", pnvramaddr); + sprintf(envval, "0x%x", pnvramaddr); + env_set("pnvramaddr", envval); /* try to read rootfssize (ram image) from environment */ p = env_get("rootfssize"); @@ -64,9 +66,12 @@ int set_km_env(void) varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); + sprintf(envval, "0x%x", varaddr); + env_set("varaddr", envval); kernelmem = gd->ram_size - 0x400 * pram; - env_set_hex("kernelmem", kernelmem); + sprintf(envval, "0x%x", kernelmem); + env_set("kernelmem", envval); return 0; } -- cgit From 0eb946ec28251272f297fcec566b9392bdad2ec6 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:36:58 +0530 Subject: board: freescale: t4rdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for t4rdb board. Signed-off-by: Priyanka Jain --- board/freescale/t4rdb/MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS index 4ba5c3a546a..7380408aaec 100644 --- a/board/freescale/t4rdb/MAINTAINERS +++ b/board/freescale/t4rdb/MAINTAINERS @@ -1,6 +1,6 @@ T4RDB BOARD -#M: Chunhe Lan -S: Orphan (since 2018-05) +M: Priyanka Jain +S: Maintained F: board/freescale/t4rdb/ F: include/configs/T4240RDB.h F: configs/T4160RDB_defconfig -- cgit From 6d1657b998f761ecdac50a259f61f554a6337a58 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:36:59 +0530 Subject: board: freescale: p1_p2_rdb_pc: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for p1_p2_rdb_pc board. Signed-off-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index b737b09b093..0004d717d1d 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -1,5 +1,5 @@ P1_P2_RDB_PC BOARD -#M: - +M: Priyanka Jain S: Maintained F: board/freescale/p1_p2_rdb_pc/ F: include/configs/p1_p2_rdb_pc.h -- cgit From eccf98f8d85d4c4928b8e5656124b2527ba259d1 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:37:00 +0530 Subject: board: freescale: p2041rdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for p2041rdb board. Signed-off-by: Priyanka Jain --- board/freescale/p2041rdb/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS index d93cb0bebb6..2121243e148 100644 --- a/board/freescale/p2041rdb/MAINTAINERS +++ b/board/freescale/p2041rdb/MAINTAINERS @@ -1,5 +1,5 @@ P2041RDB BOARD -#M: - +M: Priyanka Jain S: Maintained F: board/freescale/p2041rdb/ F: include/configs/P2041RDB.h -- cgit From 0b036d4c1b685aa73b58167e942dc6bff43e3a10 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Jun 2021 13:37:01 +0530 Subject: board: freescale: t102xrdb: Add MAINTAINER Add "Priyanka Jain " as MAINTAINER for t102xrdb board. Signed-off-by: Priyanka Jain --- board/freescale/t102xrdb/MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS index ebb17b81313..471ea07d3ca 100644 --- a/board/freescale/t102xrdb/MAINTAINERS +++ b/board/freescale/t102xrdb/MAINTAINERS @@ -1,6 +1,6 @@ T102XRDB BOARD -#M: Shengzhou Liu -S: Orphan (since 2018-05) +M: Priyanka Jain +S: Maintained F: board/freescale/t102xrdb/ F: include/configs/T102xRDB.h F: configs/T1024RDB_defconfig -- cgit From a7fd6fa1c277ed667d61de4e366fe034def4800a Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:16:28 +0000 Subject: board/km: add support for expu1 design based on nxp The EXPU1 design is a new 40G capable ethernet service unit card for Hitachi-Powergrids wired-com product lines. The base SoC is same as for already added SELI8 card, consequently the already added u-boot support for SELI8 is reused. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski [Fixed new line error at EOF] Signed-off-by: Priyanka Jain --- board/keymile/Kconfig | 7 ++++++ board/keymile/pg-wcom-ls102xa/Kconfig | 20 +++++++++++++++++ board/keymile/pg-wcom-ls102xa/MAINTAINERS | 3 +++ board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 29 ++++++++++++++++++------- 4 files changed, 51 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 86a667067de..3a6c63b774f 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -64,6 +64,13 @@ config SYS_PAX_BASE help IFC Base Address for PAXx FPGA. +config SYS_CLIPS_BASE + hex "CLIPS IFC Base Address" + default 0x78000000 + depends on ARCH_LS1021A + help + IFC Base Address for CLIPS FPGA. + config KM_CONSOLE_TTY string "KM Console" default "ttyS0" diff --git a/board/keymile/pg-wcom-ls102xa/Kconfig b/board/keymile/pg-wcom-ls102xa/Kconfig index 15c009dbe8a..f0b5ceabb69 100644 --- a/board/keymile/pg-wcom-ls102xa/Kconfig +++ b/board/keymile/pg-wcom-ls102xa/Kconfig @@ -17,3 +17,23 @@ config BOARD_SPECIFIC_OPTIONS imply FS_CRAMFS endif + +if TARGET_PG_WCOM_EXPU1 + +config SYS_BOARD + default "pg-wcom-ls102xa" + +config SYS_VENDOR + default "keymile" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "pg-wcom-expu1" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + imply FS_CRAMFS + +endif diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index e1bc90a7e65..26b202316ce 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -6,5 +6,8 @@ S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: include/configs/km/pg-wcom-ls102xa.h F: include/configs/pg-wcom-seli8.h +F: include/configs/pg-wcom-expu1.h F: configs/pg_wcom_seli8_defconfig +F: configs/pg_wcom_expu1_defconfig F: arch/arm/dts/ls1021a-pg-wcom-seli8.dts +F: arch/arm/dts/ls1021a-pg-wcom-expu1.dts diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 6b0e9631b3f..69b5d211ba2 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -70,16 +70,29 @@ int board_early_init_f(void) /* QRIO Configuration */ qrio_uprstreq(UPREQ_CORE_RST); - if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) { - qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_wdmask(KM_LIU_RST, true); +#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8) + qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_LIU_RST, true); - qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_wdmask(KM_PAXK_RST, true); + qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(KM_PAXK_RST, true); +#endif - qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prst(KM_DBG_ETH_RST, false, false); - } +#if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1) + qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(WCOM_TMG_RST, true); + + qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(WCOM_PHY_RST, false, false); + + qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_wdmask(WCOM_QSFP_RST, true); + + qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST); + qrio_prst(WCOM_CLIPS_RST, false, false); +#endif + qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); + qrio_prst(KM_DBG_ETH_RST, false, false); i2c_deblock_gpio_cfg(); -- cgit From 3aea3ddf21a29145176189b55eca7a833b8f7a4d Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:17:34 +0000 Subject: km/ls102xa: add support for u-boot POST memory test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From production view this is standard test executed during production on all linux based foxmc cards. On CENT2 HW defined memory region is zero means that some DDR accesses are done by memory_post_dataline and memory_post_addrline but pattern tests are skipped that's why mem_regions is fast there. On ls102x for the complete DDR region of 1GiB memory_regions_post_test takes approx. 4min and this is too much for production, so this patch defines only 1MiB region as compromise. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'board') diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 69b5d211ba2..97915f94c40 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -141,6 +141,40 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +#if defined(CONFIG_POST) +int post_hotkeys_pressed(void) +{ + /* DIC26_SELFTEST: GPRTA0, GPA0 */ + qrio_gpio_direction_input(QRIO_GPIO_A, 0); + return qrio_get_gpio(QRIO_GPIO_A, 0); +} + +ulong post_word_load(void) +{ + /* POST word is located at the beginning of reserved physical RAM */ + void *addr = (void *)(CONFIG_SYS_SDRAM_BASE + + gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8); + return in_le32(addr); +} + +void post_word_store(ulong value) +{ + /* POST word is located at the beginning of reserved physical RAM */ + void *addr = (void *)(CONFIG_SYS_SDRAM_BASE + + gd->ram_size - CONFIG_KM_RESERVED_PRAM + 8); + out_le32(addr, value); +} + +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + /* Define only 1MiB range for mem_regions at the middle of the RAM */ + /* For 1GiB range mem_regions takes approx. 4min */ + *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); + *size = 1 << 20; + return 0; +} +#endif + u8 flash_read8(void *addr) { return __raw_readb(addr + 1); -- cgit From fbb0e15a42e816e4b81b96d5c4d1303584afe1c0 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:20:13 +0000 Subject: km/scripts: fix saveenv command syntax This is most probably a typo, and in older u-uboot versions is same as 'saveenv', in the newer uboot versions there is a separate 'save' command that is different from 'saveenv'. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/scripts/ramfs-common.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index e590a2bee6a..0a4a9c80b7e 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -3,7 +3,7 @@ boot_bank=-1 altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot -save_and_reset_once=setenv save_and_reset_once true && save && reset +save_and_reset_once=setenv save_and_reset_once true && saveenv && reset nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_rootfssize && saveenv && reset setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} -- cgit From 02802eb89e85696d9cd2276c2842255d5ad7edf6 Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Tue, 8 Jun 2021 14:24:32 +0000 Subject: pg-wcom-ls102x: initialize front led and app buf This patch adds the front led initialization and the application buffer enable to the eraly board inititlaization. Signed-off-by: Rainer Boschung Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board') diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 97915f94c40..db49e8ff225 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -96,6 +96,12 @@ int board_early_init_f(void) i2c_deblock_gpio_cfg(); + /* enable the Unit LED (red) & Boot LED (on) */ + qrio_set_leds(); + + /* enable Application Buffer */ + qrio_enable_app_buffer(); + arch_soc_init(); return 0; -- cgit From a484f7c4869723451c1ca98e8b2e9dbee0e8ff16 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:05 +0300 Subject: board: freescale: t208xrdb: remove the legacy non-DM_ETH code Both DM_ETH and DM_PCI are enabled for the T2080RDB board. Remove the board_eth_init() callback and the non-DM_ETH code paths since they are not needed anymore. Signed-off-by: Camelia Groza Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/eth_t208xrdb.c | 79 --------------------------------- board/freescale/t208xrdb/t208xrdb.c | 4 -- 2 files changed, 83 deletions(-) (limited to 'board') diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index b0ff4b1f375..4b44b1617d6 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -26,85 +26,6 @@ #include #include -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x66: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); - fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); - fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); - break; - default: - printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - /* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two * "fsl,dpa-ethernet" nodes that reference them. */ diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 7ccb205c647..35f5dff4664 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -136,11 +136,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fsl_fdt_fixup_dr_usb(blob, bd); #ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#else fdt_fixup_board_fman_ethernet(blob); -#endif fdt_fixup_board_enet(blob); #endif -- cgit From c91b1305547ee72c0b0e5995c3b47d2b56ad698f Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:06 +0300 Subject: board: freescale: t208xrdb: detect the board revision version Detect and print the board revision version based on the CPLD registers. Signed-off-by: Camelia Groza Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/t208xrdb.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 35f5dff4664..f7fa65d1a16 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -27,14 +27,29 @@ DECLARE_GLOBAL_DATA_PTR; +u8 get_hw_revision(void) +{ + u8 ver = CPLD_READ(hw_ver); + + switch (ver) { + default: + case 0x1: + return 'C'; + case 0x0: + return 'D'; + case 0x2: + return 'E'; + } +} + int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", - CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + printf("Board rev: %c CPLD ver: 0x%02x, boot from ", + get_hw_revision(), CPLD_READ(sw_ver)); #ifdef CONFIG_SDCARD puts("SD/MMC\n"); -- cgit From 4e21a555c1dc2eacee9e3ad07f3b112c20b0f7a2 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Wed, 16 Jun 2021 17:47:31 +0530 Subject: board: freescale: t208xrdb: add Linux fdt fix-ups for rev D The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs connected to MAC1 and MAC2. The second Aquantia PHY is located at a different address on the MDIO bus compared to rev C (0x8 instead of 0x1). Fix-up the Linux device tree to update the PHY address for the second Aquantia PHY on boards revisions D and up. Also rename the PHY node to reflect the changes. Signed-off-by: Camelia Groza [Rebased] Signed-off-by: Priyanka Jain --- board/freescale/t208xrdb/eth_t208xrdb.c | 35 +++++++++++++++++++++++++++++++++ board/freescale/t208xrdb/t208xrdb.c | 1 + board/freescale/t208xrdb/t208xrdb.h | 1 + 3 files changed, 37 insertions(+) (limited to 'board') diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index 4b44b1617d6..e4592eac153 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -26,6 +26,8 @@ #include #include +extern u8 get_hw_revision(void); + /* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two * "fsl,dpa-ethernet" nodes that reference them. */ @@ -60,6 +62,39 @@ void fdt_fixup_board_fman_ethernet(void *fdt) } } +/* Update the address of the second Aquantia PHY on boards revision D and up. + * Also rename the PHY node to align with the address change. + */ +void fdt_fixup_board_phy(void *fdt) +{ + const char phy_path[] = + "/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1"; + int ret, offset, new_addr = AQR113C_PHY_ADDR2; + char new_name[] = "ethernet-phy@00"; + + if (get_hw_revision() == 'C') + return; + + offset = fdt_path_offset(fdt, phy_path); + if (offset < 0) { + printf("ethernet-phy@1 node not found in the dts\n"); + return; + } + + ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr)); + if (ret < 0) { + printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", + fdt_strerror(ret)); + return; + } + + sprintf(new_name, "ethernet-phy@%x", new_addr); + ret = fdt_set_name(fdt, offset, new_name); + if (ret < 0) + printf("Unable to rename node ethernet-phy@1: %s\n", + fdt_strerror(ret)); +} + void fdt_fixup_board_enet(void *fdt) { return; diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index f7fa65d1a16..1f0cdee0b86 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -153,6 +153,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); fdt_fixup_board_enet(blob); + fdt_fixup_board_phy(blob); #endif return 0; diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h index cd0a9f44da7..edbc860c9d0 100644 --- a/board/freescale/t208xrdb/t208xrdb.h +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -10,5 +10,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); +void fdt_fixup_board_phy(void *blob); #endif -- cgit From 13ea307f799ba76164354325a0c76c11b7b9c494 Mon Sep 17 00:00:00 2001 From: Camelia Groza Date: Fri, 11 Jun 2021 15:28:08 +0300 Subject: board: freescale: t208xrdb: add a config option for rev D dts fixups Under DM, we rely on u-boot's device tree to provide the correct PHY addresses. The board_fix_fdt callback is intended to be used for device tree fixups before relocation. Unfortunately, this isn't an option when booting from flash since the device tree isn't writable before relocation. This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a board revision D or up is the target. The config option is used to set the correct Aquantia PHY address in the board's u-boot device tree. Defconfig files with the option enable explicitly are added for convenience. Signed-off-by: Camelia Groza Reviewed-by: Priyanka Jain --- board/freescale/t208xrdb/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig index 6f0b012baba..8249c5df967 100644 --- a/board/freescale/t208xrdb/Kconfig +++ b/board/freescale/t208xrdb/Kconfig @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "T208xRDB" +config T2080RDB_REV_D + bool "Support for T2080RDB revisions D and up" + default n + source "board/freescale/common/Kconfig" endif -- cgit From b7efcaff8bb5196b9271bcfaeb0a5f100b3867c2 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Thu, 17 Jun 2021 12:52:46 +0530 Subject: board: freescale: t1028xrdb: Add MAINTAINER for revD Add Priyanka Jain as MAINTAINER for T2080RDB_revD_defconfig, T2080RDB_revD_NAND_defconfig, T2080RDB_revD_SDCARD_defconfig and T2080RDB_revD_SPIFLASH_defconfig Signed-off-by: Priyanka Jain --- board/freescale/t208xrdb/MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS index f894f77b735..6e9b25fa049 100644 --- a/board/freescale/t208xrdb/MAINTAINERS +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -8,6 +8,10 @@ F: configs/T2080RDB_NAND_defconfig F: configs/T2080RDB_SDCARD_defconfig F: configs/T2080RDB_SPIFLASH_defconfig F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +F: configs/T2080RDB_revD_defconfig +F: configs/T2080RDB_revD_NAND_defconfig +F: configs/T2080RDB_revD_SDCARD_defconfig +F: configs/T2080RDB_revD_SPIFLASH_defconfig T2080RDB_SECURE_BOOT BOARD M: Ruchika Gupta -- cgit