From 0ce3639d6f612d3fc215474a45075717d4e7aaa8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 11 Jun 2020 10:53:49 +0200 Subject: board: amlogic: move boards doc into doc/board/amlogic Move the natural text Amlogic board README files to doc/board/amlogic into reStructuredText and : - add reStructuredText markup for bash code - fix secondary titles markup - move board support into global support matrix Signed-off-by: Neil Armstrong --- board/amlogic/p200/README.nanopi-k2 | 98 ------------------------ board/amlogic/p200/README.odroid-c2 | 65 ---------------- board/amlogic/p200/README.p200 | 102 ------------------------- board/amlogic/p201/README.p201 | 102 ------------------------- board/amlogic/p212/README.khadas-vim | 101 ------------------------- board/amlogic/p212/README.libretech-ac | 102 ------------------------- board/amlogic/p212/README.libretech-cc | 134 --------------------------------- board/amlogic/p212/README.p212 | 102 ------------------------- board/amlogic/q200/README.khadas-vim2 | 102 ------------------------- board/amlogic/q200/README.q200 | 101 ------------------------- board/amlogic/s400/README | 109 --------------------------- board/amlogic/sei510/README | 122 ------------------------------ board/amlogic/sei610/README | 118 ----------------------------- board/amlogic/u200/README | 127 ------------------------------- board/amlogic/w400/README.khadas-vim3 | 131 -------------------------------- board/amlogic/w400/README.khadas-vim3l | 131 -------------------------------- board/amlogic/w400/README.odroid-n2 | 129 ------------------------------- board/amlogic/w400/README.w400 | 129 ------------------------------- 18 files changed, 2005 deletions(-) delete mode 100644 board/amlogic/p200/README.nanopi-k2 delete mode 100644 board/amlogic/p200/README.odroid-c2 delete mode 100644 board/amlogic/p200/README.p200 delete mode 100644 board/amlogic/p201/README.p201 delete mode 100644 board/amlogic/p212/README.khadas-vim delete mode 100644 board/amlogic/p212/README.libretech-ac delete mode 100644 board/amlogic/p212/README.libretech-cc delete mode 100644 board/amlogic/p212/README.p212 delete mode 100644 board/amlogic/q200/README.khadas-vim2 delete mode 100644 board/amlogic/q200/README.q200 delete mode 100644 board/amlogic/s400/README delete mode 100644 board/amlogic/sei510/README delete mode 100644 board/amlogic/sei610/README delete mode 100644 board/amlogic/u200/README delete mode 100644 board/amlogic/w400/README.khadas-vim3 delete mode 100644 board/amlogic/w400/README.khadas-vim3l delete mode 100644 board/amlogic/w400/README.odroid-n2 delete mode 100644 board/amlogic/w400/README.w400 (limited to 'board') diff --git a/board/amlogic/p200/README.nanopi-k2 b/board/amlogic/p200/README.nanopi-k2 deleted file mode 100644 index c8dec3569b4..00000000000 --- a/board/amlogic/p200/README.nanopi-k2 +++ /dev/null @@ -1,98 +0,0 @@ -U-Boot for NanoPi-K2 -==================== - -NanoPi-K2 is a single board computer manufactured by FriendlyElec -with the following specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make nanopi-k2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot - > cd amlogic-u-boot - > sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile - > sed -i 's/arm-linux-/arm-none-eabi-/' arch/arm/cpu/armv8/gxb/firmware/scp_task/Makefile - > make nanopi-k2_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxb/bl2.bin fip/ - > cp $FIPDIR/gxb/acs.bin fip/ - > cp $FIPDIR/gxb/bl21.bin fip/ - > cp $FIPDIR/gxb/bl30.bin fip/ - > cp $FIPDIR/gxb/bl301.bin fip/ - > cp $FIPDIR/gxb/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/fip_create \ - --bl30 fip/bl30_new.bin \ - --bl31 fip/bl31.img \ - --bl33 fip/bl33.bin \ - fip/fip.bin - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin - - > $FIPDIR/gxb/aml_encrypt_gxb --bootsig \ - --input fip/boot_new.bin - --output fip/u-boot.bin - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1 diff --git a/board/amlogic/p200/README.odroid-c2 b/board/amlogic/p200/README.odroid-c2 deleted file mode 100644 index 3b9f80df29d..00000000000 --- a/board/amlogic/p200/README.odroid-c2 +++ /dev/null @@ -1,65 +0,0 @@ -U-Boot for ODROID-C2 -==================== - -ODROID-C2 is a single board computer manufactured by Hardkernel -Co. Ltd with the following specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make odroid-c2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > DIR=odroid-c2 - > git clone --depth 1 \ - https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \ - $DIR - > $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \ - --bl301 $DIR/fip/gxb/bl301.bin \ - --bl31 $DIR/fip/gxb/bl31.bin \ - --bl33 u-boot.bin \ - $DIR/fip.bin - > $DIR/fip/fip_create --dump $DIR/fip.bin - > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin - > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \ - --input $DIR/boot_new.bin \ - --output $DIR/u-boot.img - > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > BL1=$DIR/sd_fuse/bl1.bin.hardkernel - > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442 - > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1 - > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97 diff --git a/board/amlogic/p200/README.p200 b/board/amlogic/p200/README.p200 deleted file mode 100644 index 84d5ca53569..00000000000 --- a/board/amlogic/p200/README.p200 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P200 -======================= - -P200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - Gigabit Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p200_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxb_p200_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201 deleted file mode 100644 index 4bb5e959053..00000000000 --- a/board/amlogic/p201/README.p201 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P201 -======================= - -P201 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p201_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxb_p201_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.khadas-vim b/board/amlogic/p212/README.khadas-vim deleted file mode 100644 index ccf933861b7..00000000000 --- a/board/amlogic/p212/README.khadas-vim +++ /dev/null @@ -1,101 +0,0 @@ -U-Boot for Khadas VIM -======================= - -Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion -Technology Co., Ltd with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG - - 8GB/16GBeMMC - - microSD - - SDIO Wifi Module, Bluetooth - - Two channels IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot - > cd vim-u-boot - > make kvim_defconfig - > make CROSS_COMPILE=aarch64-none-elf- - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.libretech-ac b/board/amlogic/p212/README.libretech-ac deleted file mode 100644 index 3f713ec3263..00000000000 --- a/board/amlogic/p212/README.libretech-ac +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for LibreTech AC -======================= - -LibreTech AC is a single board computer manufactured by Libre Technology -with the following specifications: - - - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz - - ARM Mali 450 GPU - - 512MiB DDR4 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host - - eMMC, SPI NOR Flash - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC - - Ethernet - - USB - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make libretech-ac_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot - > cd amlogic-u-boot - > wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh - > make libretech_ac_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418 - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > sh $UBOOTDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > sh $UBOOTDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p212/README.libretech-cc b/board/amlogic/p212/README.libretech-cc deleted file mode 100644 index 74434d4435e..00000000000 --- a/board/amlogic/p212/README.libretech-cc +++ /dev/null @@ -1,134 +0,0 @@ -U-Boot for LibreTech CC -======================= - -LibreTech CC is a single board computer manufactured by Libre Technology -with the following specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make libretech-cc_defconfig - > make - -Image creation -============== - -To boot the system, u-boot must be combined with several earlier stage -bootloaders: - -* bl2.bin: vendor-provided binary blob -* bl21.bin: built from vendor u-boot source -* bl30.bin: vendor-provided binary blob -* bl301.bin: built from vendor u-boot source -* bl31.bin: vendor-provided binary blob -* acs.bin: built from vendor u-boot source - -These binaries and the tools required below have been collected and prebuilt -for convenience at - -Download and extract the libretech-cc release from there, and set FIPDIR to -point to the `fip` subdirectory. - - > export FIPDIR=/path/to/extracted/fip - -Alternatively, you can obtain the original vendor u-boot tree which -contains the required blobs and sources, and build yourself. -Note that old compilers are required for this to build. The compilers here -are suggested by Amlogic, and they are 32-bit x86 binaries. - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot - > cd amlogic-u-boot - > make libretech_cc_defconfig - > make - > export FIPDIR=$PWD/fip - -Once you have the binaries available (either through the prebuilt download, -or having built the vendor u-boot yourself), you can then proceed to glue -everything together. Go back to mainline U-Boot source tree then : - - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 - -Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no -source code. Should you prefer to avoid that, there are open source reverse -engineered versions available: - -1. gxlimg , which comes with a handy - Makefile that automates the whole process. -2. meson-tools - -However, these community-developed alternatives are not endorsed by or -supported by Amlogic. diff --git a/board/amlogic/p212/README.p212 b/board/amlogic/p212/README.p212 deleted file mode 100644 index 3776f244939..00000000000 --- a/board/amlogic/p212/README.p212 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Amlogic P212 -======================= - -P212 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz - - ARM Mali 450 GPU - - 2GB DDR3 SDRAM - - 10/100 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host - - eMMC, microSD - - Infrared receiver - - SDIO WiFi Module - - CVBS+Stereo Audio Jack - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make p212_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxl_p212_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/q200/README.khadas-vim2 b/board/amlogic/q200/README.khadas-vim2 deleted file mode 100644 index 595998c4fab..00000000000 --- a/board/amlogic/q200/README.khadas-vim2 +++ /dev/null @@ -1,102 +0,0 @@ -U-Boot for Khadas VIM2 -======================= - -Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion -Technology Co., Ltd with the following specifications: - - - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz - - ARM Mali T860 GPU - - 2/3GB DDR4 SDRAM - - 10/100/1000 Ethernet - - HDMI 2.0 4K/60Hz display - - 40-pin GPIO header - - 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG - - 16GB/32GB/64GB eMMC - - 2MB SPI Flash - - microSD - - SDIO Wifi Module, Bluetooth - - Two channels IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot - > cd vim-u-boot - > make kvim2_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/q200/README.q200 b/board/amlogic/q200/README.q200 deleted file mode 100644 index d4142c88bd4..00000000000 --- a/board/amlogic/q200/README.q200 +++ /dev/null @@ -1,101 +0,0 @@ -U-Boot for Amlogic Q200 -======================= - -Q200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz - - ARM Mali T860 GPU - - 2/3GB DDR4 SDRAM - - 10/100/1000 Ethernet - - HDMI 2.0 4K/60Hz display - - 2 x USB 2.0 Host, 1 x USB 2.0 Device - - 16GB/32GB/64GB eMMC - - 2MB SPI Flash - - microSD - - SDIO Wifi Module, Bluetooth - - IR receiver - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -U-Boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make gxm_q200_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $FIPDIR/gxl/bl2.bin fip/ - > cp $FIPDIR/gxl/acs.bin fip/ - > cp $FIPDIR/gxl/bl21.bin fip/ - > cp $FIPDIR/gxl/bl30.bin fip/ - > cp $FIPDIR/gxl/bl301.bin fip/ - > cp $FIPDIR/gxl/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/s400/README b/board/amlogic/s400/README deleted file mode 100644 index a48db22a428..00000000000 --- a/board/amlogic/s400/README +++ /dev/null @@ -1,109 +0,0 @@ -U-Boot for Amlogic S400 -======================= - -S400 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz - - 1GB DDR4 SDRAM - - 10/100 Ethernet - - 2 x USB 2.0 Host - - eMMC - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connectors - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - eMMC - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - USB Host - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make s400_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot - > cd amlogic-u-boot - > make axg_s400_v1_defconfig - > make - > export FIPDIR=$PWD/fip - -Go back to mainline U-boot source tree then : - > mkdir fip - - > cp $FIPDIR/axg/bl2.bin fip/ - > cp $FIPDIR/axg/acs.bin fip/ - > cp $FIPDIR/axg/bl21.bin fip/ - > cp $FIPDIR/axg/bl30.bin fip/ - > cp $FIPDIR/axg/bl301.bin fip/ - > cp $FIPDIR/axg/bl31.img fip/ - > cp u-boot.bin fip/bl33.bin - - > $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - - > $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/axg/aml_encrypt_axg --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/sei510/README b/board/amlogic/sei510/README deleted file mode 100644 index d9358aa5018..00000000000 --- a/board/amlogic/sei510/README +++ /dev/null @@ -1,122 +0,0 @@ -U-Boot for Amlogic SEI510 -======================= - -SEI510 is a customer board manufactured by SEI Robotics with the following -specifications: - - - Amlogic S905X2 ARM Cortex-A53 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make sei510_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12a_u200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/sei610/README b/board/amlogic/sei610/README deleted file mode 100644 index d96a94b5e97..00000000000 --- a/board/amlogic/sei610/README +++ /dev/null @@ -1,118 +0,0 @@ -U-Boot for Amlogic SEI610 -========================= - -SEI610 is a customer board manufactured by SEI Robotics with the following -specifications: - - - Amlogic S905X3 ARM Cortex-A55 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - 1 x USB Type-C DRD - - 1 x FTDI USB Serial Debug Interface - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make sei610_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-4.9-g12a-201904 amlogic-u-boot - > cd amlogic-u-boot - > make sm1_ac200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/buildroot-openlinux-A113-201901.tgz - > tar xfz buildroot-openlinux-A113-201901.tgz buildroot-openlinux-A113-201901/bootloader - > export BRDIR=$PWD/buildroot-openlinux-A113-201901 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README deleted file mode 100644 index a4080eb299c..00000000000 --- a/board/amlogic/u200/README +++ /dev/null @@ -1,127 +0,0 @@ -U-Boot for Amlogic U200 -======================= - -U200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S905D2 ARM Cortex-A53 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connector - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make u200_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12a_u200_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ - > cp $FIPDIR/g12a/ddr3_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_1d.fw fip/ - > cp $FIPDIR/g12a/ddr4_2d.fw fip/ - > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12a/piei.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.khadas-vim3 b/board/amlogic/w400/README.khadas-vim3 deleted file mode 100644 index 399bf49295f..00000000000 --- a/board/amlogic/w400/README.khadas-vim3 +++ /dev/null @@ -1,131 +0,0 @@ -U-Boot for Khadas VIM3 -====================== - -Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion -Technology Co., Ltd. with the following specifications: - - - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 4GB LPDDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 display - - 40-pin GPIO header - - 1 x USB 3.0 Host, 1 x USB 2.0 Host - - eMMC, microSD - - M.2 - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim3_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=vim3-u-boot - > git clone --depth 1 \ - https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ - $DIR - - > cd vim3-u-boot - > make kvim3_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/khadas/kvim3/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl31.img fip/ - > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/piei.fw fip/ - > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --ddrfw9 fip/lpddr3_1d.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.khadas-vim3l b/board/amlogic/w400/README.khadas-vim3l deleted file mode 100644 index b2d9abbfd9b..00000000000 --- a/board/amlogic/w400/README.khadas-vim3l +++ /dev/null @@ -1,131 +0,0 @@ -U-Boot for Khadas VIM3L -======================= - -Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion -Technology Co., Ltd. with the following specifications: - - - Amlogic S905D3 Arm Cortex-A55 quad-core SoC - - 2GB LPDDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 display - - 40-pin GPIO header - - 1 x USB 3.0 Host, 1 x USB 2.0 Host - - eMMC, microSD - - M.2 - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the U-Boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make khadas-vim3l_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=vim3l-u-boot - > git clone --depth 1 \ - https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \ - $DIR - - > cd vim3l-u-boot - > make kvim3l_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/khadas/kvim3l/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12a/bl31.img fip/ - > cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12a/piei.fw fip/ - > cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --ddrfw9 fip/lpddr3_1d.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.odroid-n2 b/board/amlogic/w400/README.odroid-n2 deleted file mode 100644 index 8142eebea00..00000000000 --- a/board/amlogic/w400/README.odroid-n2 +++ /dev/null @@ -1,129 +0,0 @@ -U-Boot for ODROID-N2 -==================== - -ODROID-N2 is a single board computer manufactured by Hardkernel -Co. Ltd with the following specifications: - - - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 4GB DDR4 SDRAM - - Gigabit Ethernet - - HDMI 2.1 4K/60Hz display - - 40-pin GPIO header - - 4 x USB 3.0 Host, 1 x USB OTG - - eMMC, microSD - - Infrared receiver - -Schematics are available on the manufacturer website. - -Currently the u-boot port supports the following devices: - - serial - - eMMC, microSD - - Ethernet - - I2C - - Regulators - - Reset controller - - Clock controller - - ADC - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make odroid-n2_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - - > DIR=odroid-n2 - > git clone --depth 1 \ - https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \ - $DIR - - > cd odroid-n2 - > make odroidn2_defconfig - > make - > export UBOOTDIR=$PWD - - Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/hardkernel/odroidn2/firmware/acs.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl2.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl30.bin fip/ - > cp $UBOOTDIR/fip/g12b/bl31.img fip/ - > cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/ - > cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/ - > cp $UBOOTDIR/fip/g12b/piei.fw fip/ - > cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 --compress lz4 - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/w400/README.w400 b/board/amlogic/w400/README.w400 deleted file mode 100644 index c129717a118..00000000000 --- a/board/amlogic/w400/README.w400 +++ /dev/null @@ -1,129 +0,0 @@ -U-Boot for Amlogic W400 -======================= - -U200 is a reference board manufactured by Amlogic with the following -specifications: - - - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC - - 2GB DDR4 SDRAM - - 10/100 Ethernet (Internal PHY) - - 1 x USB 3.0 Host - - eMMC - - SDcard - - Infrared receiver - - SDIO WiFi Module - - MIPI DSI Connector - - Audio HAT Connector - - PCI-E M.2 Connector - -Schematics are available from Amlogic on demand. - -Currently the u-boot port supports the following devices: - - serial - - Ethernet - - Regulators - - Clock controller - -u-boot compilation -================== - - > export CROSS_COMPILE=aarch64-none-elf- - > make w400_defconfig - > make - -Image creation -============== - -Amlogic doesn't provide sources for the firmware and for tools needed -to create the bootloader image, so it is necessary to obtain them from -the git tree published by the board vendor: - - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz - > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz - > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot - > cd amlogic-u-boot - > make g12b_w400_v1_defconfig - > make - > export UBOOTDIR=$PWD - -Download the latest Amlogic Buildroot package, and extract it : - > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz - > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader - > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 - > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip - -Go back to mainline U-Boot source tree then : - > mkdir fip - - > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh - > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ - > cp $UBOOTDIR/build/board/amlogic/g12b_w400_v1/firmware/acs.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12b/bl2.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12b/bl30.bin fip/ - > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12b/bl31.img fip/ - > cp $FIPDIR/g12b/ddr3_1d.fw fip/ - > cp $FIPDIR/g12b/ddr4_1d.fw fip/ - > cp $FIPDIR/g12b/ddr4_2d.fw fip/ - > cp $FIPDIR/g12b/diag_lpddr4.fw fip/ - > cp $FIPDIR/g12b/lpddr4_1d.fw fip/ - > cp $FIPDIR/g12b/lpddr4_2d.fw fip/ - > cp $FIPDIR/g12b/piei.fw fip/ - > cp $FIPDIR/g12b/aml_ddr.fw fip/ - > cp u-boot.bin fip/bl33.bin - - > sh fip/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 - - > sh fip/blx_fix.sh \ - fip/bl2.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/acs.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - > $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \ - --output fip/bl30_new.bin.g12a.enc \ - --level v3 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \ - --output fip/bl30_new.bin.enc \ - --level v3 --type bl30 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \ - --output fip/bl31.img.enc \ - --level v3 --type bl31 - > $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \ - --output fip/bl33.bin.enc \ - --level v3 --type bl33 - > $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \ - --output fip/bl2.n.bin.sig - > $FIPDIR/g12b/aml_encrypt_g12b --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc \ - --ddrfw1 fip/ddr4_1d.fw \ - --ddrfw2 fip/ddr4_2d.fw \ - --ddrfw3 fip/ddr3_1d.fw \ - --ddrfw4 fip/piei.fw \ - --ddrfw5 fip/lpddr4_1d.fw \ - --ddrfw6 fip/lpddr4_2d.fw \ - --ddrfw7 fip/diag_lpddr4.fw \ - --ddrfw8 fip/aml_ddr.fw \ - --level v3 - -and then write the image to SD with: - - > DEV=/dev/your_sd_device - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 -- cgit From 9c55f5d11260c5aa0f91d8cb32aa0ad00910659d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 11 Jun 2020 10:57:39 +0200 Subject: board: amlogic: add board doc files to MAINTAINERS Add the recently added reStructuredText board documentation in the appropriate MAINTAINERS files. Signed-off-by: Neil Armstrong --- board/amlogic/p200/MAINTAINERS | 3 +++ board/amlogic/p201/MAINTAINERS | 1 + board/amlogic/p212/MAINTAINERS | 4 ++++ board/amlogic/q200/MAINTAINERS | 1 + board/amlogic/s400/MAINTAINERS | 1 + board/amlogic/sei510/MAINTAINERS | 1 + board/amlogic/sei610/MAINTAINERS | 1 + board/amlogic/u200/MAINTAINERS | 1 + board/amlogic/w400/MAINTAINERS | 4 ++++ 9 files changed, 17 insertions(+) (limited to 'board') diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS index c20f056af24..1df9b8b24be 100644 --- a/board/amlogic/p200/MAINTAINERS +++ b/board/amlogic/p200/MAINTAINERS @@ -7,3 +7,6 @@ F: board/amlogic/p200/ F: configs/nanopi-k2_defconfig F: configs/odroid-c2_defconfig F: configs/p200_defconfig +F: doc/board/amlogic/p200.rst +F: doc/board/amlogic/nanopi-k2.rst +F: doc/board/amlogic/odroid-c2.rst diff --git a/board/amlogic/p201/MAINTAINERS b/board/amlogic/p201/MAINTAINERS index f84984d7ab6..1501b6280da 100644 --- a/board/amlogic/p201/MAINTAINERS +++ b/board/amlogic/p201/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/p201/ F: configs/p201_defconfig +F: doc/board/amlogic/p201.rst diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index 8848df05b7c..cae6994393d 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -8,3 +8,7 @@ F: configs/khadas-vim_defconfig F: configs/libretech-ac_defconfig F: configs/libretech-cc_defconfig F: configs/p212_defconfig +F: doc/board/amlogic/p212.rst +F: doc/board/amlogic/libretech-ac.rst +F: doc/board/amlogic/libretech-cc.rst +F: doc/board/amlogic/khadas-vim.rst diff --git a/board/amlogic/q200/MAINTAINERS b/board/amlogic/q200/MAINTAINERS index 6f00f873860..ec05aa6f4c7 100644 --- a/board/amlogic/q200/MAINTAINERS +++ b/board/amlogic/q200/MAINTAINERS @@ -7,3 +7,4 @@ F: include/configs/q200.h F: configs/khadas-vim2_defconfig F: configs/libretech-s905d-pc_defconfig F: configs/libretech-s912-pc_defconfig +F: doc/board/amlogic/khadas-vim2.rst diff --git a/board/amlogic/s400/MAINTAINERS b/board/amlogic/s400/MAINTAINERS index da90cf9b6f2..fb46b1bbbf7 100644 --- a/board/amlogic/s400/MAINTAINERS +++ b/board/amlogic/s400/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/s400/ F: include/configs/s400.h F: configs/s400_defconfig +F: doc/board/amlogic/s400.rst diff --git a/board/amlogic/sei510/MAINTAINERS b/board/amlogic/sei510/MAINTAINERS index 8dc655e8cc1..c01c1d60df4 100644 --- a/board/amlogic/sei510/MAINTAINERS +++ b/board/amlogic/sei510/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/sei510/ F: configs/sei510_defconfig F: include/configs/sei510.h +F: doc/board/amlogic/sei510.rst diff --git a/board/amlogic/sei610/MAINTAINERS b/board/amlogic/sei610/MAINTAINERS index da77aafa412..092178b2c83 100644 --- a/board/amlogic/sei610/MAINTAINERS +++ b/board/amlogic/sei610/MAINTAINERS @@ -5,3 +5,4 @@ L: u-boot-amlogic@groups.io F: board/amlogic/sei610/ F: configs/sei610_defconfig F: include/configs/sei610.h +F: doc/board/amlogic/sei610.rst diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS index 5ae7f5e66a2..8c23f9a7d31 100644 --- a/board/amlogic/u200/MAINTAINERS +++ b/board/amlogic/u200/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/u200/ F: configs/u200_defconfig +F: doc/board/amlogic/u200.rst diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS index 2ff90039ca2..5e837cfaef3 100644 --- a/board/amlogic/w400/MAINTAINERS +++ b/board/amlogic/w400/MAINTAINERS @@ -6,3 +6,7 @@ F: board/amlogic/w400/ F: configs/khadas-vim3_defconfig F: configs/khadas-vim3l_defconfig F: configs/odroid-n2_defconfig +F: doc/board/amlogic/w400.rst +F: doc/board/amlogic/khadas-vim3.rst +F: doc/board/amlogic/khadas-vim3l.rst +F: doc/board/amlogic/odroid-n2.rst -- cgit From c46443dd85cb1ebb329ce733018d4a04babe2f25 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Mon, 13 Apr 2020 18:11:42 +0300 Subject: colibri_t20: change maintainer Take over maintainership for Colibri T20 module. Signed-off-by: Igor Opaniuk Acked-by: Lucas Stach --- board/toradex/colibri_t20/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS index b251c000fe0..2a8e6fb74b7 100644 --- a/board/toradex/colibri_t20/MAINTAINERS +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -1,5 +1,5 @@ COLIBRI_T20 -M: Lucas Stach +M: Igor Opaniuk S: Maintained F: board/toradex/colibri_t20/ F: include/configs/colibri_t20.h -- cgit From d8da22c5dbdc7bc61b575278ea0e02919ffbe734 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 18 Jun 2020 20:21:20 -0300 Subject: mx6cuboxi: Convert to DM_ETH Migration to DM_ETH is mandatory, so convert mx6cuboxi to Ethernet Driver Model. This also brings the benefit of restoring Ethernet functionality. Reported-by: Tom Rini Signed-off-by: Fabio Estevam Tested-by: Tom Rini --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 +++++------------------------------ 1 file changed, 17 insertions(+), 117 deletions(-) (limited to 'board') diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 94707bccb26..59e8b1dca1d 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -33,8 +32,6 @@ #include #include #include -#include -#include #include #include #include @@ -52,16 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) #define USB_H1_VBUS IMX_GPIO_NR(1, 0) enum board_type { @@ -237,110 +224,6 @@ int board_mmc_init(bd_t *bis) return 0; } -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* AR8035 reset */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - /* AR8035 interrupt */ - IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), - /* GPIO16 -> AR8035 25MHz */ - IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), - IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), -}; - -static void setup_iomux_enet(void) -{ - struct gpio_desc desc; - int ret; - - SETUP_IOMUX_PADS(enet_pads); - - ret = dm_gpio_lookup_name("GPIO4_15", &desc); - if (ret) { - printf("%s: phy reset lookup failed\n", __func__); - return; - } - - ret = dm_gpio_request(&desc, "phy-reset"); - if (ret) { - printf("%s: phy reset request failed\n", __func__); - return; - } - - gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(10); - gpio_set_value(ETH_PHY_RESET, 1); - udelay(100); - - gpio_free_list_nodev(&desc, 1); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -/* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */ -#define ETH_PHY_MASK ((1 << 0x0) | (1 << 0x4)) - -int board_eth_init(bd_t *bis) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mii_dev *bus; - struct phy_device *phydev; - - int ret = enable_fec_anatop_clock(0, ENET_25MHZ); - if (ret) - return ret; - - /* set gpr1[ENET_CLK_SEL] */ - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - - setup_iomux_enet(); - - bus = fec_get_miibus(IMX_FEC_BASE, -1); - if (!bus) - return -EINVAL; - - phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); - if (!phydev) { - ret = -EINVAL; - goto free_bus; - } - - debug("using phy at address %d\n", phydev->addr); - ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); - if (ret) - goto free_phydev; - - return 0; - -free_phydev: - free(phydev); -free_bus: - free(bus); - return ret; -} - #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { @@ -433,6 +316,21 @@ static int setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + ret = enable_fec_anatop_clock(0, ENET_25MHZ); + if (ret) + return ret; + + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -440,6 +338,8 @@ int board_early_init_f(void) #ifdef CONFIG_CMD_SATA setup_sata(); #endif + setup_fec(); + return 0; } -- cgit From f7ac30b042dc9c9383e102fb54431c664c281d0d Mon Sep 17 00:00:00 2001 From: Martyn Welch Date: Thu, 11 Jun 2020 18:53:50 +0100 Subject: Fix MMC access on Sabrelite It appears that MMC access on the Sabrelite has been broken since cdcaee9518: Loading Environment from MMC... Card did not respond to voltage select! *** Warning - No block device, using default environment Remove the board_mmc_init() and related entries now that we should be using DM_MMC, add PINCTRL so that things work as expected. Signed-off-by: Martyn Welch Reviewed-by: Jaehoon Chung Reviewed-by: Fabio Estevam Tested-by: Troy Kisky Acked-by: Troy Kisky --- board/boundary/nitrogen6x/nitrogen6x.c | 72 ---------------------------------- 1 file changed, 72 deletions(-) (limited to 'board') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index d49725daa8c..b3b121bad89 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -161,26 +160,6 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL), - IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */ -}; - static iomux_v3_cfg_t const enet_pads1[] = { IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), @@ -305,57 +284,6 @@ int board_ehci_power(int port, int on) #endif -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : - IMX_GPIO_NR(2, 6); - - gpio_direction_input(gp_cd); - return !gpio_get_value(gp_cd); -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - u32 index = 0; - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[1].max_bus_width = 4; - - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { - switch (index) { - case 0: - SETUP_IOMUX_PADS(usdhc3_pads); - break; - case 1: - SETUP_IOMUX_PADS(usdhc4_pads); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); - if (ret) - return ret; - } - - return 0; -} -#endif - #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) { -- cgit From a1f79c2170ba425972d626cc6351bcdef2ca9d08 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 8 Jun 2020 01:43:47 +0200 Subject: arm: wandboard: move CONFIG_MXC_UART to defconfig For using a debug UART on the Wandboard CONFIG_MXC_UART=y must be set in the .config file. To avoid duplicate definitions move the setting from include/configs/wandboard.h to configs/wandboard_defconfig. Document the debug UART settings in the README. Signed-off-by: Heinrich Schuchardt Reviewed-by: Fabio Estevam --- board/wandboard/README | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'board') diff --git a/board/wandboard/README b/board/wandboard/README index f84f2053375..2d514a72149 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -37,3 +37,13 @@ as the mx6 processor) - Connect the serial cable to the host PC - Power up the board and U-Boot messages will appear in the serial console. + +Debug UART +---------- + +The following settings provide a debug UART for the Wandboard: + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_MXC=y +CONFIG_DEBUG_UART_BASE=0x02020000 +CONFIG_DEBUG_UART_CLOCK=80000000 -- cgit From ba78c25afe96e4038849e9716e41261b9e114ab6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 14 May 2020 18:49:10 +0200 Subject: ARM: imx6: Fetch MAC address in board_init_late() on DH iMX6 PDK2 This is needed to obtain the MAC from EEPROM/OTP only after the final env is populated, otherwise the ethaddr might be overriden. Signed-off-by: Marek Vasut Cc: Claudius Heine Cc: Harald Seiler Cc: Ludwig Zenz Cc: Stefano Babic --- board/dhelectronics/dh_imx6/dh_imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 8f50433f17c..9937d6b0106 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -142,8 +142,6 @@ int board_init(void) /* Enable eim_slow clocks */ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); - setup_dhcom_mac_from_fuse(); - setup_fec_clock(); return 0; @@ -189,6 +187,8 @@ int board_late_init(void) u32 hw_code; char buf[16]; + setup_dhcom_mac_from_fuse(); + hw_code = board_get_hwcode(); switch (get_cpu_type()) { -- cgit From fb0b862e81afd60ee788ac4c8edfddf034d6dd47 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 20 May 2020 13:47:06 +0200 Subject: imx: imx8qm_rom7720_a1: update README Update README to extract firmware from scripts Signed-off-by: Oliver Graute --- board/advantech/imx8qm_rom7720_a1/README | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board') diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README index bff57125897..585fde440d4 100644 --- a/board/advantech/imx8qm_rom7720_a1/README +++ b/board/advantech/imx8qm_rom7720_a1/README @@ -29,6 +29,17 @@ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin $ chmod +x firmware-imx-8.0.bin $ ./firmware-imx-8.0.bin +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 +$ tar -xf imx-sc-firmware-1.1.tar.bz2 +$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + +$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 +$ tar -xf firmware-imx-8.0.tar.bz2 +$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + Build U-Boot ============ -- cgit From 6c3fbf3e456c49c2f43c0c286106a0d4b099b67b Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:22 -0300 Subject: mx6cuboxi: customize board_boot_order to access eMMC In SPL legacy code only one MMC device is created, based on BOOT_CFG register, which can be either SD or eMMC. In this context board_boot_order return always MMC1 when configure to boot from SD/eMMC. After switching to DM both SD and eMMC devices are created based on the information available on DT, but as board_boot_order only returns MMC1 is not possible to boot from eMMC. This patch customizes board_boot_order taking into account BOOT_CFG register to point to correct MMC1 / MMC2 device. Additionally, handle IO mux for the desired boot device. Signed-off-by: Walter Lozano --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'board') diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 59e8b1dca1d..c531fbec71d 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -529,6 +529,54 @@ int board_fit_config_name_match(const char *name) return strcmp(name, tmp_name); } +void board_boot_order(u32 *spl_boot_list) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK; + unsigned int bmode = readl(&src_base->sbmr2); + + /* If bmode is serial or USB phy is active, return serial */ + if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) { + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (boot_mode >> IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD2 + * 0x2 SD3 + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + switch (reg) { + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case 2: + SETUP_IOMUX_PADS(usdhc3_pads); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + } + break; + default: + /* By default use USB downloader */ + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + } + + /* As a last resort, use serial downloader */ + spl_boot_list[1] = BOOT_DEVICE_BOARD; +} + #ifdef CONFIG_SPL_BUILD #include static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { -- cgit From 824e6fe0ae0280cabd9df763fbc3bbaca2682b32 Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Tue, 19 May 2020 15:24:24 -0300 Subject: mx6cuboxi: remove unused code After enabling SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC the MMC initialization code is not longer needed. This patch removes the unused code. Signed-off-by: Walter Lozano --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 65 ------------------------------------ 1 file changed, 65 deletions(-) (limited to 'board') diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index c531fbec71d..ae1c04df87d 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -154,76 +154,11 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } -static struct fsl_esdhc_cfg usdhc_cfg = { - .esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 4, -}; - -static struct fsl_esdhc_cfg emmc_cfg = { - .esdhc_base = USDHC3_BASE_ADDR, - .max_bus_width = 8, -}; - int board_mmc_get_env_dev(int devno) { return devno; } -#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */ - break; - } - - return ret; -} - -static int mmc_init_spl(bd_t *bis) -{ - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD2 - * 0x2 SD3 - */ - switch (reg & 0x3) { - case 0x1: - SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg); - case 0x2: - SETUP_IOMUX_PADS(usdhc3_pads); - emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - gd->arch.sdhc_clk = emmc_cfg.sdhc_clk; - return fsl_esdhc_initialize(bis, &emmc_cfg); - } - - return -ENODEV; -} - -int board_mmc_init(bd_t *bis) -{ - if (IS_ENABLED(CONFIG_SPL_BUILD)) - return mmc_init_spl(bis); - - return 0; -} - #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { -- cgit From 3427f4d2045729c8995b19407daf91ea9a50e4f8 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 9 Dec 2015 18:46:43 +0530 Subject: fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes Correct the PL bitstream loading sequence for zynqaes command by clearing the loaded PL bitstream before loading the new encrypted bitstream using the zynq aes command. This was done by setting the PROG_B same as in case of fpgaload commands. This patch fixes the issue of loading the encrypted PL bitstream onto the PL in which a bitstream has already been loaded successfully. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynq/cmds.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 0c46de7599c..d5e7d70bdf5 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -399,7 +399,8 @@ static int zynq_verify_image(u32 src_ptr) status = zynq_decrypt_load(part_load_addr, part_img_len, part_dst_addr, - part_data_len); + part_data_len, + BIT_NONE); if (status != 0) { printf("DECRYPTION_FAIL\n"); return -1; @@ -438,6 +439,7 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, char *endp; u32 srcaddr, srclen, dstaddr, dstlen; int status; + u8 imgtype = BIT_NONE; if (argc < 5 && argc > cmdtp->maxargs) return CMD_RET_USAGE; @@ -464,7 +466,8 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, if (dstlen % 4) dstlen = roundup(dstlen, 4); - status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2); + status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, + dstlen >> 2, imgtype); if (status != 0) return CMD_RET_FAILURE; -- cgit From b80a476faa3a36ea66a706cf985533792e1e185e Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Tue, 12 Mar 2019 20:20:22 +0530 Subject: fpga: zynqpl: Add zynq aes load & loadp commands Added support for zynq aes load & loadp commands. Signed-off-by: T Karthik Reddy Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynq/cmds.c | 47 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 12 deletions(-) (limited to 'board') diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index d5e7d70bdf5..73e2b0eac7e 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -444,18 +444,37 @@ static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 5 && argc > cmdtp->maxargs) return CMD_RET_USAGE; - srcaddr = simple_strtoul(argv[2], &endp, 16); - if (*argv[2] == 0 || *endp != 0) - return CMD_RET_USAGE; - srclen = simple_strtoul(argv[3], &endp, 16); - if (*argv[3] == 0 || *endp != 0) - return CMD_RET_USAGE; - dstaddr = simple_strtoul(argv[4], &endp, 16); - if (*argv[4] == 0 || *endp != 0) - return CMD_RET_USAGE; - dstlen = simple_strtoul(argv[5], &endp, 16); - if (*argv[5] == 0 || *endp != 0) - return CMD_RET_USAGE; + if (argc == 5) { + if (!strcmp("load", argv[2])) + imgtype = BIT_FULL; + else if (!strcmp("loadp", argv[2])) + imgtype = BIT_PARTIAL; + else + return CMD_RET_USAGE; + + srcaddr = simple_strtoul(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + return CMD_RET_USAGE; + srclen = simple_strtoul(argv[4], &endp, 16); + if (*argv[4] == 0 || *endp != 0) + return CMD_RET_USAGE; + + dstaddr = 0xFFFFFFFF; + dstlen = srclen; + } else { + srcaddr = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + return CMD_RET_USAGE; + srclen = simple_strtoul(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + return CMD_RET_USAGE; + dstaddr = simple_strtoul(argv[4], &endp, 16); + if (*argv[4] == 0 || *endp != 0) + return CMD_RET_USAGE; + dstlen = simple_strtoul(argv[5], &endp, 16); + if (*argv[5] == 0 || *endp != 0) + return CMD_RET_USAGE; + } /* * Roundup source and destination lengths to @@ -520,6 +539,10 @@ static char zynq_help_text[] = " - Decrypts the encrypted image present in source\n" " address and places the decrypted image at\n" " destination address\n" + "aes load \n" + "aes loadp \n" + " if operation type is load or loadp, it loads the encrypted\n" + " full or partial bitstream on to PL respectively.\n" #endif ; #endif -- cgit From fe1eb9945b9d28a91f5a0e20710e3ed5e54d877e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Wed, 22 Apr 2020 16:27:19 +0200 Subject: board: topic-miami: Set FCLK1 to 150MHz In all reference designs the FCLK1 runs at 150MHz, but the bootloader doesn't set it up like that. Set the divider to 8 to generate the correct clock. Fixes (a.o.) the DMA speed being too slow. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +- board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c index 360beaef8ec..e7cc2c2dec6 100644 --- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U), EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U), EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100800U), EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U), EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U), EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c index ae4666f7d59..0f141260ff6 100644 --- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -49,7 +49,7 @@ static unsigned long ps7_clock_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), - EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100800U), EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), -- cgit From dfbe492edef421de09617dc26805fc428440924e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 18 Oct 2019 07:34:13 +0200 Subject: board: zynqmp: Fix for wrong AMS setting by ROM A bug in the ZynqMP bootrom sets the PS_SYSMON_ANALOG_BUS register at 0xFFA50914 to the wrong value 0x3201. This causes the AMS to exchange the PS supply voltages 0 and 1. On Xilinx boards this is not noticeable since these are tied together, it's only really noticeable if banks 500 and 501 have different supplies. Xilinx' tech support reported this undocumented register to be the cause, and this patch applies a fix for all boards by programming the correct value. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'board') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index cb72914adb3..a6cd41af1a0 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -359,6 +359,9 @@ static int multi_boot(void) return 0; } +#define PS_SYSMON_ANALOG_BUS_VAL 0x3210 +#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914 + int board_init(void) { #if defined(CONFIG_ZYNQMP_FIRMWARE) @@ -378,6 +381,9 @@ int board_init(void) printf("EL Level:\tEL%d\n", current_el()); + /* Bug in ROM sets wrong value in this register */ + writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG); + #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ defined(CONFIG_SPL_BUILD)) -- cgit From 39c5cf0e7082fd822b6bf80e896caf8be5a6a10e Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 6 Jun 2019 09:47:41 +0200 Subject: topic: zynqmp: Add support for zynqmp-xilinx-xdp platform XDP - Xilinx Drone Platform is a board for drones or other UAV. Pinmux the SD card by default, and if the SD card detect line is high (inactive) then pinmux the SD1 interface to EMIO instead. SD is placed on extension card and shares connection with on board wife. That means that when SD card is present in the board wifi can't be used. There seems to be an issue with DDR access from PL at 2400MT/s, after updating the PMU and ATF firmware this is causing extremely slow DDR access. Reducing the DDR speed from 2400 to 2133 appears to solve that issue, even though the hardware has proven to be 2400 capable. Signed-off-by: Mike Looijmans Signed-off-by: Michal Simek --- .../psu_init_gpl.c | 1038 ++++++++++++++++++++ 1 file changed, 1038 insertions(+) create mode 100644 board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c (limited to 'board') diff --git a/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c new file mode 100644 index 00000000000..dbed7b789e3 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c @@ -0,0 +1,1038 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU); + psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU); + psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U); + psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U); + mask_delay(1); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U); + mask_delay(5); + psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U); + + mask_delay(1); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U); + + mask_delay(5); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U); + psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U); + psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U); + psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U); + psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U); + psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U); + psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + int count = 0; + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xc] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +static void psu_init_sdio_pinmux(void) +{ + if (Xil_In32(0xFF0A0064U) & (1U << 19)) { + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + + psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U); + + psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U); + } else { + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + } +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + psu_init_sdio_pinmux(); + + if (status == 0) + return 1; + return 0; +} -- cgit From 3ccea69fc495a8e6c529d6c647af4da3775dcb87 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 May 2020 12:50:33 +0200 Subject: arm64: zynqmp: Print multiboot reg in decimal It is better to print multiboot value in decimal because boot images are also composed in decimal not in hex. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a6cd41af1a0..ebb71729081 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -354,7 +354,7 @@ static int multi_boot(void) multiboot = readl(&csu_base->multi_boot); - printf("Multiboot:\t%x\n", multiboot); + printf("Multiboot:\t%d\n", multiboot); return 0; } -- cgit From e20d88bffaa4292f2fec9e03eac91154429c6482 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 27 Apr 2020 11:26:31 +0200 Subject: xilinx: zynqmp: Enable pmufw config reloading PMU FW has functionality to accept and reload configuration object at run time. The patch is adding support for doing it via u-boot prompt. For example: tftpboot 100000 pmu_obj.bin zynqmp pmufw 100000 $filesize The most of pmufw configurations don't allow config reloading. Also official Xilinx PMUFW doens't support this feature properly but the patch should open a way to call PMUFW with this request. Here is example of PMUFW config fragment which enables config reloading. /* SET CONFIG SECTION */ PM_CONFIG_SET_CONFIG_SECTION_ID, /* Section ID */ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Permissions to set config */ Signed-off-by: Michal Simek --- board/xilinx/zynqmp/cmds.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'board') diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index 0f1f26986f2..c0d28a73e45 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -130,8 +130,27 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, } #endif +static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr, size; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + size = simple_strtoul(argv[3], NULL, 16); + flush_dcache_range((ulong)addr, (ulong)(addr + size)); + + zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr, + (size_t)size); + + return 0; +} + static struct cmd_tbl cmd_zynqmp_sub[] = { U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), + U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""), U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), #ifdef CONFIG_DEFINE_TCM_OCM_MMAP @@ -184,6 +203,7 @@ static char zynqmp_help_text[] = " to be initialized. Supported modes will be\n" " lock(0)/split(1)\n" #endif + "zynqmp pmufw address size - load PMU FW configuration object\n" ; #endif -- cgit