mirror/u-boot.git - mirror/u-boot.git

stat options

Commits per author per week (path 'board/nc650/u-boot.lds.debug')

Author	W06 2025	W07 2025	W08 2025	W09 2025	Total
Total	0	0	0	0	0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931

/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ #ifndef __CONFIG_H #define __CONFIG_H /* * T104x RDB board configuration file */ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SECURE_BOOT #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg #else #define CONFIG_SYS_FSL_PBL_PBI \ $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg #endif #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_NAND #ifdef CONFIG_SECURE_BOOT #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along * with U-Boot image. */ #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ CONFIG_U_BOOT_HDR_SIZE) #else #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg #endif #ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #endif #define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg #endif #ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #endif #define CONFIG_SPL_SPI_BOOT #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif #ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg #endif #ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg #endif #ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif #define CONFIG_SPL_MMC_BOOT #endif #endif /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ /* support deep sleep */ #define CONFIG_DEEP_SLEEP #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #ifdef CONFIG_SECURE_BOOT #define CONFIG_RAMBOOT_NAND #define CONFIG_BOOTSCRIPT_COPY_RAM #endif #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 66666666 /* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 /* * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address * (CONFIG_SYS_INIT_L3_VADDR) will be different. */ #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE 256 << 10 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #endif #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull


Period:
Authors: