/*

mode setting sequence done by cirrus drm driver

--- set mode ( 1024 x 768 @ 24 bpp ) ---
vga_cirrus_write_io addr 0x3d4, val 0x11
vga_cirrus_write_io addr 0x3d5, val 0x20
vga_cirrus_write_io addr 0x3d4, val 0x0
vga_cirrus_write_io addr 0x3d5, val 0xa3
vga_cirrus_write_io addr 0x3d4, val 0x1
vga_cirrus_write_io addr 0x3d5, val 0x7f
vga_cirrus_write_io addr 0x3d4, val 0x4
vga_cirrus_write_io addr 0x3d5, val 0x84
vga_cirrus_write_io addr 0x3d4, val 0x5
vga_cirrus_write_io addr 0x3d5, val 0x95
vga_cirrus_write_io addr 0x3d4, val 0x6
vga_cirrus_write_io addr 0x3d5, val 0x24
vga_cirrus_write_io addr 0x3d4, val 0x12
vga_cirrus_write_io addr 0x3d5, val 0xff
vga_cirrus_write_io addr 0x3d4, val 0x9
vga_cirrus_write_io addr 0x3d5, val 0x60
vga_cirrus_write_io addr 0x3d4, val 0x7
vga_cirrus_write_io addr 0x3d5, val 0x79
vga_cirrus_write_io addr 0x3d4, val 0x1a
vga_cirrus_write_io addr 0x3d5, val 0xe0
vga_cirrus_write_io addr 0x3d4, val 0x17
vga_cirrus_write_io addr 0x3d5, val 0x3

vga_cirrus_write_io addr 0x3c4, val 0x7
vga_cirrus_read_io addr 0x3c5, val 0x0
vga_cirrus_write_io addr 0x3c4, val 0x7
vga_cirrus_write_io addr 0x3c5, val 0x15

vga_cirrus_write_io addr 0x3d4, val 0x13
vga_cirrus_write_io addr 0x3d5, val 0x80
vga_cirrus_write_io addr 0x3d4, val 0x1b
vga_cirrus_write_io addr 0x3d5, val 0x32
vga_cirrus_write_io addr 0x3ce, val 0x5
vga_cirrus_write_io addr 0x3cf, val 0x40
vga_cirrus_write_io addr 0x3ce, val 0x6
vga_cirrus_write_io addr 0x3cf, val 0x1

vga_cirrus_read_io addr 0x3c6, val 0xff
vga_cirrus_read_io addr 0x3c6, val 0xff
vga_cirrus_read_io addr 0x3c6, val 0xff
vga_cirrus_read_io addr 0x3c6, val 0xff
vga_cirrus_write_io addr 0x3c6, val 0xc5

--- set base address ( 0 ) ---
vga_cirrus_write_io addr 0x3d4, val 0xc
vga_cirrus_write_io addr 0x3d5, val 0x0
vga_cirrus_write_io addr 0x3d4, val 0xd
vga_cirrus_write_io addr 0x3d5, val 0x0

vga_cirrus_write_io addr 0x3d4, val 0x1b
vga_cirrus_read_io addr 0x3d5, val 0x32
vga_cirrus_write_io addr 0x3d4, val 0x1b
vga_cirrus_write_io addr 0x3d5, val 0x32

vga_cirrus_write_io addr 0x3d4, val 0x1d
vga_cirrus_read_io addr 0x3d5, val 0x0
vga_cirrus_write_io addr 0x3d4, val 0x1d
vga_cirrus_write_io addr 0x3d5, val 0x0

-- unblank --
vga_cirrus_write_io addr 0x3c0, val 0x20

*/

#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h>

#include "cirrus.h"

void cirrus_setmode(volatile uint8_t *mmio)
{
    fprintf(stderr, "setting mode (1024x768 @ 24bpp)\n");
    /* mode */
    mmio[0x3d4 + VGA_OFFSET] = 0x11;
    mmio[0x3d5 + VGA_OFFSET] = 0x20;
    mmio[0x3d4 + VGA_OFFSET] = 0x0;
    mmio[0x3d5 + VGA_OFFSET] = 0xa3;
    mmio[0x3d4 + VGA_OFFSET] = 0x1;
    mmio[0x3d5 + VGA_OFFSET] = 0x7f;
    mmio[0x3d4 + VGA_OFFSET] = 0x4;
    mmio[0x3d5 + VGA_OFFSET] = 0x84;
    mmio[0x3d4 + VGA_OFFSET] = 0x5;
    mmio[0x3d5 + VGA_OFFSET] = 0x95;
    mmio[0x3d4 + VGA_OFFSET] = 0x6;
    mmio[0x3d5 + VGA_OFFSET] = 0x24;
    mmio[0x3d4 + VGA_OFFSET] = 0x12;
    mmio[0x3d5 + VGA_OFFSET] = 0xff;
    mmio[0x3d4 + VGA_OFFSET] = 0x9;
    mmio[0x3d5 + VGA_OFFSET] = 0x60;
    mmio[0x3d4 + VGA_OFFSET] = 0x7;
    mmio[0x3d5 + VGA_OFFSET] = 0x79;
    mmio[0x3d4 + VGA_OFFSET] = 0x1a;
    mmio[0x3d5 + VGA_OFFSET] = 0xe0;
    mmio[0x3d4 + VGA_OFFSET] = 0x17;
    mmio[0x3d5 + VGA_OFFSET] = 0x3;
    mmio[0x3c4 + VGA_OFFSET] = 0x7;
    mmio[0x3c5 + VGA_OFFSET] = 0x15;
    mmio[0x3d4 + VGA_OFFSET] = 0x13;
    mmio[0x3d5 + VGA_OFFSET] = 0x80;
    mmio[0x3d4 + VGA_OFFSET] = 0x1b;
    mmio[0x3d5 + VGA_OFFSET] = 0x32;
    mmio[0x3ce + VGA_OFFSET] = 0x5;
    mmio[0x3cf + VGA_OFFSET] = 0x40;
    mmio[0x3ce + VGA_OFFSET] = 0x6;
    mmio[0x3cf + VGA_OFFSET] = 0x1;
#if 0
    mmio[0x3c6 + VGA_OFFSET];
    mmio[0x3c6 + VGA_OFFSET];
    mmio[0x3c6 + VGA_OFFSET];
    mmio[0x3c6 + VGA_OFFSET];
    mmio[0x3c6 + VGA_OFFSET] = 0xc5;
#endif

    /* base */
    mmio[0x3d4 + VGA_OFFSET] = 0xc;
    mmio[0x3d5 + VGA_OFFSET] = 0x0;
    mmio[0x3d4 + VGA_OFFSET] = 0xd;
    mmio[0x3d5 + VGA_OFFSET] = 0x0;
    mmio[0x3d4 + VGA_OFFSET] = 0x1b;
    mmio[0x3d5 + VGA_OFFSET] = 0x32;
    mmio[0x3d4 + VGA_OFFSET] = 0x1d;
    mmio[0x3d5 + VGA_OFFSET] = 0x0;

    /* dpms */
    mmio[0x3d4 + VGA_OFFSET] = 0x1;
    mmio[0x3d5 + VGA_OFFSET] = 0x0;
    mmio[0x3ce + VGA_OFFSET] = 0xe;
    mmio[0x3cf + VGA_OFFSET] = 0x1;

    /* unblank */
    mmio[0x3c0 + VGA_OFFSET] = 0x20;

    fprintf(stderr, "mode done\n");
    sleep(1);
}