#define VGA_OFFSET (-0x3c0) #define BLT_OFFSET (0x100) #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword #define CIRRUS_MMIO_BLTWIDTH 0x08 // word #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte #define CIRRUS_MMIO_BLTMODE 0x18 // byte #define CIRRUS_MMIO_BLTROP 0x1a // byte #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte #define CIRRUS_BLT_BUSY 0x01 #define CIRRUS_BLT_START 0x02 #define CIRRUS_BLT_RESET 0x04 #define CIRRUS_BLTMODE_BACKWARDS 0x01 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 #define CIRRUS_BLTMODE_COLOREXPAND 0x80 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 #define CIRRUS_ROP_0 0x00 #define CIRRUS_ROP_SRC_AND_DST 0x05 #define CIRRUS_ROP_NOP 0x06 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 #define CIRRUS_ROP_NOTDST 0x0b #define CIRRUS_ROP_SRC 0x0d #define CIRRUS_ROP_1 0x0e #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 #define CIRRUS_ROP_SRC_XOR_DST 0x59 #define CIRRUS_ROP_SRC_OR_DST 0x6d #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad #define CIRRUS_ROP_NOTSRC 0xd0 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda void cirrus_setmode(volatile uint8_t *mmio);