diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-05-15 13:22:26 +0200 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2014-06-04 11:06:58 -0400 |
| commit | 40d03128531e06b35a3836f9346790003692540e (patch) | |
| tree | 0807826d822c4a8eebdcac99174f96e8a1e1cb05 /src/fw/pciinit.c | |
| parent | c029a912d39f82cefc305800b49c933f1789faee (diff) | |
| download | seabios-40d03128531e06b35a3836f9346790003692540e.tar.gz | |
piix: add and use dev-piix.h
Move all definitions for PIIX registers to a single header file,
like there is one already for Q35, and make the naming more
consistent.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'src/fw/pciinit.c')
| -rw-r--r-- | src/fw/pciinit.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 2e6382f9..0ad548fc 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -8,6 +8,7 @@ #include "byteorder.h" // le64_to_cpu #include "config.h" // CONFIG_* #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR +#include "dev-piix.h" // PIIX_* #include "hw/ata.h" // PORT_ATA1_CMD_BASE #include "hw/pci.h" // pci_config_readl #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL @@ -152,8 +153,8 @@ static void piix_isa_bridge_setup(struct pci_device *pci, void *arg) /* activate irq remapping in PIIX */ pci_config_writeb(pci->bdf, 0x60 + i, irq); } - outb(elcr[0], 0x4d0); - outb(elcr[1], 0x4d1); + outb(elcr[0], PIIX_PORT_ELCR1); + outb(elcr[1], PIIX_PORT_ELCR2); dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]); } @@ -229,10 +230,10 @@ static void piix4_pm_config_setup(u16 bdf) // acpi sci is hardwired to 9 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9); - pci_config_writel(bdf, 0x40, acpi_pm_base | 1); - pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */ - pci_config_writel(bdf, 0x90, (acpi_pm_base + 0x100) | 1); - pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */ + pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1); + pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */ + pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1); + pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */ } static int PiixPmBDF = -1; |