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| author | Kevin O'Connor <kevin@koconnor.net> | 2015-03-11 17:45:47 -0400 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2015-03-11 17:45:47 -0400 |
| commit | 5ae3dd6f74e17a7cd06165a75214798b0c606115 (patch) | |
| tree | f5460feb107bcc00e39fb2efe6dc30a79c941b9f /src/romlayout.S | |
| parent | 0fe4c9ee7af5f6bb3a1fcbf1d39116a894600c90 (diff) | |
| download | seabios-5ae3dd6f74e17a7cd06165a75214798b0c606115.tar.gz | |
smp: Fix smp race introduced in 0673b787
In 0673b787 the QEMU SMP init code was changed to run in 32bit mode.
Unfortunately, the transition32 assembler function is not
multi-processor safe, because it modifies the global RTC index
register. This race condition led to sporadic failures when emulating
machines with a large number of processors.
This patch changes the entry_smp code to use a variant of transition32
that does not touch the RTC registers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Diffstat (limited to 'src/romlayout.S')
| -rw-r--r-- | src/romlayout.S | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/romlayout.S b/src/romlayout.S index 6b3aabd9..93b6874e 100644 --- a/src/romlayout.S +++ b/src/romlayout.S @@ -22,7 +22,8 @@ // %edx = return location (in 32bit mode) // Clobbers: ecx, flags, segment registers, cr0, idt/gdt DECLFUNC transition32 -transition32_for_smi: +transition32_nmi_off: + // transition32 when NMI and A20 are already initialized movl %eax, %ecx jmp 1f transition32: @@ -205,7 +206,7 @@ __farcall16: entry_smi: // Transition to 32bit mode. movl $1f + BUILD_BIOS_ADDR, %edx - jmp transition32_for_smi + jmp transition32_nmi_off .code32 1: movl $BUILD_SMM_ADDR + 0x8000, %esp calll _cfunc32flat_handle_smi - BUILD_BIOS_ADDR @@ -216,8 +217,10 @@ entry_smi: DECLFUNC entry_smp entry_smp: // Transition to 32bit mode. + cli + cld movl $2f + BUILD_BIOS_ADDR, %edx - jmp transition32 + jmp transition32_nmi_off .code32 // Acquire lock and take ownership of shared stack 1: rep ; nop |