Allow rom to grow beyond 64K.

If rom is over 64K then use part of e-segment for 32bit code.
Push 32bit code as high as it can go in the f-segment.
Do version building before layoutrom.py - this way layoutrom knows
    full size of rom.
Make layoutrom.py build the full ld script - remove now unused ld
    scripts that just imported the output of layoutrom.py.
Also, use "objdump" instead of "nm" - reduce toolchain requirements.
Enhance tools/checkrom.py so that it can pad bios.bin to size qemu is
    happy with.
Also, add dependencies to build rules for local tools - if tool
    changes automatically rerun it.
Make sure option roms don't overwrite the 32bit code (should the 32bit
    code be in the e-segment).
Make sure shadow code works even if part of the code is in the
    e-segment.

1 files changed, 34 insertions, 32 deletions

diff --git a/src/shadow.c b/src/shadow.c
index daa2e213..f0f97c51 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -23,28 +23,8 @@
 
 // Enable shadowing and copy bios.
 static void
-copy_bios(u16 bdf)
+__make_bios_writable(u16 bdf)
 {
-    pci_config_writeb(bdf, 0x59, 0x30);
-    memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
-}
-
-// Make the 0xc0000-0x100000 area read/writable.
-void
-make_bios_writable()
-{
-    if (CONFIG_COREBOOT)
-        return;
-
-    dprintf(3, "enabling shadow ram\n");
-
-    // Locate chip controlling ram shadowing.
-    int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
-    if (bdf < 0) {
-        dprintf(1, "Unable to unlock ram - bridge not found\n");
-        return;
-    }
-
     // Make ram from 0xc0000-0xf0000 writable
     int clear = 0;
     int i;
@@ -68,24 +48,46 @@ make_bios_writable()
     if (clear)
         memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
 
+    // Make ram from 0xf0000-0x100000 writable
     int reg = pci_config_readb(bdf, 0x59);
-    if (reg & 0x10) {
-        // Ram already present - just enable writes
-        pci_config_writeb(bdf, 0x59, 0x30);
+    pci_config_writeb(bdf, 0x59, 0x30);
+    if (reg & 0x10)
+        // Ram already present.
+        return;
+
+    // Copy bios.
+    memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
+}
+
+// Make the 0xc0000-0x100000 area read/writable.
+void
+make_bios_writable()
+{
+    if (CONFIG_COREBOOT)
+        return;
+
+    dprintf(3, "enabling shadow ram\n");
+
+    // Locate chip controlling ram shadowing.
+    int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
+    if (bdf < 0) {
+        dprintf(1, "Unable to unlock ram - bridge not found\n");
         return;
     }
 
-    // Enable shadowing and copy bios.
-    if (IN_RANGE((u32)copy_bios, BUILD_BIOS_ADDR, BUILD_BIOS_SIZE)) {
-        // Jump to shadow enable function - use the copy in the
-        // temporary storage area so that memory does not change under
-        // the executing code.
-        u32 pos = (u32)copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
+    int reg = pci_config_readb(bdf, 0x59);
+    if (!(reg & 0x10)) {
+        // QEMU doesn't fully implement the piix shadow capabilities -
+        // if ram isn't backing the bios segment when shadowing is
+        // disabled, the code itself wont be in memory.  So, run the
+        // code from the high-memory flash location.
+        u32 pos = (u32)__make_bios_writable - BUILD_BIOS_ADDR + BIOS_SRC_ADDR;
         void (*func)(u16 bdf) = (void*)pos;
         func(bdf);
-    } else {
-        copy_bios(bdf);
+        return;
     }
+    // Ram already present - just enable writes
+    __make_bios_writable(bdf);
 }
 
 // Make the BIOS code segment area (0xf0000) read-only.