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* pci: factor out pci bar allocation.Gerd Hoffmann2020-10-151-0/+6
| | | | | | | Factor out pci bar allocation into a separate pci_setup_alloc() function so it can also be used without running the platform setup code. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: add mmconfig supportGerd Hoffmann2020-03-271-0/+1
| | | | | | | | | | Add support for pci config space access via mmconfig bar. Enable for qemu q35 chipset. Main advantage is that we need only one instead of two io operations per config space access, which translates to one instead of two vmexits for virtualization. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200323145911.22319-3-kraxel@redhat.com
* pciinit: Use %pP shorthand for printing device ids in intel_igd_setup()Kevin O'Connor2019-05-231-12/+9
| | | | | | | | The hardcoded device names can cause false-positives on Windows bios version checks. Use the %pP format to avoid that. Reported-by: Sam Eiderman <shmuel.eiderman@oracle.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* pci: recognize RH PCI legacy bridge resource reservation capabilityJing Liu2018-09-051-21/+29
| | | | | | | | | | | | Enable the firmware recognizing RedHat legacy PCI bridge device ID, so QEMU can reserve additional PCI bridge resource capability. Change the debug level lower to 3 when it is non-QEMU bridge. Signed-off-by: Jing Liu <jing2.liu@linux.intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com> Message-id: 1535100781-3910-4-git-send-email-jing2.liu@linux.intel.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: clean up the debug message for pci capability foundJing Liu2018-09-051-1/+3
| | | | | | | | | | Improve the debug message when QEMU resource reserve cap is not found and when the vendor-id or device-id does't match REDHAT special ones. Signed-off-by: Jing Liu <jing2.liu@linux.intel.com> Message-id: 1535100781-3910-3-git-send-email-jing2.liu@linux.intel.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: fix the return value for truncated capabilityJing Liu2018-09-051-0/+1
| | | | | | | | Return zero when finding truncated capability. Signed-off-by: Jing Liu <jing2.liu@linux.intel.com> Message-id: 1535100781-3910-2-git-send-email-jing2.liu@linux.intel.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: fix 'io hints' capability for RedHat PCI bridgesMarcel Apfelbaum2018-01-161-9/+5
| | | | | | | | | | | | | | | | | | | | Commit ec6cb17f (pci: enable RedHat PCI bridges to reserve additional resources on PCI init) added a new vendor specific PCI capability for RedHat PCI bridges allowing them to reserve additional buses and/or IO/MEM space. When adding the IO hints PCI capability to the pcie-root-port without specifying a value for bus reservation, the subordinate bus computation is wrong and the guest kernel gets messed up. Fix it by returning to prev code if the value for bus reservation is not set. Removed also a wrong debug print "PCI: invalid QEMU resource reserve cap offset" which appears if the 'IO hints' capability is not present. Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
* pci: enable RedHat PCI bridges to reserve additional resources on PCI initAleksandr Bezzubikov2017-09-141-4/+102
| | | | | | | | In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific capability. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
* pci: refactor pci_find_capapibilty to get bdf as the first argument instead ↵Aleksandr Bezzubikov2017-09-141-2/+2
| | | | | | | | | | | of the whole pci_device Refactor pci_find_capability function to get bdf instead of a whole pci_device* as the only necessary field for this function is still bdf. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
* fw/pci: Add support for mapping Intel IGD via QEMUAlex Williamson2016-06-011-0/+48
| | | | | | | | | | | | | | | | | | | | | | QEMU provides two fw_cfg files to support IGD. The first holds the OpRegion data which holds the Video BIOS Table (VBT). This needs to be copied into reserved memory and the address stored in the ASL Storage register of the device at 0xFC offset in PCI config space. The OpRegion is generally 8KB. This file is named "etc/igd-opregion". The second file tells us the required size of the stolen memory space for the device. This space requires 1MB alignment and is generally either 1MB to 8MB depending on hardware config, but may be hundreds of MB for user specified stolen memory. The base address of the reserved memory allocated for this is written back to the Base Data of Stolen Memory register (BDSM) at PCI config offset 0x5C on the device. This file is named "etc/igd-bdsm-size". QEMU documents these fw_cfg entries in docs/igd-assign.txt. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Message-id: 20160517203151.6996.95545.stgit@gimli.home Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* fw/pci: add Q35 S3 supportMarcel Apfelbaum2016-03-071-17/+56
| | | | | | | | | | Following the i440fx example, save the LPC, SMBUS and PCIEXBAR bdfs between OS sleeps and use them to re-configure the corresponding registers. Tested-by: Gal Hammer <ghammer@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
* pci: Split low-level pci code from higher-level 'struct pci_device' codeKevin O'Connor2016-02-031-0/+1
| | | | | | | | | Split pci.c into pci.c and pcidevice.c. The low-level code that interacts directly with the PCI devices remains in pci.c, while functions dealing with the higher level pci_device cache move to pcidevice.c. Only pci.c is needed in 16bit mode. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* pci: Move code in pci.c that is specific to pciinit.c to pciinit.cKevin O'Connor2016-02-031-0/+37
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* pci: Implement '%pP' printf handler for 'struct pci_device' pointersKevin O'Connor2016-02-031-16/+9
| | | | | | | Handle '%pP' format descriptions as a pointer to a 'struct pci_device' and display it in bus:device.function (%02x:%02x.%x) format. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Fix comment typoCao jin2016-02-011-1/+1
| | | | Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
* fw/pci: do not automatically allocate IO region for PCIe bridgesMarcel Apfelbaum2015-12-201-4/+5
| | | | | | | | | | | | | PCIe downstream ports (Root Ports and switches Downstream Ports) appear to firmware as PCI-PCI bridges and a 4K IO space is allocated for them even if there is no device behind them requesting IO space, all that for hotplug purpose. However, PCIe devices can work without IO, so there is no need to allocate IO space for hotplug. Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
* e820: Rename memmap.c to e820map.c and use consistent "e820_" prefixKevin O'Connor2015-10-151-3/+3
| | | | | | | | | Rename memmap.c to e820map.c as the code in that file only deals with maintaining the e820 map. Move all the e820 definitions to new file e820map.h and use a consistent "e820_" prefix on all exported functions. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* ich9: initialise RCBA register through LPC interfacePaulo Alcantara2015-07-141-0/+5
| | | | | | | | | | | This patch initialises root complex register block BAR in order to support TCO watchdog emulation features on QEMU. Cc: Kevin O'Connor <kevin@koconnor.net> Cc: Gerd Hofmann <kraxel@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: allow to loop over capabilitiesGerd Hoffmann2015-06-301-2/+2
| | | | | | | | Add a parameter to pci_find_capability, to specify the start point. This allows to find multiple capabilities of the same type, by calling pci_find_capability again with the offset of the last capability found. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* fw/pci: map memory and IO regions for multiple pci root busesMarcel Apfelbaum2015-03-061-0/+10
| | | | | | | | | For resource sizing and mapping purposes treat devices on extra root buses as if they are on the default root bus (bus 0). Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* fw/pci: scan all buses if extraroots romfile is presentMarcel Apfelbaum2015-03-061-0/+9
| | | | | | | | If there are extra primary root buses, scanning the bus's 0 subtree is not enough. Scan all the range. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: enable SERR# for error forwarding in bridge control registerChen Fan2015-02-241-0/+4
| | | | | | | | | | | | | For PCIe device support AER(Advanced Error Reporting), from the pcie spec 3.0 chapter 6.2.5, ERR_COR, ERR_NONFATAL, and ERR_FATAL can be forwarded from the secondary interface to the primary interface, only require the SERR# Enable bit in the Bridge Control register is set. and at the kernel side, we found only _HPP() method can enable SERR#, So here we want to turn on this bit. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* pciinit: Fix build warning in mch_pci_slot_get_irq()Kevin O'Connor2014-11-121-16/+7
| | | | | | | | Some old versions of gcc warn that 'irq might be used uninitialized'. Replace the switch statement with an if statement to suppress the warning. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* hw/pci: reserve IO and mem for pci express downstream ports with no devices ↵Marcel Apfelbaum2014-07-011-2/+32
| | | | | | | | | | | | | attached Commit c6e298e1f12e0f4ca02b6da5e42919ae055f6830 hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached introduced support for hot-plugging devices behind pci-2-pci bridges. Extend hotplug support also for pci express downstream ports. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* piix: add and use dev-piix.hPaolo Bonzini2014-06-041-6/+7
| | | | | | | | Move all definitions for PIIX registers to a single header file, like there is one already for Q35, and make the naming more consistent. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Allow using full io region on q35.Gerd Hoffmann2014-05-201-7/+9
| | | | | | | | | | If qemu is new enough to support acpi table loading, then go move pmbase out of the way. This allows to use the whole 0x1000 -> 0xffff io address space on q35. piix has hotplug ports in the 0xa000 -> 0xafff area, so we can't do the same there. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* acpi: remove PORT_ACPI_PM_BASE constantGerd Hoffmann2014-05-201-8/+8
| | | | | | Use the new acpi_pm_base variable instead. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* hw/pci: check if pci2pci bridges implement optional limit registersMarcel Apfelbaum2014-04-161-7/+2
| | | | | | | | | <I/O Base Register, I/O Limit Register> pair and <Prefetchable Memory Base Register, Prefetchable Memory Limit Register> pair are both optional. Do not reserve ranges if the above registers are not implemented. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
* hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attachedMarcel Apfelbaum2014-04-161-0/+3
| | | | | | | | | If a pci-2-pci bridge supports hot-plug functionality but there are no devices connected to it, reserve IO/mem in order to be able to attach devices later. Do not waste space, use minimum allowed. Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
* pci: improve io address space allocationGerd Hoffmann2014-01-271-5/+40
| | | | | | | | | | | | | | | | This patch improves the io address space allocation. It adds a check that the region above 0xc000 which is traditionally used for pci io is actually big enougth. If it isn't it tries the larger window at 0x1000. If that is to small too it errors out. When creating guests with multiple pci-pci bridges (and devices with io regions behind them) the 0xc000 -> 0xffff region quickly becomes too small. While being at it document the io address space layout used by qemu/seabios. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Minor - pciinit.c - order header files and use static on local functions.Kevin O'Connor2014-01-151-6/+6
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* resume: restore piix pm config registers after resumeMarcel Apfelbaum2014-01-151-3/+21
| | | | | | | | | | | | | | | | On resume, the OS queries the power management event that caused it. In order to complete this task, it executes some reads to the piix pm io space. This all happens before the OS has a chance to restore the PCI config space for devices, so it is bios's responsibility to make sure the pm IO space is configured correctly. (During suspend, the piix pm configuration space is lost). Note: For 'ordinary' pci devices the config space is saved by the OS on sleep and restored on resume. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
* pci: map 64-bit BARs at location provided by emulatorGerd Hoffmann2013-11-291-1/+5
| | | | | | | | | | | | | | | | | Currently 64-bit PCI BARs are unconditionally mapped by BIOS right over 4G + RamSizeOver4G location, which doesn't allow to reserve extra space before 64-bit PCI window. For memory hotplug an extra RAM space might be reserved after present 64-bit RAM end and BIOS should map 64-bit PCI BARs after it. Introduce "etc/reserved-memory-end" romfile to provide BIOS a hint where it should start mapping of 64-bit PCI BARs. If romfile is missing, BIOS reverts to legacy behavior and starts mapping after high memory. Based-on-patch-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-By: Igor Mammedov <imammedo@redhat.com>
* pci: log pci windowsGerd Hoffmann2013-11-291-0/+2
| | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: tweak + comment minimum allocationsGerd Hoffmann2013-11-291-3/+3
| | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: align 64bit pci regions to 1GGerd Hoffmann2013-11-291-2/+7
| | | | | | So they are hugepage aligned. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: don't map usb host adapters above 4GGerd Hoffmann2013-11-291-0/+2
| | | | | | Otherwise our xhci driver has trouble accessing the mmio registers. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* pci: don't reorder entries when moving to 64bit listGerd Hoffmann2013-11-291-0/+1
| | | | | | | Otherwise the 64bit bars are not mapped in largest first order, thereby messing up the alignment. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* Remove ioport.h; disperse its contents to other header files.Kevin O'Connor2013-09-281-1/+2
| | | | | | | Move the inb(), insb(), etc. code from ioport.h to x86.h. Move the PORT_* definitions to their appropriate hardware files. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Move fw/acpi.h to std/acpi.h.Kevin O'Connor2013-09-181-1/+0
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Move function definitions for output.c from util.h to new file output.h.Kevin O'Connor2013-09-181-6/+7
| | | | | | Also, sort the order of include files in the c files. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Move malloc code from pmm.c to new files malloc.c and malloc.h.Kevin O'Connor2013-09-181-0/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Rename util.c to string.c and introduce string.h.Kevin O'Connor2013-09-181-0/+1
| | | | Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
* Move code cenetered around firmware initialization to src/fw/Kevin O'Connor2013-09-021-0/+843
Move many C files from the src/ directory to the new src/fw/ directory. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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