| Commit message (Collapse) | Author | Age | Files | Lines |
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since QEMU_CFG_NB_CPUS not going away anytime soon
and serves the same purpose as just added "etc/boot-cpus" fw_cfg
drop support for "etc/boot-cpus" while this code is not
in use yet (i.e. QEMU with "etc/boot-cpus" hasn't been released)
and reuse QEMU_CFG_NB_CPUS instead of it.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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SDM[*1] says that if there are CPUs with APIC ID
greater than 254, BIOS is to pass control to OS
in x2APIC mode. Use the fact that QEMU passes in
"etc/max-cpus" max possible "APIC ID + 1" to
detect need for x2APIC mode. Also instead of
CMOS_BIOS_SMP_COUNT which is limited to 256 CPUs
use a new rom file "etc/boot-cpus" that QEMU
supporting more than 256 CPUs will provide.
*1) SDM: Volume 3: EXTENDED XAPIC (X2APIC):
Initialization by System Software
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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Signed-off-by: "Kevin O'Connor" <kevin@koconnor.net>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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Currently the MTRRs and MSR_IA32_FEATURE_CONTROL are not restored on S3
resume. Because these have to be applied to all processors, SMP setup
has to be added to S3 resume.
There are two differences between the boot and resume paths. First,
romfile_* is not usable in the resume paths so we separate out the
remaining common code to a new smp_scan function. Second, smp_msr has
to be walked on the BSP as well, so we extract that out of handle_smp
and into a new function smp_write_msrs. Then, resume can call
smp_write_msrs on the BSP followed by smp_scan to initialize the APs.
Reported-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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OS usually expects BIOS to set certain bits in MSR_IA32_FEATURE_CONTROL
for some features (e.g. VMX and LMCE). QEMU provides a fw_cfg file
"etc/msr_feature_control" to advise bits that should be set in
MSR_IA32_FEATURE_CONTROL. If this file exists, SeaBIOS will set the
advised bits in that MSR.
Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20160622065324.23812-1-haozhong.zhang@intel.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Always enable caching at start of 32bit code and always make sure the
paging flag is off. Because this alters the cr0 register, perform a
backup and restore of it when using call32().
Also, rename get/setcr0() to cr0_read/write() to more closely match
other register access functions.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Add CONFIG_ checks around the handle_smi/handle_smp functions.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Change the multi-processor init code to trampoline into 32bit mode on
each of the additional processors. Implement an atomic lock so that
each processor performs its initialization serially.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Group the Real Time Clock code into hw/rtc.[ch].
Also, use rtc_read/write/mask function naming (instead of
inb/outb_cmos) to be more consistent with other register accessors.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Also, sort the order of include files in the c files.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Move many C files from the src/ directory to the new src/fw/ directory.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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