diff options
| -rw-r--r-- | conformance.tex | 1 | ||||
| -rw-r--r-- | content.tex | 22 |
2 files changed, 23 insertions, 0 deletions
diff --git a/conformance.tex b/conformance.tex index 4524237..0ac58aa 100644 --- a/conformance.tex +++ b/conformance.tex @@ -214,6 +214,7 @@ A PCI device MUST conform to the following normative statements: \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Notification capability} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Device-specific configuration} +\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / Non-transitional Device With Legacy Driver} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration} diff --git a/content.tex b/content.tex index d481359..1476b0e 100644 --- a/content.tex +++ b/content.tex @@ -689,6 +689,8 @@ The fields are interpreted as follows: #define VIRTIO_PCI_CAP_DEVICE_CFG 4 /* PCI configuration access */ #define VIRTIO_PCI_CAP_PCI_CFG 5 +/* Shared memory region */ +#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 \end{lstlisting} Any other value is reserved for future use. @@ -1077,6 +1079,26 @@ any device type which has a device-specific configuration. The \field{offset} for the device-specific configuration MUST be 4-byte aligned. +\subsubsection{Shared memory capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability} + +Shared memory regions \ref{sec:Basic Facilities of a Virtio +Device / Shared Memory Regions} are enumerated on the PCI transport +as a sequence of VIRTIO_PCI_CAP_SHARED_MEMORY_CFG capabilities, one per region. + +The capability is defined by a struct virtio_pci_cap64 and +utilises the \field{cap.id} to allow multiple shared memory +regions per device. +The identifier in \field{cap.id} does not denote a certain order of +preference; it is only used to uniquely identify a region. + +\devicenormative{\paragraph}{Device-specific configuration}{Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability} + +The region defined by the combination of the \field {cap.offset}, +\field {cap.offset_hi}, and \field {cap.length}, \field +{cap.length_hi} fields MUST be contained within the declared bar. + +The \field{cap.id} MUST be unique for any one device instance. + \subsubsection{PCI configuration access capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability} The VIRTIO_PCI_CAP_PCI_CFG capability |