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authorMichael Brown <mcb30@ipxe.org>2014-04-22 13:12:54 +0100
committerMichael Brown <mcb30@ipxe.org>2014-04-22 13:12:54 +0100
commit27884298a39553aa0b9b336493c988cf54d73f77 (patch)
treecd34aee6b6cb35a796f3d7524c7097e3ceac77af /src/drivers/net/intel.h
parent93acb5d8d0635b8f7726bd993cde4a90a6b1d723 (diff)
downloadipxe-27884298a39553aa0b9b336493c988cf54d73f77.tar.gz
[intel] Avoid completely filling the TX descriptor ring
It is unclear from the datasheets whether or not the TX ring can be completely filled (i.e. whether writing the tail value as equal to the current head value will cause the ring to be treated as completely full or completely empty). It is very plausible that this edge case could differ in behaviour between real hardware and the many implementations of an emulated Intel NIC found in various virtual machines. Err on the side of caution and always leave at least one ring entry empty. Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/intel.h')
-rw-r--r--src/drivers/net/intel.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/drivers/net/intel.h b/src/drivers/net/intel.h
index 20b4255e..8ce9ea97 100644
--- a/src/drivers/net/intel.h
+++ b/src/drivers/net/intel.h
@@ -156,6 +156,9 @@ enum intel_descriptor_status {
*/
#define INTEL_NUM_TX_DESC 16
+/** Transmit descriptor ring maximum fill level */
+#define INTEL_TX_FILL ( INTEL_NUM_TX_DESC - 1 )
+
/** Receive/Transmit Descriptor Base Address Low (offset) */
#define INTEL_xDBAL 0x00