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| author | Tomer Maimon <tmaimon77@gmail.com> | 2020-11-19 10:00:02 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-11-23 17:13:41 +0100 |
| commit | b2d91953b66c724eaf8d7f84f37c006d966f67ac (patch) | |
| tree | 59e6d8b26eb6b66fc922cb447f782979b7b29aac | |
| parent | 1e548b67828087a29c6b8294629c1620826fba15 (diff) | |
| download | linux-b2d91953b66c724eaf8d7f84f37c006d966f67ac.tar.gz | |
ARM: dts: add Nuvoton NPCM730 device tree
Add Nuvoton NPCM730 SoC device tree.
The Nuvoton NPCN730 SoC is a part of the
Nuvoton NPCM7xx SoCs family.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Benjamin Fair <benjaminfair@google.com>
Link: https://lore.kernel.org/r/20201119080002.100342-1-tmaimon77@gmail.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; |