diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2022-09-16 08:28:36 -0700 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-09-17 12:21:21 +0800 |
| commit | 2069c5265bb369c155b92c4ddf50ae7cc7e592c3 (patch) | |
| tree | 38f4a9d72f00884d26de2f0467dc197c94c485b2 /arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | |
| parent | 6769089ecb5073b0896addffe72c89a4d80258c9 (diff) | |
| download | linux-2069c5265bb369c155b92c4ddf50ae7cc7e592c3.tar.gz | |
ARM: dts: imx6qdl-gw52xx: add CAN regulator
The GW52xx has a transceiver with a STBY pin connected to an IMX6 GPIO.
Configure this as a regulator to drive it low when CAN is in use.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-gw52xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index b1df2beb2832..728810b9d677 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -137,6 +137,16 @@ regulator-always-on; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -170,6 +180,7 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; status = "okay"; }; @@ -612,7 +623,6 @@ fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ >; }; @@ -702,6 +712,12 @@ >; }; + pinctrl_reg_can1: regcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 |