diff options
| author | Paul Elder <paul.elder@ideasonboard.com> | 2022-04-06 17:34:01 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-05-05 09:34:33 +0800 |
| commit | 29f440a7bda8df98c595f6ac29cd196fa1df394a (patch) | |
| tree | 4a70f1c7283cac42d2d2cb4167e746f0530aa9b0 /arch/arm64/boot/dts/freescale | |
| parent | 9d89189d5227507a05a6029818e1a2e2b074522a (diff) | |
| download | linux-29f440a7bda8df98c595f6ac29cd196fa1df394a.tar.gz | |
arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a0b4957f7a16..ed75bd30d9af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1025,6 +1025,44 @@ #size-cells = <1>; ranges; + media_blk_ctrl: blk-ctrl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", + "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&pgc_mediamix>, + <&pgc_mipi_phy1>, + <&pgc_mipi_phy1>, + <&pgc_mediamix>, + <&pgc_mediamix>, + <&pgc_mipi_phy2>, + <&pgc_mediamix>, + <&pgc_ispdwp>, + <&pgc_ispdwp>, + <&pgc_mipi_phy2>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", + "lcdif1", "isi", "mipi-csi2", + "lcdif2", "isp", "dwe", + "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", + "disp1", "disp2", "isp", "phy"; + + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + + #power-domain-cells = <1>; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; |