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| author | Catalin Marinas <catalin.marinas@arm.com> | 2022-09-30 09:18:26 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-09-30 09:18:26 +0100 |
| commit | 53630a1f6186e9df5fb75e9b55328e22b64de150 (patch) | |
| tree | cce45ad34594ae21ee6b2f7b37e6aadfc00715ec /arch/arm64/kernel/cpufeature.c | |
| parent | c704cf27a1adc5fa40fb8e40b5617bdca889a419 (diff) | |
| parent | a0caebbd04602cb7d28f6f316213a915ffab92a2 (diff) | |
| download | linux-53630a1f6186e9df5fb75e9b55328e22b64de150.tar.gz | |
Merge branch 'for-next/misc' into for-next/core
* for-next/misc:
: Miscellaneous patches
arm64/kprobe: Optimize the performance of patching single-step slot
ARM64: reloc_test: add __init/__exit annotations to module init/exit funcs
arm64/mm: fold check for KFENCE into can_set_direct_map()
arm64: uaccess: simplify uaccess_mask_ptr()
arm64: mte: move register initialization to C
arm64: mm: handle ARM64_KERNEL_USES_PMD_MAPS in vmemmap_populate()
arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()
arm64: support huge vmalloc mappings
arm64: spectre: increase parameters that can be used to turn off bhb mitigation individually
arm64: run softirqs on the per-CPU IRQ stack
arm64: compat: Implement misalignment fixups for multiword loads
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 5d0527ba0804..a51edf3c0214 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2043,7 +2043,8 @@ static void bti_enable(const struct arm64_cpu_capabilities *__unused) static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) { sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); - isb(); + + mte_cpu_setup(); /* * Clear the tags in the zero page. This needs to be done via the |