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| author | Anup Patel <Anup.Patel@wdc.com> | 2019-04-25 08:38:41 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:11 -0700 |
| commit | a3182c91ef4e7dda90ff080a4132efd3ecb8786a (patch) | |
| tree | 5309b2480f3c6bb9e6df4d7921c7a71ce18dcc4d /arch/riscv/kernel/perf_event.c | |
| parent | 6dcaf00487ca10d87e53fc8decb2e30f113c955d (diff) | |
| download | linux-a3182c91ef4e7dda90ff080a4132efd3ecb8786a.tar.gz | |
RISC-V: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/perf_event.c')
| -rw-r--r-- | arch/riscv/kernel/perf_event.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea..91626d9ae5f2 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -185,10 +185,10 @@ static inline u64 read_counter(int idx) switch (idx) { case RISCV_PMU_CYCLE: - val = csr_read(cycle); + val = csr_read(CSR_CYCLE); break; case RISCV_PMU_INSTRET: - val = csr_read(instret); + val = csr_read(CSR_INSTRET); break; default: WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); |