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authorMax Filippov <jcmvbkbc@gmail.com>2018-11-27 16:27:47 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2018-12-04 14:08:11 -0800
commitcad6fade6e78030e60188da3f18090577daa9243 (patch)
tree4e2a429c4ba70161706227a3b195832201617ffd /arch/xtensa/include/asm/coprocessor.h
parentc066cc8af9de8f749d29f75ad8c1c37d565f32b7 (diff)
downloadlinux-cad6fade6e78030e60188da3f18090577daa9243.tar.gz
xtensa: clean up WSR*/RSR*/get_sr/set_sr
WSR and RSR are too generic and collide with other macro definitions in the kernel causing warnings in allmodconfig builds. Drop WSR and RSR macros and WSR_* and RSR_* variants. Change get_sr and set_sr to xtensa_get_sr and xtensa_set_sr. Fix up users. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/coprocessor.h')
-rw-r--r--arch/xtensa/include/asm/coprocessor.h20
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h
index eafe986a0246..6712929a27c9 100644
--- a/arch/xtensa/include/asm/coprocessor.h
+++ b/arch/xtensa/include/asm/coprocessor.h
@@ -12,7 +12,6 @@
#ifndef _XTENSA_COPROCESSOR_H
#define _XTENSA_COPROCESSOR_H
-#include <linux/stringify.h>
#include <variant/core.h>
#include <variant/tie.h>
#include <asm/types.h>
@@ -90,19 +89,6 @@
#ifndef __ASSEMBLY__
-
-#if XCHAL_HAVE_CP
-
-#define RSR_CPENABLE(x) do { \
- __asm__ __volatile__("rsr %0, cpenable" : "=a" (x)); \
- } while(0);
-#define WSR_CPENABLE(x) do { \
- __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \
- } while(0);
-
-#endif /* XCHAL_HAVE_CP */
-
-
/*
* Additional registers.
* We define three types of additional registers:
@@ -162,12 +148,6 @@ extern void coprocessor_flush(struct thread_info*, int);
extern void coprocessor_release_all(struct thread_info*);
extern void coprocessor_flush_all(struct thread_info*);
-static inline void coprocessor_clear_cpenable(void)
-{
- unsigned long i = 0;
- WSR_CPENABLE(i);
-}
-
#endif /* XTENSA_HAVE_COPROCESSORS */
#endif /* !__ASSEMBLY__ */