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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-09-27 12:11:23 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wenst@chromium.org> | 2022-09-29 12:06:34 +0800 |
| commit | a5f7bf5458c2cf6730106e16a6373638a0e5ed1e (patch) | |
| tree | 65e49cdb67647944c4ef8594e18e3ab4180963bc /drivers/clk/mediatek | |
| parent | ae333e63a2474a8277c9c34709615a40e46d2bb8 (diff) | |
| download | linux-a5f7bf5458c2cf6730106e16a6373638a0e5ed1e.tar.gz | |
clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
The MFG_BG3D is a gate to enable/disable clock output to the GPU,
but the actual output is decided by multiple muxes; in particular:
mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and
"fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the
26MHz clock and various system PLLs.
The clock gate comes after all the muxes, so its parent is
mfg_ck_fast_reg, not top_mfg_core_tmp.
Reparent MFG_BG3D to the latter to match the hardware and add the
CLK_SET_RATE_PARENT flag to it: this way we ensure propagating
rate changes that are requested on MFG_BG3D along its entire clock
tree.
Fixes: 35016f10c0e5 ("clk: mediatek: Add MT8195 mfgcfg clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8195-mfg.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c index 9411c556a5a9..c94cb71bd9b9 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -17,10 +17,12 @@ static const struct mtk_gate_regs mfg_cg_regs = { }; #define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr, \ + CLK_SET_RATE_PARENT) static const struct mtk_gate mfg_clks[] = { - GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0), + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_ck_fast_ref", 0), }; static const struct mtk_clk_desc mfg_desc = { |