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| author | Sekhar Nori <nsekhar@ti.com> | 2018-05-07 17:04:57 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-15 15:33:52 -0700 |
| commit | a714dceb721407c2a5d2887938f37e34ed00669c (patch) | |
| tree | 8fa1e5b8db61828c25a5d1346abf28854ecfff36 /drivers/clk/renesas/r8a77990-cpg-mssr.c | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
| download | linux-a714dceb721407c2a5d2887938f37e34ed00669c.tar.gz | |
clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
USB0 48MHz PHY clock registration fails on DA830 because the
da8xx-cfgchip clock driver cannot get a reference to USB0
LPSC clock.
The USB0 LPSC needs to be enabled during PHY clock enable. Setup
the clock lookup correctly to fix this.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/renesas/r8a77990-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions