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| author | Dmitry Osipenko <digetx@gmail.com> | 2020-03-19 22:02:19 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-12 22:48:42 +0200 |
| commit | 9157abe74b05b9c2ede8f07ad4c7f89b717ff303 (patch) | |
| tree | d560cd35b479e4b62a427548eb06a05f2a571922 /drivers/clk/tegra/clk.h | |
| parent | 1641567920fc363be971f9059f3e7afc58a0dda6 (diff) | |
| download | linux-9157abe74b05b9c2ede8f07ad4c7f89b717ff303.tar.gz | |
clk: tegra: pll: Add pre/post rate-change hooks
There is a need to temporarily re-parent CCLK away from PLLX if PLLX's
rate is about to change. The newly introduced PLL pre/post rate-change
hooks allow to handle such case.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 659c0be03b2e..87a6fb21aafa 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -266,6 +266,10 @@ struct tegra_clk_pll; * disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. + * @pre_rate_change: Callback which is invoked just before changing + * PLL's rate. + * @post_rate_change: Callback which is invoked right after changing + * PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -342,6 +346,8 @@ struct tegra_clk_pll_params { void (*set_defaults)(struct tegra_clk_pll *pll); int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg); + int (*pre_rate_change)(void); + void (*post_rate_change)(void); }; #define TEGRA_PLL_USE_LOCK BIT(0) |