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| author | Yong Zhao <Yong.Zhao@amd.com> | 2020-03-04 16:46:13 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-05-01 15:19:07 -0400 |
| commit | 5c180eb910df3c635e22f5327fd074aafafc7523 (patch) | |
| tree | b4f2b584c7ac93860d46c932c3269f4273a7cb7f /drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | |
| parent | 942a0dd2d6d5b1586784e1ff2c056382ee05a9fa (diff) | |
| download | linux-5c180eb910df3c635e22f5327fd074aafafc7523.tar.gz | |
drm/amdgpu: Rename amdgpu_gfx_kcq_queue_mask_transform()
Rename it to amdgpu_queue_mask_bit_to_set_resource_bit() to be more
specific about its functionality. KFD will use it later.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index ed212c070e8e..d612033a23ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -48,7 +48,7 @@ int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, return bit; } -void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, +void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, int *mec, int *pipe, int *queue) { *queue = bit % adev->gfx.mec.num_queue_per_pipe; @@ -274,7 +274,7 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) continue; - amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); + amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); /* * 1. Using pipes 2/3 from MEC 2 seems cause problems. @@ -485,17 +485,17 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) return amdgpu_ring_test_helper(kiq_ring); } -int amdgpu_gfx_kcq_queue_mask_transform(struct amdgpu_device *adev, +int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, int queue_bit) { int mec, pipe, queue; - int queue_kcq_bit = 0; + int set_resource_bit = 0; - amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); + amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); - queue_kcq_bit = mec * 4 * 8 + pipe * 8 + queue; + set_resource_bit = mec * 4 * 8 + pipe * 8 + queue; - return queue_kcq_bit; + return set_resource_bit; } int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) @@ -520,7 +520,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) break; } - queue_mask |= (1ull << amdgpu_gfx_kcq_queue_mask_transform(adev, i)); + queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); } DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, |