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| author | Likun Gao <Likun.Gao@amd.com> | 2019-11-20 16:21:22 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:09 -0400 |
| commit | 25fc05648f49e083e3cf031626b8ecf86fca5dd1 (patch) | |
| tree | 6db5b0549c969e8e27fefdd2e8e06eb5b10548e8 /drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h | |
| parent | 83a0c342e04adca17eb89a75889ee295d8b82c3e (diff) | |
| download | linux-25fc05648f49e083e3cf031626b8ecf86fca5dd1.tar.gz | |
drm/amdgpu/mes: correct register offset for sienna_cichlid
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v3_0.h')
0 files changed, 0 insertions, 0 deletions