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| author | Martin Leung <martin.leung@amd.com> | 2019-07-17 16:08:19 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:54:27 -0500 |
| commit | 5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e (patch) | |
| tree | 62aa9ea986f025062d7ed0dd8b45708aca89af26 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | |
| parent | 39bdac36cc139dfaf4ff324250319b79c6c224b8 (diff) | |
| download | linux-5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e.tar.gz | |
drm/amd/display: enabling seamless boot sequence for dcn2
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes
[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.
This is part 2 of 2 for seamless boot NV10
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index 02599eb92ca6..66c08d05da0e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -539,6 +539,10 @@ struct dcn_otg_state { void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s); +bool optc1_is_matching_timing( + struct timing_generator *tg, + const struct dc_crtc_timing *otg_timing); + bool optc1_validate_timing( struct timing_generator *optc, const struct dc_crtc_timing *timing); |