diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-09-11 16:31:26 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-09-12 10:42:38 +0100 |
| commit | 74689ddfb7574e2bf08c7206a4ab0dff04978b05 (patch) | |
| tree | 00b143e9e09773bf2f49b1e13548c8ad555cca4e /drivers/gpu | |
| parent | 249778704c01384d76984d83e6d6377ac96b2cc4 (diff) | |
| download | linux-74689ddfb7574e2bf08c7206a4ab0dff04978b05.tar.gz | |
drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk
On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.
Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190911133129.27466-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 13779b6029f5..6fc8e3c0cfba 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, u32 divider; int div; + bxt_de_pll_readout(dev_priv, cdclk_state); + if (INTEL_GEN(dev_priv) >= 12) cdclk_state->bypass = cdclk_state->ref / 2; else if (INTEL_GEN(dev_priv) >= 11) @@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, else cdclk_state->bypass = cdclk_state->ref; - bxt_de_pll_readout(dev_priv, cdclk_state); if (cdclk_state->vco == 0) { cdclk_state->cdclk = cdclk_state->bypass; goto out; |