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| author | Pali Rohár <pali@kernel.org> | 2022-02-22 16:50:24 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2022-02-22 16:04:20 +0000 |
| commit | e3e13c9135da969cfe1666a9f24e76b589d5652b (patch) | |
| tree | 6be2037c1ffe9b5656ec2fff692f06e3c7509db0 /drivers/pci/controller/pci-mvebu.c | |
| parent | 2a81dd9fd9b0b42b42ba7484baf6feb7b4d94d2e (diff) | |
| download | linux-e3e13c9135da969cfe1666a9f24e76b589d5652b.tar.gz | |
PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge
Register with Subsystem Device/Vendor ID is at offset 0x2c. Export is via
emulated bridge.
After this change Subsystem ID is visible in lspci output at line:
Capabilities: [40] Subsystem
Link: https://lore.kernel.org/r/20220222155030.988-7-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/pci-mvebu.c')
| -rw-r--r-- | drivers/pci/controller/pci-mvebu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index d0a75c3b78c3..566d8382afe6 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -32,6 +32,7 @@ #define PCIE_DEV_REV_OFF 0x0008 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) +#define PCIE_SSDEV_ID_OFF 0x002c #define PCIE_CAP_PCIEXP 0x0060 #define PCIE_HEADER_LOG_4_OFF 0x0128 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) @@ -731,6 +732,7 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) struct pci_bridge_emul *bridge = &port->bridge; u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF); u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); + u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF); u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); @@ -752,6 +754,8 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) */ bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver); + bridge->subsystem_vendor_id = ssdev_id & 0xffff; + bridge->subsystem_id = ssdev_id >> 16; bridge->has_pcie = true; bridge->data = port; bridge->ops = &mvebu_pci_bridge_emul_ops; |